CN111463203A - Memory with Image Recognition - Google Patents

Abstract

The memory with image recognition function is an extension of the distributed mode processor, which performs local image retrieval on the user image data stored by itself according to the input image model (such as the image to be found). The memory contains a plurality of memory processing units, each memory processing unit containing a pattern processing circuit including an image recognition circuit and at least one three-dimensional memory (3D-M) array storing at least a portion of the image data. All transistors in the mode processing circuit are located in a semiconductor substrate; none of the memory cells in the 3D-M array are located in any semiconductor substrate.

Description

Memory with Image Recognition

This application is a divisional application for an invention patent application with an application number of 201710130887.X (for the divisional application number 201710460367.5) and an application date of March 7, 2017.

technical field

The present invention relates to the field of integrated circuits, more specifically, to a memory with image recognition function.

Background technique

Pattern matching and pattern recognition refer to finding patterns in the target pattern (the pattern to be retrieved, target pattern) that are the same as or similar to the retrieval pattern (the pattern used for retrieval, the search pattern). Among them, pattern matching requires finding the same pattern, and pattern recognition only requires finding close patterns. Unless otherwise specified, this specification does not distinguish between pattern matching and pattern recognition, and uses pattern processing to collectively refer to various operations performed on patterns.

Pattern processing, including pattern matching and pattern recognition, is widely used. Commonly used pattern processing includes string matching, code matching, speech recognition, and image recognition. String matching is widely used in big data analysis (such as financial data analysis, e-commerce data analysis, bioinformatics) and other fields: find and retrieve strings from big data (currently mostly text databases, containing target strings), and perform Statistical Analysis. Code matching is widely used in anti-malware (such as network security, computer antivirus) and other fields: finding virus signatures from network packets or checking whether network packets conform to network rules, thereby Determines whether network packets are secure. Speech recognition matches speech signals collected by speech sensors or stored in a speech archive with an acoustic model library and a language model library. Image recognition matches the image signal collected by the image sensor or stored in the image archive with the image model library.

With the advent of the era of big data, the traditional schema repository (including retrieval schema repository and target schema repository) has become a large database (TB level to PB level, even EB level): Retrieval schema repository (including all schemas used for retrieval) The amount of data in the target schema repository (including all retrieved schemas, usually the user database) is even larger. The von Neumann architecture currently used by computers can no longer meet the requirements for pattern processing in the era of big data. In the vonNeumann architecture, the processor used to process the pattern and the memory used to store the pattern are separated: the memory (such as hard disk, optical disc, tape, etc.) is only used to store the pattern data, and cannot perform any pattern processing on it; all All mode processing is done by external processors (such as CPU, GPU). As we all know, the bandwidth between the separate processor and memory is limited, and it takes a long time just to read all the data from the pattern library, let alone process and analyze them. As a result, pattern processing for large pattern libraries can take a long time.

A typical application of pattern processing is image recognition. One means of image recognition is to perform pattern recognition on user images according to the image model library. During recognition, the pattern processor compares the user image data with the image models in the image model library to find the closest image model. In traditional computer architecture, user image data is stored in external memory (eg hard disk). The external memory is just a simple memory, which itself does not have any image recognition function. When a new image model needs to be recognized, it is necessary to read all the user image data in the computer hard disk into the processor for image recognition. Due to the limited number of cores of traditional image processors (such as CPU and GPU), the low parallelism of image recognition, and the time-consuming reading of user image data from external memory, the traditional computer architecture is inefficient in processing image recognition.

SUMMARY OF THE INVENTION

The main purpose of the present invention is to improve the efficiency of image recognition.

Another object of the present invention is to provide a memory capable of efficiently and also having an image recognition function.

In order to achieve these and other purposes, the present invention proposes a memory with image recognition function, which is an extension of the distributed mode processor: the memory can not only store user image data, but also The image you want to look for) performs local image retrieval on the user image data stored by itself. The memory includes a plurality of storage processing units, each storage processing unit includes a pattern processing circuit including an image recognition circuit and at least one three-dimensional memory (3D-M for short) array storing at least part of the image data. The vertical integration of the 3D-M array with the pattern processing circuit brings many advantages: since the 3D-M array does not occupy the substrate area, it can be integrated on the pattern processing circuit, which can increase the memory capacity and reduce the chip area. What's more, since the 3D-M array and the pattern processing circuit are in the same chip and in close proximity, a large bandwidth electrical connection can be achieved between them. By using massively parallel computing (each memory chip can contain tens of thousands of memory processing units), the memory can achieve fast image processing of large image libraries (such as image archives) based on input image models (such as images to be found) retrieve.

Correspondingly, the present invention provides a memory (200) with image recognition function, which is characterized by comprising: an input bus (110) for transmitting at least a part of the image model; a plurality of storages coupled with the input bus (110) Processing units (100aa-100mn), each storage processing unit (100ij) in the plurality of storage processing units (100aa-100mn) includes an image recognition circuit (180) and at least one three-dimensional storage (3D-M) array ( 170; or 170A-170D); wherein, the 3D-M array (170; or 170A-170D) stores at least part of the image data; the image recognition circuit (180) performs the part of the image data according to the image model. Pattern recognition; the 3D-M array (170; or 170A-170D) has multiple peripheral circuits (15, 15', 17, 17'; or 15A-15D, 17A-17D), the image recognition circuit (180 ) and all transistors (0t) in the peripheral circuits (15, 15', 17, 17'; or 15A-15D, 17A-17D) are located in the same semiconductor substrate (0), and are located in the semiconductor the upper surface of the substrate (0); all memory cells (5aa) in the 3D-M array (170; or 170A-170D) are located above the semiconductor substrate (0) and are not located on any semiconductor substrate the 3D-M array (170; or 170A-170D) and the peripheral circuits (15, 15', 17, 17'; or 15A-15D, 17A-17D) through a plurality of contact via holes ( 1av) coupling, the contact via hole (1av) does not penetrate any semiconductor substrate; the image recognition circuit (180) is connected by the peripheral circuit (15, 15', 17, 17'; or 15A-15D, 17A -17D) at least partially surrounded; the peripheral circuits (15, 15', 17, 17'; or 15A-15D, 17A-17D) are located outside the image recognition circuit (180).

The present invention also provides a memory (200) with image recognition function, which is characterized by comprising: an input bus (110) for transmitting at least part of the image model; a plurality of storage processing units coupled with the input bus (110) (100aa-100mn), each storage processing unit (100ij) in the plurality of storage processing units (100aa-100mn) includes an image recognition circuit (180) and a plurality of three-dimensional storage (3D-M) arrays (170A- 170D, 170W-170Z), wherein the 3D-M array (170A-170D, 170W-170Z) stores at least part of the image data; the image recognition circuit (180) performs the part of the image data according to the image model. pattern recognition; the 3D-M array (170A-170D, 170W-170Z) has multiple peripheral circuits (15A-15D, 17A-17D; 15W-15Z, 17W-17Z), the image recognition circuit (180) and All transistors (0t) in the peripheral circuits (15A-15D, 17A-17D; 15W-15Z, 17W-17Z) are located in the same semiconductor substrate (0) and are located in the semiconductor substrate (0) The upper surface of ; all memory cells (5aa) in the 3D-M array (170A-170D, 170W-170Z) are located above the semiconductor substrate (0), and are not located in any semiconductor substrate; The 3D-M array (170A-170D, 170W-170Z) is coupled with the peripheral circuits (15A-15D, 17A-17D, 15W-15Z, 17W-17Z) through a plurality of contact via holes (1av), the The contact via hole (1av) does not penetrate any semiconductor substrate; the image recognition circuit (180) contains a plurality of components (180A, 180B), and each of the components (180A) is connected by the peripheral circuits (15A-15D, 17A-17D, 15W-15Z, 17W-17Z) at least partially surrounded by selected peripheral circuits (15A-15D, 17A-17D) located in all of said components ( 180A, 180B).

Description of drawings

FIG. 1 is a circuit block diagram of a distributed mode processor.

2A-2C are circuit block diagrams of three storage processing units.

FIG. 3A is a cross-sectional view of a three-dimensional writable memory (3D-W for short) and a storage processing unit based on 3D-W; FIG. 3B is a three-dimensional printed memory (three-dimensional printed memory, 3D-P for short) and a cross-sectional view of a 3D-P-based storage processing unit.

FIG. 4 is a perspective view of a storage processing unit.

5A-5C are substrate circuit layout diagrams of three memory processing units.

Note that these figures are schematic diagrams only, they are not drawn to scale. Some dimensions and structures in the figures may be exaggerated or reduced for the sake of conspicuousness and convenience. In different embodiments, letter suffixes following numbers represent different instances of the same type of structure; the same number prefixes represent the same or similar structures. This specification uses the following wording conventions: "The circuit (or transistor) is located in the substrate" means that at least part of the circuit (or transistor) is located in the substrate, such as the channel, drain and source of the transistor included in the circuit are located in the substrate However, the gate of the transistor and its interconnection are still located outside the substrate; "circuit devices (such as memory cells) are not located in the substrate" means that no part of the circuit device is located in the substrate; "The upper surface of the substrate" refers to the surface where most of the transistors in the substrate are located; "The transistor is located on the upper surface of the substrate" means that the channel, drain and source of the transistor are located under the upper surface of the substrate, and the gate is located at Above the top surface of the substrate; "above the substrate" means on the same side as the top surface of the substrate; "a circuit device (such as a memory cell) is located above the substrate" means any part of the circuit device is located on the substrate , not in the substrate; "the pattern processing circuit overlaps the 3D-M array" means that the projection of the 3D-M array on the substrate overlaps the pattern processing circuit. In addition, "/" represents the relationship of "and" and "or".

Detailed ways

FIG. 1 shows a memory 200 with image recognition function, which is a distributed mode processor chip. The processor 200 contains m x n memory processing units 100aa-100mn. These memory processing units 100aa to 100mn are all formed on the substrate 0 . An input bus 110 is coupled to each storage processing unit, and an output bus 120 is coupled to each storage processing unit. Note that the distributed mode processor chip 200 may contain tens of thousands of memory processing units 100aa-100mn. Such a large number of storage processing units 100aa-100mn can guarantee massively parallel computing to realize high-speed mode processing.

Each storage processing unit 100ij includes a pattern processing circuit 170 and at least one 3D-M array 180 for storing at least one pattern. 2A-2C are circuit block diagrams of three storage processing units 100ij. In these embodiments, one mode processing circuit 180 serves a different number of 3D-M arrays 170 . The pattern processing circuit 180 in FIG. 2A serves a 3D-M array 170: pattern data stored in the 3D-M array 170 is fed into the pattern processing circuit 180 through the high bandwidth electrical connection 160 (see FIGS. The input pattern data 110 is subjected to pattern matching or pattern recognition, and output pattern data 120 is generated. The pattern processing circuit 180 in FIG. 2B serves four memory arrays 170A-170D: Pattern data stored in the 3D-M arrays 170A-170D is fed into the pattern through high bandwidth electrical connections 160A-160D (see FIGS. 3A-4 ) The circuit 180 is processed, and pattern matching or pattern recognition is performed with the input pattern data 110 . Pattern processing circuit 180 in FIG. 2C serves eight memory arrays 170A-170D and 170W-170Z: pattern data stored in 3D-M arrays 170A-170D and 170W-170Z electrically connect 160A-160D and 160W- 160Z (see FIGS. 3A-4 ) is fed into pattern processing circuit 180 and subjected to pattern matching or pattern recognition with input pattern data 110 . As can be seen from Figures 5A-5C in the future, the mode processing circuit 180 serving more 3D-M arrays has a larger area and higher functionality.

Figures 3A-3B show two typical 3D-Ms. FIG. 3A is a cross-sectional view of a 3D-W based storage processing unit 100ij. The information stored in 3D-W is entered using electrical programming. Common 3D-W has 3D-XPoint. Other 3D-Ws include memristor, resistive memory (RRAM), phase change memory (PCM), programmable metallization cell (PMC), conductive bridging random-access memory (CBRAM), and more. According to its programmable times, 3D-W is divided into three-dimensional one-time-programmable memory (three-dimensional one-time-programmable memory, referred to as 3D-OTP) and three-dimensional multiple-time-programmable memory (three-dimensional multiple-time-programmable memory, 3D-MTP for short). As the name suggests, 3D-OTP can be programmed once, and 3D-MTP can be programmed multiple times (including repeated programming). The 3D-OTP technology is mature, and it can store and retrieve pattern libraries (such as virus identification library, network specification library, acoustic model library, language model library, etc.), and the pattern data in these pattern libraries are only added but not modified. 3D-MTP is a general-purpose memory that can be used to store target schema libraries such as user data (including user code), etc.

The 3D-W based memory processing unit 100ij includes a substrate circuit layer OK formed on a semiconductor substrate 0 . The storage layer 16A is stacked over the substrate circuit OK, and the storage layer 16B is stacked over the storage layer 16A. The substrate circuit layer 0K includes peripheral circuits 15, 17 . . . of the memory layers 16A, 16B and a mode processing circuit 180 (FIG. 5A-FIG. 5C), which includes a transistor 0t and an interconnection line 0M. All transistors 0t in the substrate circuit layer 0K are located in the substrate 0 and are located on the upper surface of the substrate 0 . Each memory layer (eg, 16A) contains multiple first address lines (eg, 2a, along the y direction), multiple second address lines (eg, 1a, along the x direction), and multiple 3D-W memory cells (eg, 1aa) . All memory cells 1aa in memory layers 16A, 16B are located above substrate 0 and not in any substrate. The storage layers 16A, 16B are coupled to the substrate 0 through contact via holes 1av, 3av, respectively, and the contact via holes 1av, 3av do not penetrate any substrate.

The 3D-W memory cell 5aa includes a programming film 12 and a diode film 14 . The programming film 12 may be an anti-fuse film (for 3D-OTP) or other multi-time programming films (for 3D-MTP). The diode film 14 has the following generalized characteristics: under the read voltage, its resistance is small; when the applied voltage is smaller than the read voltage or in the opposite direction to the read voltage, its resistance is large. The diode film may be a PiN diode, a metal oxide (eg TiO ₂ ) diode, or the like.

FIG. 3B is a cross-sectional view of a 3D-P-based storage processing unit 100ij. The information stored in 3D-P is entered by printing during the production process in the factory (printing method). This information is permanently fixed and cannot be changed after leaving the factory. The imprinting method may be photo-lithography, nano-imprint, e-beam lithography, DUV scanning exposure, laser programming and the like. Common 3D-P has three-dimensional mask programming read-only memory (3D-MPROM), which records data through mask programming by photolithography. The reading speed of 3D-P is faster than that of 3D-W, and it is suitable for storing fixed pattern libraries (such as acoustic model library and language model library, etc.) and realizing high-performance pattern processing (such as realizing natural language processing and real-time language translation, etc.).

3D-P contains at least two kinds of memory cells 5aa, 6aa. Memory cell 6aa is a low-resistance memory cell, and memory cell 5aa is a high-resistance memory cell. The low-resistance memory element 6aa includes a diode film 14, and the high-resistance memory element 5aa includes a high-resistance film 12 more than the low-resistance memory element 6aa. As a simple example, the high resistance film 12 may be a silicon dioxide film. The high-resistance film 12 is physically removed at the memory cell 6aa by a printing method in the process flow.

In the 3D-M of Figures 3A-3B (including 3D-W and 3D-P), each storage layer contains multiple 3D-M arrays. A 3D-M array is a collection of all memory cells in a memory layer that share at least one address line. In a 3D-M array, all address lines are contiguous and do not share any address lines with different 3D-M arrays. On the other hand, one 3D-M chip contains multiple 3D-M modules. Each 3D-M module contains all storage layers in 3D-M, and its top storage layer contains only one 3D-M array, and the projection of the 3D-M array on the substrate determines the boundary of the 3D-M module.

FIG. 4 discloses the structure of the storage processing unit 100ij from another perspective. The memory mode 3D-M array 170 is stacked over the substrate 0 , and the processing mode mode processing circuit 180 is located in the substrate 0 and is at least partially covered by the 3D-M array 170 . Communication between the 3D-M array 170 and the pattern processing circuit 180 is achieved through a large bandwidth electrical connection 160 formed by a large number of contact via holes 1av, 3av. Due to the large number of contact via holes 1av and 3av (can be tens of thousands) and the short length (micron level), the bandwidth of the electrical connection 160 in the chip is much higher than the communication bandwidth between the chips.

The vertical integration of the 3D-M array 170 with the pattern processing circuit 180 brings many advantages: since the 3D-M array 170 does not occupy the substrate area, it can be integrated on the pattern processing circuit 180, which can increase the storage capacity and reduce the chip area . More importantly, since the 3D-M array 170 and the mode processing circuit 180 are located in the same chip 200 and are in close proximity, a larger bandwidth can be achieved between them. By employing massively parallel computing, the distributed pattern processor 200 enables fast pattern processing for large pattern libraries.

Figures 5A-5C disclose specific implementations of three storage processing units. In these embodiments, the mode processing circuit 180 is at least partially covered by a 3D-M array (170; 170A-170D; or 170W-170Z). In other words, the mode processing circuit 180 at least partially overlaps the 3D-M array (170; 170A-170D; or 170W-170Z). The embodiment of FIG. 5A corresponds to the storage processing unit 100ij in FIG. 2A. Mode processing circuit 180 serves a 3D-M array 170 . In this embodiment, the 3D-M array 170 contains four peripheral circuits, including X decoders 15, 15' and Y decoders (including readout circuits) 17, 17'. The 3D-M array 170 is coupled to its peripheral circuits 15, 15', 17, 17' through contact via holes 1av, 3av. The mode processing circuit 180 is coupled to the peripheral circuits 15, 15', 17, 17' (not shown in the figure). The mode processing circuit 180 is surrounded by peripheral circuits 15 , 15 ′, 17 , 17 ′, which are located outside the mode processing circuit 180 . In FIG. 5A, since the 3D-M array 170 is located above the substrate circuit 0K, not in the substrate circuit 0K, its projection on the substrate 0 is represented here by a dashed line.

In this embodiment, the mode processing circuit 180 is confined between four peripheral circuits, and its area cannot exceed the area of the 3D-M array 170 , so its area is small and its functions are limited. This embodiment is more suitable for implementing simpler pattern processing (such as string matching and code matching). Obviously, more complex pattern processing (eg, speech recognition, image recognition) requires larger circuitry, which requires a larger substrate area under the 3D-M array 170 for the layout of the pattern processing circuitry 180 . 5B-5C disclose two mode processing circuits 180 with larger area and higher functionality.

The embodiment of Figure 5B corresponds to the storage processing unit 100ij in Figure 2B. In this embodiment, one mode processing circuit 180 serves four 3D-M arrays 170A-170D. Each 3D-M array (eg 170A) has only two peripheral circuits (eg X decoder 15A and Y decoder 17A). Below the four 3D-M arrays 170A-170D, the substrate circuit OK can be freely laid out to form a pattern processing circuit 180 . Obviously, the mode processing circuit 180 of FIG. 5B can be four times larger than that of FIG. 5A, which enables more complex mode processing functions.

The embodiment of Figure 5C corresponds to the storage processing unit 100ij in Figure 2C. In this embodiment, one mode processing circuit 180 serves eight 3D-M arrays 170A-170D and 170W-170Z. The eight 3D-M arrays are divided into two groups 150A, 150B. Each group (eg 150A) includes four 3D-M arrays (eg 170A-170D). Below the four 3D-M arrays 170A- 170D of the first set 150A, the substrate circuits can be freely laid out, forming a first mode processing circuit assembly A 180A. Similarly, under the four 3D-M arrays 170W-170Z of the second group 150B, the substrate circuits can also be freely laid out to form the second mode processing circuit assembly B 180B. The first mode processing circuit component 180A and the second mode processing circuit component 180B constitute the mode processing circuit 180 . In this embodiment, between adjacent peripheral circuits (such as between adjacent X decoders 15A and 15C; between adjacent Y decoders 17A and 17B; between adjacent Y decoders 17C and 17D) A gap (eg G) is left between the two to form wiring channels 190Xa, 190Ya, 190Yb for communication between different mode processing circuit components 150A, 150B or between different mode processing circuits. Clearly, the mode processing circuit 180 of Figure 5C can be eight times larger than that of Figure 5A, which enables more complex mode processing functions.

In some embodiments of the present invention, the mode processing circuit 180 only needs to perform part of the mode processing functions. For example, the pattern processing circuit 180 only needs to perform simple pattern processing (eg, extraction and processing of simple features). The filtered mode after the simple mode processing will be further sent to a more powerful external processor (eg CPU, GPU) through the output bus 120 to complete the final mode processing. Since most of the patterns in the pattern library are filtered out by simple pattern processing, the output patterns only occupy a small part of the pattern library, which can reduce the bandwidth pressure on the output bus 120 .

In the distributed mode processor 200, the storage processing unit 100ij can adopt two mode processing modes - a processor-like mode and a memory-like mode. For the processor-like mode, the storage processing unit 100ij is like a processor to the outside world that can use its own retrieval pattern library to perform pattern processing on external user data. Specifically, the 3D-M array 170 of the storage processing unit 100ij stores a retrieval database; the input data 110 of the storage processing unit 100ij is user data (including user codes), which are generally generated in real time, such as network data packets ; The storage processing unit 100ij performs pattern matching or pattern recognition on the user data 110 and the retrieval pattern library. Due to the large bandwidth connection 160 between the 3D-M array 170 and the pattern processor 180, this pattern processing method is more efficient than the traditional pattern processing method of retrieving pattern libraries stored in separate memory.

For the memory-like mode, the storage processing unit 100ij looks to the outside world like a memory mainly used for storing user data, and can use its own mode processing circuit to perform mode processing. Specifically, the user data is permanently stored in the 3D-M array 170 of the storage processing unit 100ij; the input data 110 of the storage processing unit 100ij is retrieval pattern data; the storage processing unit 100ij performs pattern matching or pattern matching on the retrieval pattern data 110 with its user data pattern recognition. Note that a plurality of distributed mode processor chips 200 in a memory-like manner can be packaged into memory cards (such as SD cards, TF cards) and solid-state hard disks like flash memory chips, for storing massive user data (such as user data files) ). Since each storage processing unit 100ij in each distributed mode processor chip 200 has its own mode processing circuit 180, the mode processing circuit 180 only needs to process the data stored in the 3D-M array 170 in the storage processing unit 100ij. Therefore, regardless of the capacity of the memory card and solid state drive, the mode processing time is close to the time for the single mode processing circuit 180 to process the data stored in the 3D-M array 170 to which it is coupled. This huge advantage is unimaginable for traditional processors.

In the memory-like approach, the storage processing unit 100ij is the final storage device for user data. This is different from traditional processors with embedded memory: the embedded memory in traditional processors only temporarily stores user data, and the final storage device for user data is external memory (such as hard disk, optical disk, tape, etc.). If user data is permanently stored in a conventional processor, the conventional processor can only serve these data and cannot serve other data. That is, a lot of user data requires a lot of processors. Since traditional processors are very expensive, this approach is prohibitively expensive. In contrast, in the storage processing unit 100ij proposed by the present invention, the mode processing circuit 180 is integrated under the 3D-M array 170 and formed simultaneously with the peripheral circuits (eg, decoder) of the 3D-M array. Since 3D-M originally needs to form peripheral circuits, and the peripheral circuits only occupy a small area on the substrate 0 (see FIG. 5A-FIG. 5C ), most of the substrate area can be used to form the mode processing circuit 180, the mode processing circuit 180 is free for 3D-M. Thus, a large number of approximately free mode processing circuits 180 may be formed on the distributed mode processor chip 200, each mode processing circuit 180 serving specific data (stored in the 3D-M array 170 coupled thereto).

The following is a brief introduction to the application of distributed mode processors. As an example, the distributed mode processor 200 is an anti-malware processor, which is mainly used for network security and computer antivirus. The network security can adopt a processor-like approach: the input data 110 of the distributed pattern processor 200 is network data packets, the 3D-M array 170 stores the network specification library and the virus identification library, and the pattern processing circuit 180 performs pattern matching on them. Computer anti-virus can use a processor-like method and a memory-like method: for the processor-like method, the user data stored in the computer is transmitted as input data 110 to the distributed mode processor 200, and the 3D-M array 170 stores the virus identification library. Circuit 180 pattern-matches them; for the memory-like approach, virus identifiers are passed as input data 110 to distributed pattern processor 200, user data is stored in 3D-M array 170, and pattern processing circuit 180 pattern-matches them. In the processor-like way, 3D-M can be 3D-OTP or 3D-MTP, which is used to store the network specification library and virus identification library. In a memory-like approach, 3D-M is preferably 3D-MTP, which stores the user database.

As another example, the distributed schema processor 200 may be used for big data analysis (eg, financial data analysis, e-commerce data analysis, bioinformatics). Big data analysis involves unstructured or semi-structured data. Traditional analytical methods using relational databases are powerless to do this. The distributed mode processor 200 can improve big data analysis capabilities. In order to improve efficiency, it is better to use a memory-like approach: big data is stored in the 3D-M array 170 as a file, and keywords used for data analysis are sent to the distributed pattern processor 200 as input pattern data 110, and the pattern processing circuit 180 pairs They do pattern matching. In big data analytics, 3D-M is preferably 3D-MTP, which is used to store user data.

The distributed mode processor 200 may also be used for speech recognition and/or image recognition. In the identification process, a processor-like method and a memory-like method can be used. For the processor-like approach, the voice/image data generated by the user is sent to the distributed mode processor 200 as input data 110, and the 3D-M array 170 stores various recognition model libraries (eg, acoustic model library, language model library, image model library, etc.). etc.), after which the mode processor 180 identifies. For the memory-like method, the voice/image data generated by the user is stored in the 3D-M array 170 as a file, and the speech signal or image signal to be searched is sent to the distributed mode processor 200 as the input data 110, and then the mode processing circuit 180 performs the processing. Identify and find. In the processor-like way, 3D-M can be 3D-P, 3D-OTP or 3D-MTP, which stores acoustic model library, language model library, image model library and so on. In a memory-like approach, 3D-M is preferably 3D-MTP, which stores a voice/image archive.

It will be understood that changes may be made in form and detail without departing from the spirit and scope of the invention, which does not prevent them from applying the spirit of the invention. Accordingly, the invention should not be limited in any way except in accordance with the spirit of the appended claims.

Claims (10)

1. A memory (200) having an image recognition function, comprising:

an input bus (110) for transmitting at least part of the image model;

a plurality of memory processing units (100aa-100mn) coupled to the input bus (110), each memory processing unit (100ij) of the plurality of memory processing units (100aa-100mn) including an image recognition circuit (180) and at least one three-dimensional memory (3D-M) array (170; or 170A-170D); wherein the 3D-M array (170; or 170A-170D) stores at least a portion of the image data; the image recognition circuit (180) performs pattern recognition on the partial image data according to the image model;

the 3D-M array (170; or 170A-170D) has a plurality of peripheral circuits (15, 15 ', 17, 17'; or 15A-15D,17A-17D), all transistors (0t) in the image recognition circuit (180) and the peripheral circuits (15, 15 ', 17, 17'; or 15A-15D,17A-17D) are located in the same semiconductor substrate (0) and located on the upper surface of the semiconductor substrate (0);

all memory cells (5aa) in the 3D-M array (170; or 170A-170D) are located above the semiconductor substrate (0) and not in any semiconductor substrate;

the 3D-M array (170; or 170A-170D) and the peripheral circuits (15, 15 ', 17, 17'; or 15A-15D,17A-17D) are coupled through a plurality of contact via holes (1av), the contact via holes (1av) not penetrating any semiconductor substrate;

the image recognition circuit (180) is at least partially surrounded by the peripheral circuit (15, 15 ', 17, 17', or 15A-15D, 17A-17D); the peripheral circuits (15, 15 ', 17, 17'), or 15A-15D,17A-17D) are located outside the image recognition circuit (180).

2. The memory (200) with image recognition function according to claim 1, further characterized in that: each of the storage processing units (100ij) contains a 3D-M array (170).

3. The memory (200) with image recognition function according to claim 2, further characterized in that: the 3D-M array (170) has two peripheral circuits (15, 15 '; or 17, 17') in one direction (X or Y).

4. The memory (200) with image recognition function according to claim 1, further characterized in that: each of the storage processing units (100ij) contains four 3D-M arrays (170A-170D).

5. The memory (200) with image recognition function according to claim 4, further characterized in that: the 3D-M array (170A) has only one peripheral circuit (15A or 17A) in one direction (X or Y).

6. A memory (200) having an image recognition function, comprising:

an input bus (110) for transmitting at least part of the image model;

a plurality of memory processing units (100aa-100mn) coupled to the input bus (110), each memory processing unit (100ij) of the plurality of memory processing units (100aa-100mn) comprising an image recognition circuit (180) and a plurality of three-dimensional memory (3D-M) arrays (170A-170D,170W-170Z), wherein the 3D-M arrays (170A-170D,170W-170Z) store at least a portion of image data; the image recognition circuit (180) performs pattern recognition on the partial image data according to the image model;

the 3D-M array (170A-170D,170W-170Z) has a plurality of peripheral circuits (15A-15D, 17A-17D; 15W-15Z,17W-17Z), all transistors (0t) in the image recognition circuit (180) and the peripheral circuits (15A-15D, 17A-17D; 15W-15Z,17W-17Z) are located in the same semiconductor substrate (0) and are located on the upper surface of the semiconductor substrate (0);

all memory cells (5aa) in the 3D-M array (170A-170D,170W-170Z) are located above the semiconductor substrate (0) and not in any semiconductor substrate;

the 3D-M array (170A-170D,170W-170Z) and the peripheral circuits (15A-15D, 17A-17D,15W-15Z, 17W-17Z) are coupled through a plurality of contact via holes (1av), the contact via holes (1av) not penetrating any semiconductor substrate;

the image recognition circuit (180) has a plurality of components (180A, 180B), each of the components (180A) being at least partially surrounded by selected ones (15A-15D, 17A-17D,15W-15Z, 17W-17Z) of the peripheral circuits (15A-15D, 17A-17D), the peripheral circuits (15A-15D, 17A-17D) being located outside all of the components (180A, 180B).

7. The memory (200) with image recognition function according to claim 6, further characterized in that: a wiring channel (190Xa) is provided between adjacent ones of the peripheral circuits (15B, 15D).

8. The memory (200) with image recognition function according to claims 1-7, further characterized by: the 3D-M array (170 …) is a three-dimensional writable storage (3D-W) array.

9. The memory (200) with image recognition function according to claims 1-7, further characterized by: the image recognition circuit (180) at least partially overlaps the 3D-M array (170 …).

10. The memory (200) with image recognition function according to claims 1-7, further characterized by: the image recognition circuit (180) only performs a partial pattern recognition function; the memory (200) is coupled to an external processor via an output bus (120).

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