CN111466032A - Silicon carbide semiconductor device and power conversion device - Google Patents

Abstract

In a SiC-MOSFET having a schottky diode built therein, bipolar current flow to a well region at an end of an active region may not be sufficiently reduced, and reliability of the device may be reduced. In a SiC-MOSFET with a built-in Schottky diode, the density in the planar direction of the Schottky diodes formed in the termination region is made higher or the distance in the planar direction between the Schottky diodes is made shorter than the density of the Schottky diodes formed in the active region without ohmic connection between the well and the source of the termination region.

Description

Silicon carbide semiconductor device and power conversion device

technical field

The present invention relates to a silicon carbide semiconductor device and a power conversion device including silicon carbide.

Background technique

In a PN diode made of silicon carbide (SiC), when a forward current, ie, a bipolar current, continues to flow, a stacking fault occurs in the crystal and a forward voltage shift is known to have a reliability problem. The reason for this is considered to be that stacking faults, which are plane defects, originate from basal plane dislocations, etc. existing in the silicon carbide substrate due to the recombination energy of minority carriers injected through the PN diode and majority carriers. extension. This stacking fault inhibits the flow of current. Therefore, due to the expansion of the stacking fault, the current decreases and the forward voltage increases, resulting in a decrease in the reliability of the semiconductor device.

Such an increase in forward voltage similarly occurs in a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) using silicon carbide. The vertical MOSFET includes a parasitic PN diode (body diode) between the source and the drain, and when a forward current flows through the body diode, the same reliability degradation as the PN diode is caused in the vertical MOSFET. When the body diode of the SiC-MOSFET is used as the freewheeling diode of the MOSFET, this MOSFET characteristic degradation may occur.

As a method for solving the reliability problem caused by the forward current flowing to the parasitic PN diode as described above, as shown in Patent Document 1, there is a method in which the forward current flows through the parasitic PN diode for a long time. The current is applied to the pressure, and the change in the forward voltage before and after the pressure application is measured, and the components with a large change in the forward voltage are excluded (screened) from the product. However, in this method, there is a disadvantage that the energization time becomes longer, and a large number of defective products are generated when a wafer with many defects is used.

As another method, there is a method of incorporating a unipolar diode as a freewheeling diode in a semiconductor device such as a MOSFET which is a unipolar transistor. For example, Patent Document 2 and Patent Document 3 describe a method of incorporating a Schottky Barrier Diode (SBD: Schottky Barrier Diode) as a unipolar diode in a MOSFET element.

When a unipolar transistor in which a unipolar diode is built in the active region, that is, a diode that is energized only by majority carriers, is applied to a SiC semiconductor device, the voltage at which the energization operation starts by applying the diffusion potential of the unipolar diode It is designed to be lower than the diffusion potential of the PN junction so that a bipolar current does not flow through the body diode during the freewheeling operation, thereby suppressing the deterioration of the characteristics of the unipolar transistor in the active region.

However, even in a unipolar transistor with a built-in unipolar diode in the active region, a site where a parasitic PN diode is formed may occur at a site other than the terminal region, ie, the region other than the active region, where it is structurally difficult to arrange a unipolar diode.

For example, in a region near the gate pad and near the terminal portion of the semiconductor device, a terminal well region protruding to the outer peripheral side than the source electrode is formed, and a parasitic PN diode is formed between the terminal well region and the drift layer. Further, in this portion, the Schottky electrode is not formed, and the unipolar diode is not formed. Since there is no Schottky electrode in the terminal well region, a voltage between the source electrode and the drain electrode is applied to the PN diode formed by the terminal well region and the drift layer, and as a result, a bipolar current flows in the PN diode.

When the origin of basal plane dislocation or the like exists in such a location, the stacking fault may expand and the withstand voltage of the transistor may decrease. Specifically, when the transistor is in the OFF state, a leakage current occurs, and elements and circuits may be destroyed due to heat generation due to the leakage current.

In order to avoid this problem, the voltage applied between the source and the drain may be limited to a certain value or less so that a bipolar current does not flow through the PN diode formed of the terminal well region and the drift layer. For this reason, the source-drain voltage that occurs when a freewheeling current flows may be reduced by increasing the chip size. In this case, there is a disadvantage that the chip size increases and the cost increases.

In addition, as a method of suppressing the forward operation of the PN diode formed by the termination well region and the drift layer without increasing the chip size, there is a method of increasing the resistance of each part of the termination well region and the conduction path formed between the source electrode 80 . method. Among the methods of increasing the resistance of the current-carrying path, there is a method of increasing the contact resistance between the terminal well region and the source electrode (for example, Patent Document 4) and the like. With such a structure, when a bipolar current flows through the PN diode formed of the terminal well region and the drift layer, a voltage drop occurs due to the above-mentioned resistance component, so that the potential of the terminal well region and the source potential deviate accordingly. , the forward voltage applied to the PN diode decreases. Therefore, the conduction of bipolar current can be suppressed.

Furthermore, a method of fabricating a Schottky barrier diode (SBD) in a terminal well region is known (for example, Patent Document 5).

prior art literature

Patent Literature

Patent Document 1: Japanese Patent Laid-Open No. 2014-175412

Patent Document 2: Japanese Patent Laid-Open No. 2003-017701

Patent Document 3: WO2014-038110 International Publication

Patent Document 4: WO2014-162969 International Publication

Patent Document 5: WO2016-052261 International Publication

SUMMARY OF THE INVENTION

However, when an electrode ohmically connected to the source electrode is provided in the terminal well region, even if the contact resistance between the terminal well region and the source electrode is increased, the energization formed between the terminal well region and the source electrode may not be sufficiently improved. The resistance of the path cannot sufficiently reduce bipolar current energization to the termination well region.

Furthermore, even if the SBD is formed in the termination well region, bipolar current conduction to the termination well region and the well region at the end of the active region may not be sufficiently reduced.

The present invention has been made in order to solve the above-mentioned problems, and an object thereof is to provide a silicon carbide semiconductor device with further improved reliability.

The silicon carbide semiconductor device according to the present invention includes: a drift layer of a first conductivity type formed on a semiconductor substrate; a plurality of first well regions of a second conductivity type provided in a surface layer of the drift layer; a plurality of first well regions The first separation region of the conductivity type is formed adjacent to the first well region from the surface of the first well region to the drift layer; the first Schottky electrode is provided on the first separation region, and is formed on the first separation region. Terky junction; ohmic electrodes provided on the first well region; second well regions of the second conductivity type provided on the surface layer of the drift layer independently of the first well region; a plurality of fourth well regions of the first conductivity type The separation region is formed adjacent to the second well region from the surface of the second well region to the drift layer, and the interval is shorter than that of the plurality of first separation regions; the second Schottky electrode is provided on the fourth separation region , perform Schottky bonding with the first separation region; the source region of the first conductivity type is formed on the surface layer portion of the first well region; the gate insulating film is formed on the first well region and the second well region; a gate electrode formed on the gate insulating film on the first well region and the second well region; a gate pad connected to the gate electrode and formed above the second well region; and a source electrode connected to The first Schottky electrode, the second Schottky electrode, and the ohmic electrode are electrically connected, and are non-ohmically connected to the second well region.

According to the silicon carbide semiconductor device according to the present invention, bipolar current can be further suppressed from flowing in the well region at the end of the active region, and reliability can be improved.

Description of drawings

FIG. 1 is a schematic plan view of a silicon carbide semiconductor device according to Embodiment 1 of the present invention as viewed from a top surface.

2 is a schematic cross-sectional view of the silicon carbide semiconductor device according to Embodiment 1 of the present invention.

3 is a schematic plan view of the silicon carbide semiconductor device according to Embodiment 1 of the present invention.

4 is a schematic plan view of another structure of the silicon carbide semiconductor device according to Embodiment 1 of the present invention.

5 is a schematic plan view of the silicon carbide semiconductor device according to Embodiment 1 of the present invention.

6 is a schematic plan view of the silicon carbide semiconductor device according to Embodiment 1 of the present invention.

7 is a schematic plan view of another structure of the silicon carbide semiconductor device according to Embodiment 1 of the present invention.

8 is a schematic cross-sectional view of another structure of the silicon carbide semiconductor device according to Embodiment 1 of the present invention.

9 is a schematic cross-sectional view of another structure of the silicon carbide semiconductor device according to Embodiment 1 of the present invention.

10 is a schematic cross-sectional view of another structure of the silicon carbide semiconductor device according to Embodiment 1 of the present invention.

11 is a schematic cross-sectional view of another structure of the silicon carbide semiconductor device according to Embodiment 1 of the present invention.

12 is a schematic plan view of another structure of the silicon carbide semiconductor device according to Embodiment 1 of the present invention.

13 is a schematic plan view of another structure of the silicon carbide semiconductor device according to Embodiment 1 of the present invention.

14 is a schematic plan view of another structure of the silicon carbide semiconductor device according to Embodiment 1 of the present invention.

15 is a schematic plan view of another structure of the silicon carbide semiconductor device according to Embodiment 2 of the present invention.

16 is a schematic plan view of another structure of the silicon carbide semiconductor device according to Embodiment 3 of the present invention.

17 is a schematic cross-sectional view of a silicon carbide semiconductor device according to Embodiment 2 of the present invention.

18 is a schematic plan view of a silicon carbide semiconductor device according to Embodiment 2 of the present invention.

19 is a schematic cross-sectional view of a silicon carbide semiconductor device according to Embodiment 3 of the present invention.

20 is a schematic plan view of a silicon carbide semiconductor device according to Embodiment 3 of the present invention.

21 is a schematic plan view of a silicon carbide semiconductor device according to Embodiment 4 of the present invention.

22 is a schematic diagram showing a configuration of a power conversion device according to Embodiment 5 of the present invention.

(Description of reference numerals)

10: Semiconductor substrate; 20: Drift layer; 21: 1st departure region; 22: 2nd departure region; 23: 3rd departure region; 24: 4th departure region; 25: 5th departure region; 30: 1st well area; 31: 2nd well area; 32: contact area; 33: 2nd contact area; 34: auxiliary connection area; 37: JTE area; 38: auxiliary area; 39: ground auxiliary area; 40: source area; 45 : silicon carbide conductive layer; 50: gate insulating film; 51: field insulating film; 55: interlayer insulating film; 60: gate electrode; 70: ohmic electrode; 74: second ohmic electrode; 73: Second Schottky electrode; 80: Source electrode, source pad; 81: Gate pad; 82: Gate wiring; 84: Drain electrode; 90: First contact hole; 91: second contact hole; 92: second well region contact hole; 95: gate contact hole; 100: power supply; 200; power conversion device; 201: main conversion circuit; 202: drive circuit; 203: control circuit; 300 :load.

Detailed ways

Hereinafter, embodiments will be described with reference to the drawings. In addition, the drawings are schematically shown, and the mutual relationship between the sizes and positions of the images shown in different drawings is not necessarily described accurately, and can be appropriately changed. In addition, in the following description, the same code|symbol is attached|subjected to the same component, and it is shown in figure, and those names and functions are also the same. Therefore, detailed explanations about them are sometimes omitted.

In the embodiment described in this specification, as an example of a silicon carbide (SiC) semiconductor device, an n-channel silicon carbide MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type is taken as an example. Be explained. The description about the level of the potential is for the case where the first conductivity type is n-type and the second conductivity type is p-type. In the case of the n-type, the description of the level of the potential is also reversed.

Furthermore, in the present application, in the entire silicon carbide semiconductor device, a region in which the element cells are periodically arranged is referred to as an active region, and regions other than the active region are referred to as a termination region for description.

Embodiment 1.

First, the structure of the silicon carbide semiconductor device according to the first embodiment of the present invention will be described.

1 is a schematic plan view of a Schottky diode (SBD) built-in silicon carbide MOSFET (SBD built-in SiC-MOSFET) as a silicon carbide semiconductor device according to Embodiment 1, viewed from the top. In FIG. 1 , a gate pad 81 is formed on a part of the upper surface of the SiC-MOSFET, and a source electrode 80 is formed adjacent thereto. In addition, a gate wiring 82 is formed so as to extend from the gate pad 81 .

Fig. 2 is a schematic cross-sectional view schematically showing a cross-section from the source electrode 80 of Fig. 1 to the a-a' portion of the gate wiring 82 in the outer peripheral portion of the silicon carbide semiconductor device. In addition, FIG. 3 is a schematic plan view of a portion in which the silicon carbide semiconductor is mainly described in the top view of FIG. 1 .

In FIG. 2 , a drift layer 20 including n-type silicon carbide is formed on the surface of a semiconductor substrate 10 including n-type and low-resistance silicon carbide. In the surface layer portion of the drift layer 20 at a position substantially corresponding to the region where the gate wiring 82 described in FIG. 1 is provided, as shown in FIG. 3 , a second well region 31 containing p-type silicon carbide is provided.

A plurality of first well regions 30 including p-type silicon carbide are provided in the surface layer portion of the drift layer 20 below the region where the source electrode 80 described in FIG. 1 is provided. A source region 40 containing n-type silicon carbide is formed in each surface layer portion of the first well region 30 at a position entering a predetermined interval from the outer circumference of the first well region 30 toward the inside.

A contact region 32 made of low-resistance p-type silicon carbide is formed in the surface layer portion of the first well region 30 further inside the source region 40 in the surface layer portion of each first well region 30, and further inside the contact region 32 is formed. The first separation region 21 including silicon carbide which penetrates the first well region 30 . The first separation region 21 may be located in the vicinity of the first well region 30 , and may be adjacent to the first well region 30 without penetrating the first well region 30 . In addition, the first separation region 21 is of the same n-type as the drift layer 20 and has the same impurity concentration as the drift layer 20 .

On the surface side of the first separation region 21 , a first Schottky electrode 71 that is Schottky-connected to the first separation region 21 is formed. Here, the first Schottky electrode 71 is preferably formed so as to include at least the corresponding first separation region 21 when viewed from the top surface.

In addition, the ohmic electrode 70 is formed on the surface of the source region 40 , and the ohmic electrode 70 , the first Schottky electrode 71 , and the contact region 32 are formed on the ohmic electrode 70 , the first Schottky electrode 71 , and the contact region 32 . The source electrode 80 to which the contact region 32 is connected. The first well region 30 can easily exchange electrons and holes with the ohmic electrode 70 via the low-resistance contact region 32 .

The region of the drift layer 20 between the adjacent first well regions 30 is the second separation region 22 , which is the same n-type as the drift layer 20 and has the same impurity concentration as the drift layer 20 . A gate insulating film 50 is formed on the surfaces of the adjacent first well regions 30 , the second separation regions 22 therebetween, and the source regions 40 in the respective first well regions 30 , and on the gate insulating film 50 A gate electrode 60 is formed on at least the upper portion of the first well region 30 . The surface layer portion of the first well region 30 facing the lower portion of the portion where the gate electrode 60 is formed and with the gate insulating film 50 interposed therebetween is referred to as a channel region.

In the silicon carbide semiconductor device, the region where the first well region 30 is formed and the source electrode 80 of FIG. 1 is formed is an active region, and a first well region 30 is formed outside the active region, that is, outside the outermost first well region 30 . 2-well region 31 . A third separation region 23 is formed between the first well region 30 and the second well region 31 . The third separation region 23 is of the same n-type as the drift layer 20 and has the same impurity concentration as the drift layer 20 .

The outer side of the region in which the second well region 31 is formed becomes a termination region.

Inside the second well region 31 , a plurality of fourth separation regions 24 including silicon carbide are formed penetrating the second well region 31 . The fourth separation region 24 may be located in the vicinity of the second well region 31 , and may not pass through the second well region 31 but may be adjacent to the second well region 31 . Here, a second Schottky electrode 73 that is Schottky-connected to the fourth separation region 24 is formed on the surface side of each of the plurality of fourth separation regions 24 . Here, the second Schottky electrode 73 is preferably formed so as to include at least the corresponding fourth separation region 24 when viewed from the top surface.

A gate insulating film 50 and a field insulating film 51 are also formed on the second well region 31 , and a gate electrode 60 is formed on top of the gate insulating film 50 and the field insulating film 51 . In addition, an interlayer insulating film 55 is formed between the gate electrode 60 and the source electrode 80 . Furthermore, the gate electrode 60 and the gate wiring 82 above the second well region 31 are connected via a gate contact hole 95 formed in the interlayer insulating film 55 . In addition, a p-type silicon carbide JTE region 37 is formed on the outer peripheral side of the second well region 31 , that is, on the side opposite to the first well region 30 . The impurity concentration of the JTE region 37 is set to be lower than the impurity concentration of the second well region 31 .

An opening (second contact hole 91 ) is formed in a part of the gate insulating film 50 on the surface of the second well region 31 , and a source connected to the second Schottky electrode 73 , the ohmic electrode 70 and the like is formed in the opening. pole electrode 80 . Here, the second well region 31 and the source electrode 80 are not directly ohmically connected, but are insulated or Schottky connected.

In the active region, the ohmic electrode 70 , the first Schottky electrode 71 , and the source electrode 80 on the contact region 32 are insulated from the interlayer via the first contact hole 90 formed through the interlayer insulating film 55 and the gate insulating film 50 . The source electrode 80 on the film 55 is connected.

A drain electrode 84 is formed on the back surface side of the semiconductor substrate 10 .

Here, the second Schottky electrode 73 needs to be larger than the fourth separation region 24 and cover all the plane regions of the fourth separation region 24 . The reason for this is that, when a region not covered by the electrode having Schottky characteristics is formed in the fourth separation region 24 slightly, leakage current occurs in this portion in the OFF state, and a desired withstand voltage cannot be achieved. The size of the fourth separation region 24 and the size of the second Schottky electrode 73 cannot be made exactly the same due to deviations that may be caused by manufacturing such as mask alignment shift, so it is necessary to design the second Schottky electrode 73 to be larger than the second Schottky electrode 73 The fourth separation region 24 is reliably covered with the second Schottky electrode 73 by the fourth separation region 24 .

Therefore, the second Schottky electrode 73 needs to be in contact with the second well region 31 around the fourth separation region 24. However, when the contact characteristics between the second Schottky electrode 73 and the second well region 31 are assumed to have ohmic characteristics, Bipolar conduction suppression in the second well region 31 that is an effect of the present invention cannot be achieved. In order to avoid this problem, the second Schottky electrode 73 of the present invention not only has the Schottky characteristic with respect to the fourth separation region 24 but also has the Schottky characteristic with respect to the second well region 31 . Specifically, the surface concentration of the second well region 31 is sufficiently reduced to suppress tunnel leakage at the semiconductor/Schottky interface. In order to realize this, the surface concentration of the second well region 31 may be 1×10 ¹⁹ cm ⁻³ or less, more preferably 1×10 ¹⁸ cm ⁻³ or less.

In addition, the width of the fourth separation area 24 is preferably the same as the width of the first separation area 21 , or is preferably three times or less the width of the first separation area 21 even if it is larger than the width of the first separation area 21 . This is because when the width of the fourth separation region 24 is large, a large electric field is applied to the Schottky interface formed by the contact between the second Schottky electrode 73 and the fourth separation region 24 in the off state, and the leakage current increases. If it is large, the loss increases or the desired withstand voltage cannot be obtained.

Next, a method of manufacturing the SBD-embedded SiC-MOSFET as the silicon carbide semiconductor device of the present embodiment will be described.

First, on the semiconductor substrate 10 containing n-type and low-resistance silicon carbide having a polytype of 4H, the surface orientation of the first main surface is a (0001) plane having an off-angle, and a chemical vapor deposition method ( chemical VaporDeposition: CVD method), the drift layer 20 containing silicon carbide having an impurity concentration of 1×10 ¹⁵ to 1×10 ¹⁷ cm ⁻³ and an n-type thickness of 5 to 50 μm is epitaxially grown.

Next, an implantation mask is formed in a predetermined region on the surface of the drift layer 20 with a photoresist or the like, and Al (aluminum), which is a p-type impurity, is ion-implanted. At this time, the depth of the ion implantation of Al is set not to exceed about 0.5 to 3 μm of the thickness of the drift layer 20 . In addition, the impurity concentration of Al into which the ion implantation is performed is in the range of 1×10 ¹⁷ to 1×10 ¹⁹ cm ⁻³ , which is higher than the impurity concentration of the drift layer 20 . After that, the implantation mask is removed. By this step, the regions where the Al ion implantation is performed become the first well region 30 and the second well region 31 .

Next, an implantation mask is formed on the surface of the drift layer 20 with a photoresist or the like, and Al having a p-type impurity concentration is ion-implanted. At this time, the depth of the ion implantation of Al is set not to exceed about 0.5 to 3 μm of the thickness of the drift layer 20 . In addition, the impurity concentration of Al into which ion implantation is performed is in the range of 1×10 ¹⁶ to 1×10 ¹⁸ cm ⁻³ , which is higher than the impurity concentration of the drift layer 20 and lower than the impurity concentration of the first well region 30 . After that, the implantation mask is removed. Through this step, the region where Al is ion-implanted becomes the JTE region 37 . Similarly, the contact region 32 is formed by ion-implanting Al in a predetermined region at an impurity concentration higher than that of the first well region 30 .

Next, an implantation mask is formed with a photoresist or the like so that a predetermined portion inside the first well region 30 on the surface of the drift layer 20 is opened, and N (nitrogen), which is an n-type impurity, is ionized. injection. The ion implantation depth of N is made shallower than the thickness of the first well region 30 . In addition, it is assumed that the impurity concentration of N for ion implantation is in the range of 1×10 ¹⁸ to 1×10 ²¹ cm ⁻³ , which exceeds the p-type impurity concentration of the first well region 30 . Among the regions where N is implanted in this step, the region that exhibits the n-type is the source region 40 .

Next, annealing is performed at a temperature of 1300 to 1900° C. for 30 seconds to 1 hour in an inert gas atmosphere such as argon (Ar) gas by a heat treatment apparatus. By this annealing, the ion-implanted N and Al are electrically activated.

Next, using a CVD method, a photolithography technique, or the like, on the semiconductor layer in a region other than the active region substantially corresponding to the region in which the first well region 30 is formed, a field insulation comprising silicon oxide is formed with a film thickness of 0.5 to 2 μm. membrane 51.

Next, the silicon carbide surface not covered by the field insulating film 51 is thermally oxidized to form a silicon oxide film serving as the gate insulating film 50 with a desired thickness. Next, on the gate insulating film 50 and the field insulating film 51 , a polysilicon film having conductivity is formed by a reduced pressure CVD method, and is patterned to form the gate electrode 60 . Next, by the reduced pressure CVD method, the interlayer insulating film 55 containing silicon oxide is formed. Next, a first contact hole 90 that penetrates through the interlayer insulating film 55 and the gate insulating film 50 and reaches the contact region 32 in the active region and the source region 40 is formed, and at the same time, a second contact hole 91 that reaches the second well region 31 is formed .

Next, after forming a metal film mainly composed of Ni by a sputtering method or the like, heat treatment at a temperature of 600 to 1100° C. is performed to separate the metal film mainly composed of Ni and the silicon carbide layer in the first contact hole 90 . The reaction forms silicide between the silicon carbide layer and the metal film. Next, the remaining metal film other than the silicide formed by the reaction is removed by wet etching.

Thus, the ohmic electrode 70 is formed.

Next, a metal film mainly composed of Ni is formed on the back surface (second main surface) of the semiconductor substrate 10 and heat-treated to form a back surface ohmic electrode (not shown) on the back surface of the semiconductor substrate 10 .

Next, by patterning with a photoresist or the like, the interlayer insulating film 55 and the gate insulating film 50 on the first separation region 21 and the fourth separation region, and the interlayer at the position of the gate contact hole 95 are removed. insulating film 55 . As a method of removal, wet etching which does not damage the surface of the silicon carbide layer that becomes the Schottky interface is used.

Next, a metal film to be a Schottky electrode is deposited by sputtering or the like, and a first Schottky electrode is formed on the first separation region 21 in the first contact hole 90 by patterning with a photoresist or the like. 71 , a second Schottky electrode 73 is formed on the fourth separation region 24 in the second contact hole 91 .

Next, on the surface of the previously treated substrate, a wiring metal such as Al is formed by sputtering or vapor deposition, and processed into a predetermined shape by photolithography, thereby forming the ohmic electrode 70 on the source side, the first ohmic electrode 70 and the first The Schottky electrode 71 , the second Schottky electrode 73 , and the source electrode 80 in contact with the second well region 31 , and the gate pad 81 and the gate wiring 82 in contact with the gate electrode 60 .

Further, when the drain electrode 84 as a metal film is formed on the surface of the back surface ohmic electrode (not shown) formed on the back surface of the substrate, the silicon carbide semiconductor device of this embodiment shown in FIGS. 1 to 3 is completed.

Next, the operation of the SiC-MOSFET with built-in SBD as the silicon carbide semiconductor device of the present embodiment will be described. Here, a silicon carbide semiconductor device in which the semiconductor material is 4H-type silicon carbide will be described as an example. In this case, the diffusion potential of the pn junction is approximately 2V.

Hereinafter, the case of the freewheeling operation will be mainly described.

During the freewheeling operation, the drain voltage (the voltage of the drain electrode 84 ) becomes lower than the source voltage (the voltage of the source electrode 80 ), and a voltage of several V is generated. Since the SBD between the first separation region 21 and the first Schottky electrode 71 is formed in the active region and conducts at a lower voltage than the first well region 30, the freewheeling current flows in the SBD in principle, not in the first separation region 21 and the first Schottky electrode 71. 1 well region 30 flows through. When the source electrode 80 is ohmically connected to the second well region 31 via the ohmic electrode in the termination region, a source-drain junction is applied to the pn junction formed between the second well region 31 and the drift layer 20 . Since most of the voltage is present, a bipolar current flows through the pn diode formed by the second well region 31 and the drift layer 20 . However, in the silicon carbide semiconductor device of the present invention, the second well region 31 is not ohmically connected to the source electrode 80 but is insulated or Schottky connected. In addition, SBDs are formed between the plurality of fourth separation regions 24 formed through the second well regions 31 and the second Schottky electrodes 73 on top thereof.

However, the SBD current of the fourth separation region 24 formed by penetrating the second well region 31 is particularly difficult to flow in the present invention in which the second well region 31 is not ohmically connected to the source electrode 80 . In order to explain this phenomenon, the potential change of the second well region 31 during the freewheeling operation will be described.

During the freewheeling operation, a negative voltage such as -10 V is generated at the drain electrode 84 when the source voltage is set to 0 V, and current flows from the source electrode 80 to the drain electrode 84 . On the path from the source electrode 80 to the drain electrode 84 , a potential distribution corresponding to the resistance ratio occurs. Therefore, in the portion of the drift layer 20 that is in contact with the second well region 31 , the source electrode 80 and the drain occur. The potential between the pole electrodes 84 (eg -3V). Assuming that the second well region 31 is ohmically connected to the source electrode 80, the potential of the second well region 31 is maintained at approximately 0V, so a forward voltage (3V in this example) is applied to the pn junction, and the pn junction is A bipolar current flows through the junction.

On the other hand, in the present invention, since the second well region 31 is not ohmically connected to the source electrode 80, the second well region 31 is charged, and the second well region 31 is charged to be the same as the second well region 31 in the drift layer 20. The potential of the connected portion and the potential between the source electrode 80 (for example, -2V).

At this time, when focusing on the pn junction formed by the fourth separation region 24 and the second well region 31 , the second well region 31 is not ohmic compared to the case where the second well region 31 is ohmically connected to the source electrode 80 . In the case of connection, the reverse bias voltage applied to the pn junction increases the charge potential amount of the second well region 31 . The reverse bias applied to the pn junction formed by the fourth separation region 24 and the second well region 31 forms a depletion layer in each of the fourth separation region 24 and the second well region 31, but the impurity concentration is relatively low. The depletion layer extends particularly widely in the fourth exit region 24. The SBD current needs to pass through the fourth separation region 24 in which the conduction path is effectively narrowed by the depletion layer, so that a large resistance occurs in the fourth separation region 24 .

Therefore, even if the first separation region 21 and the fourth separation region 24 are designed to have the same width and the same impurity concentration, in the fourth separation region 24 sandwiched by the charged second well region 31, the resistance is so large that only A small current flows.

When the density of the SBDs formed in the termination region is equal to or smaller than the density of the SBDs formed in the active region, the SBD current flowing through the SBDs at the ends of the active region and the SBDs in the termination region is smaller than that in the center of the active region. The SBD current flowing through the SBD diffuses and flows toward the outer periphery of the chip where the SBD is not formed. Therefore, at the edge of the active region, the SBD current density flowing through the drift layer 20 and the semiconductor substrate 10 is smaller than that of other active regions inside the active region. . Therefore, the voltage drop generated in the drift layer 20 and the semiconductor substrate 10 is also smaller at the end of the active region than in other active regions.

Here, the voltage applied between the source and drain is the same in the chip, and a voltage obtained by subtracting the voltage drop between the drift layer 20 and the semiconductor substrate 10 from the voltage between the source and the drain is applied to the pn junction, Therefore, at the end of the active region, the voltage applied to the pn junction is larger than in other active regions. At the end of the active region, unlike the second well region 31 in the termination region, the first well region 30 is ohmically connected to the source electrode 80, so bipolar current flows when a voltage exceeding the diffusion potential is applied to the pn junction. The reason why this bipolar current flows is that the SBD current density of the drift layer 20 and the semiconductor substrate 10 at the end of the active region is low.

In the SiC-MOSFET with built-in SBD, which is the silicon carbide semiconductor device of the present embodiment, the interval between SBDs formed in the second well region 31 of the termination region is smaller than the interval between SBDs in the active region. That is, the density of SBDs formed in the second well region 31 serving as the termination region is higher than the density of SBDs in the active region. Therefore, even if the SBD current diffuses and flows toward the outer periphery of the chip where no SBD is formed, the SBD current density at the edge of the active region is not lower than the SBD density of other active regions, and the first well region 30 can be suppressed at the edge of the active region. A bipolar current, which is a forward current, flows through the pn junction between the drift layer 20 and the pn junction, and it is possible to suppress the stacking fault propagation of the pn junction and the reduction in the breakdown voltage due to the stacking fault propagation.

In addition, as a method of increasing the SBD current flowing in the fourth separation region 24, a method of increasing the width of the fourth separation region 24 and a method of increasing the n-type impurity concentration of the fourth separation region 24 are considered, but these increase the resistance to It is not necessarily preferable from the viewpoint of reliability because it is a reverse bias voltage applied to the SBD during voltage hold.

As described above, according to the silicon carbide semiconductor device of the present embodiment, bipolar operation during freewheeling operation at the edge of the active region can be suppressed, and reliability can be improved.

In addition, the effect of suppressing bipolar operation during the freewheeling operation of the silicon carbide semiconductor device of this embodiment is more pronounced when the distance between the SBD at the end of the active region and the SBD in the termination region is large.

The reason for this is that, as described above, the SBD current flowing from the SBD at the end of the active region spreads in the outer peripheral direction. When the distance between the SBD at the edge of the active region and the SBD in the termination region is large, the SBD current at the edge of the active region tends to spread in the outer peripheral direction. In this case, as in the silicon carbide semiconductor device of this embodiment, when the interval between the SBDs of the termination region is smaller than the interval of the SBDs of the active region, the SBD current at the edge of the active region can be suppressed from spreading in the outer peripheral direction, and the SBD current at the edge of the active region can be suppressed from spreading in the outer peripheral direction. A bipolar current that is a forward current flows through the pn junction between the first well region 30 and the drift layer 20 in the pn junction, and it is possible to suppress the stacking fault propagation of the pn junction and the dielectric breakdown voltage caused by the stacking fault propagation. reduce.

FIG. 4 shows a schematic cross-sectional view of the silicon carbide semiconductor device of the present embodiment in which the field insulating film 51 is formed on most of the second well region 31 . In the silicon carbide semiconductor device having the structure shown in FIG. 4 , the gate insulating film 50 is formed on the active region side on the second well region 31 , and is formed on the far side when viewed from the active region on the second well region 31 . There is a field insulating film 51 having a thickness larger than that of the gate insulating film 50 .

At this time, the end of the field insulating film 51 , that is, the boundary between the field insulating film 51 and the gate insulating film 50 is formed between the SBD at the end of the active region and the innermost SBD in the termination region, and the field insulating film 51 is penetrated to The second contact hole 91 for forming the SBD formed inside the second well region 31 is formed. In the etching step for penetrating the field insulating film 51 thicker than the gate insulating film 50 to form the second contact hole 91, the amount of etching in the chip plane direction, that is, the amount of side etching increases. Therefore, the end of the field insulating film 51 and the finished position of the side wall of the second contact hole 91 tend to vary. Considering the variation, it is necessary to estimate a large dimensional margin in the chip plane direction. As a result, the SBD at the end of the active region and the The distance between the innermost SBDs in the terminal region may be greater than the distance between the SBDs in the active region.

In such a case, as also shown in the schematic cross-sectional view of FIG. 4 , by making the interval between SBDs in the termination region smaller than the interval between SBDs in the active region, the SBD current at the end of the active region can be suppressed from spreading in the outer peripheral direction , it is possible to suppress the bipolar current that is a forward current from flowing through the pn junction between the first well region 30 and the drift layer 20 at the end of the active region. As a result, it is possible to suppress the stacking fault propagation of the pn junction and the reduction in the dielectric strength voltage due to the stacking fault propagation.

Among them, the effect of the silicon carbide semiconductor device of the present embodiment is particularly large between the active region and the region where the gate contact hole 95 is formed. In such a place, it is necessary to connect the potential of the gate electrode 60 from the active region to the gate contact hole 95, so the gate electrode 60 is not completely separated between the terminal region and the active region as shown in the cross-sectional view of FIG. On the other hand, a bridge portion connecting the gate electrode 60 is formed somewhere in the depth direction of the cross-sectional view. Since the second contact hole 91 cannot be formed in the region where the bridge portion of the gate electrode 60 is formed, the SBD of the termination region is not formed.

FIG. 5 is a schematic plan view of a part of the silicon carbide semiconductor device of the present embodiment mainly describing the structure of the semiconductor layer from the end of the active region to the termination region. In addition, FIG. 6 shows a schematic plan view of a part of the silicon carbide semiconductor device of the present embodiment mainly describing the same structure of the gate electrode 60 from the end of the active region to the termination region.

As described in FIG. 5 and FIG. 6 , the SBD of the termination region is formed intermittently with respect to the direction along the periphery of the end portion of the active region. In addition, as shown in FIG. 6 , the SBD of the termination region is formed in the middle of the path from the gate contact hole 95 to the active region, and the region of the second well region 31 above the region where the gate contact hole 95 is formed is formed. On the active region side, the gate electrode 60 (the bridge portion of the gate electrode 60 ) and the SBD of the termination region are alternately formed along the periphery of the end portion of the active region.

Here, if it is considered that the gate current flowing in the gate electrode 60 diffuses and flows to the wide active region after passing through the bridge portion of the gate electrode 60 from the gate contact hole 95, the input to the active region formed everywhere is affected. When the capacitor is charged and discharged, it can be seen that when the width of the bridge portion of the gate electrode 60 is approximately the same as the width of the gate electrode 60 formed in the active region, the gate electrode in the bridge portion relative to the active region The density of gate current flowing in 60 is higher. In such a case, the switching speed is limited by the high resistance of the bridge, and there is a possibility that other problems such that high-speed switching cannot be realized or, in a more significant case, the element is destroyed due to heat generation of the bridge may arise. In order to avoid such a problem, it is preferable to make the width of the bridge portion of the gate electrode 60 wider than the width of the gate electrode 60 formed in the active region.

However, when the width of the bridge portion of the gate electrode 60 is wide, the distance between the SBDs of the terminal regions separated by the bridge portion in the direction along the end portion of the active region also increases, so that the active region adjacent to the bridge portion can be easily damaged. Bipolar energization occurs at the end of the zone. As described in the present embodiment, by providing a plurality of SBDs in the termination structure along the chip peripheral direction, and forming a high density of SBDs in the second well region 31 , the SBD current in the termination region can be increased, so that the gate electrode 60 can be suppressed from being damaged. Bipolar conduction at the end of the active region near the bridge portion, and the distance between the terminal regions SBD separated in the direction along the end of the active region is designed to be large, as a result, the gate electrode of the bridge portion can be enlarged. 60 width, enabling high-speed switching.

As described above, the distance between the SBD at the end of the active region and the innermost SBD in the termination region is larger than the distance between the SBDs in the active region. Therefore, the termination region can be increased by providing a plurality of them in the direction toward the outer periphery of the chip. The SBD density inside can increase the SBD current density on the active region side including the terminal region of the bridge portion of the gate electrode 60, and can suppress the SBD current at the edge of the active region from spreading to the chip outer peripheral side. As a result, bipolar current as a forward current can be suppressed from flowing in the pn junction between the first well region 30 and the drift layer 20 at the end of the active region, and stacking fault propagation of the pn junction and the stacking fault caused by the pn junction can be suppressed. The dielectric withstand voltage decreases due to stacking fault expansion.

As described in FIGS. 5 and 6 , the interval between the second Schottky electrodes 73 in the termination region is shorter than the interval between the first Schottky electrodes 71 in the active region. In addition, the density of the second Schottky electrodes 73 in the termination region is higher than the density of the first Schottky electrodes 71 in the active region.

Similarly, the interval between the fourth separation regions 24 in the terminal region is shorter than the interval between the first separation regions 21 in the active region. In addition, the density of the second Schottky electrodes 73 in the termination region is higher than the density of the first Schottky electrodes 71 in the active region.

Furthermore, the interval between the SBDs of the terminal region is shorter than the interval between the SBDs of the active region. The SBD density of the terminal region is higher than that of the active region.

Here, the density of the second Schottky electrodes 73 in the termination region, the density of the fourth separation region 24 , and the SBD density are the densities in the second well region 31 in the termination region, and further, among the second well regions 31 , in The density on the active region side may be sufficient for the region where the gate contact hole 95 is formed above.

In addition, in this embodiment, the first well region 30 and the second well region 31 are described as being separated from each other, but the first well region 30 and the second well region 31 may be connected. In addition, although it was demonstrated that there are a plurality of first well regions 30 and the plurality of first well regions 30 are separated from each other, the plurality of first well regions 30 may be connected to each other. FIG. 7 is a schematic plan view showing a state in which the first well region 30 and the second well region 31 are connected, and the plurality of first well regions 30 are connected to each other.

In such a case, the first well region 30 is a first Schottky provided from the source region 40 in the first well region 30 or the first separation region 21 in the first well region 30 The distance between any one or both of the electrodes 71 is within 50 μm.

In addition, FIG. 8 is a schematic plan view of a portion mainly describing the silicon carbide semiconductor of another form of the silicon carbide semiconductor device of the present embodiment. In FIG. 8 , a second well region contact hole 92 for ohmically connecting the second well region 31 and the source electrode 80 is formed in a part of the second well region 31 . FIG. 9 is a schematic cross-sectional view showing a cross-section including a portion where the second well region contact hole 92 of FIG. 8 is formed. In FIG. 9 , the second well region contact hole 92 is formed through the field insulating film 51 and the interlayer insulating film 55 . Alternatively, a second well contact region 36 having a higher p-type impurity concentration and lower resistance than the second well region 31 may be provided in the second well region 31 below the second well region contact hole 92 .

The second well region contact hole 92 is formed on the shortest path in the second well region 31 so as to be separated from the second contact hole 91 by 10 μm or more in the transverse cross section. Here, in the second well region 31 , the portion separated from the second well region contact hole 92 by 10 μm or more is substantially regarded as a non-ohmic connection. The distance between the second contact hole 91 and the second well region contact hole 92 on the shortest path in the second well region 31 is more preferably 50 μm or more.

10 and 11 are schematic cross-sectional views of a part of a silicon carbide semiconductor device according to still another embodiment of the silicon carbide semiconductor device of the present embodiment. In FIGS. 10 and 11 , a silicon carbide conductive layer 45 of the first conductivity type is formed on a part of the surface layer of the second well region 31 , and an ohmic connection between the silicon carbide conductive layer 45 and the source electrode 80 is formed. The ohmic electrodes 72 are the same as those in FIG. 2 and FIG. 4 except for this. 12 is a schematic plan view illustrating a region of the silicon carbide conductive layer 45 formed on the silicon carbide semiconductor device shown in the schematic cross-sectional views of FIGS. 10 and 11 .

In the silicon carbide semiconductor device of the present embodiment, the silicon carbide conductive layer 45 of the first conductivity type is formed in a part of the surface layer of the second well region 31 , so in addition to the above-mentioned effects, the resistance in the plane lateral direction of the second well region 31 can be reduced , the voltage generated due to the displacement current flowing in the second well region 31 when the silicon carbide semiconductor device is turned on/off can be reduced. Therefore, reliability can be further improved.

In addition, heretofore, as the planar shape of the fourth separation region 24 and the second Schottky electrode 73, an example in which square-shaped regions are arranged from the active region toward the outer periphery of the chip has been shown, but these planar shapes and arrangement methods are arbitrary. For example, As shown in FIGS. 13 and 14, respectively, the structures of the semiconductor layer and the gate electrode 60 may be formed so that the planar shapes of the fourth separation region 24 and the second Schottky electrode 73 are formed along the chip peripheral direction. of multiple stripes. In addition, as shown in FIGS. 15 and 16, respectively, the structures of the semiconductor layer and the gate electrode 60, the planar shapes of the fourth separation region 24 and the second Schottky electrode 73 may be set along the A plurality of stripe shapes are formed in directions perpendicular to the direction of the outer periphery of the chip.

In addition, in the present embodiment, the example in which each ion implantation is performed in a predetermined order is shown, but the order of the ion implantation may be appropriately changed. In addition, the formation order of the ohmic electrode on the back surface, the ohmic electrode 70 on the front surface, the first Schottky electrode 71 , and the second Schottky electrode 73 may be appropriately changed.

In the present embodiment, it is shown that the first Schottky electrode 71 is formed only on the first separation region 21 and the first well region 30 , and the second Schottky electrode 73 is formed only on the fourth separation region 24 and the first well region 30 . In the example above the two-well region 31 , it may be formed on the ohmic electrode 70 and the interlayer insulating film 55 .

In addition, in this embodiment mode, the channel region and the Schottky electrode surface are formed to be parallel to the wafer plane and are described assuming a planar type, but the channel region and the Schottky electrode surface are formed to be inclined or perpendicular to the wafer plane. Also effective in grooved type. In this case, the surface defined in this specification includes not only the wafer plane but also the groove forming surface.

Furthermore, in the present embodiment, the first separation region 21 is assumed to be the same n-type as the drift layer 20 and have the same impurity concentration as the drift layer 20 , but the n-type impurity concentration of the first separation region 21 may be higher than that of the drift layer 20 . n-type impurity concentration of the drift layer 20 . The second separation area 22 and the fourth separation area 24 are also the same as the first separation area 21 .

In addition, the description is that the first conductivity type and the second conductivity type are n-type and p-type, respectively, but the description may be reversed. However, when the first conductivity type is n-type and the second conductivity type is p-type , which is further effective.

Embodiment 2.

The SBD formed in the second well region 31 of the termination region of the silicon carbide semiconductor device according to the first embodiment includes one second Schottky electrode 73 and one fourth separation region 24 in one second contact hole 91, In the SBD formed in the well region of the termination region of the silicon carbide semiconductor device of the present embodiment, the interval between the plurality of fourth separation regions 24 is smaller than the interval between the first separation regions 21 of the active region, and is formed over a plurality of The second contact hole 91 and the second Schottky electrode 73 in the fourth separation region 24 . The other points are the same as in Embodiment 1, so detailed description is omitted.

FIG. 17 schematically shows the cross section of the present embodiment from the source electrode 80 of FIG. 1 to the a-a' portion of the gate wiring 82 in the outer peripheral portion of the silicon carbide semiconductor device used in the description of the first embodiment. A schematic cross-sectional view of a silicon carbide semiconductor device. In addition, FIG. 18 is a schematic plan view of the semiconductor layer mainly describing the same region.

In the termination region of the silicon carbide semiconductor device of the present embodiment shown in FIG. 17 and FIG. 18 , in the plane of the second well region 31 of the second conductivity type, a first conductivity type polycrystalline silicon carbide is formed. The fourth separation region 24 is the second, and the region between the fourth separation regions 24 is an auxiliary region 38 of the second conductivity type that is the same as that of the second well region 31 . A second Schottky electrode 73 , which is Schottky-connected to the fourth separation region 24 , is formed on the upper portion of the plurality of fourth separation regions 24 , including the upper portion of the auxiliary region 38 therebetween. In addition, the gate insulating film 50 or the field insulating film 51 and the interlayer insulating film are penetrated so as to include a plurality of fourth separation regions 24 and the second Schottky electrode 73 formed under one second Schottky electrode 73 . film 55, and the second contact hole 91 is formed. Inside the second contact hole 91 , a source electrode 80 is formed so as to be in contact with the second well region 31 and the second Schottky electrode 73 .

The manufacturing method of the silicon carbide semiconductor device of the present embodiment is the same as that of the first embodiment, except that only the mask pattern is changed to form the second Schottky electrode 73 , the fourth separation region 24 , and the second contact hole 91 .

According to the silicon carbide semiconductor device of the present embodiment, the same effect as the silicon carbide semiconductor device of the first embodiment can be achieved, and the number of divisions of the second contact hole 91 and the second Schottky electrode can be reduced, and the fourth separation can be reduced. Distance between zones 24.

Therefore, the SBD density in the second well region 31 can be further increased, and a higher density SBD current can flow. As a result, bipolar conduction at the edge of the active region can be suppressed more strongly.

At this time, the second Schottky electrode 73 is in contact with the auxiliary region 38 that divides the fourth separation regions 24 from each other. When the auxiliary region 38 of the second conductivity type is connected to the second well region 31 in plan view, and when the second Schottky electrode 73 electrically connected to the source electrode 80 is ohmically connected to the auxiliary region 38, the second well region Since 31 is also connected to the source electrode by 80 ohms, the bipolar conduction suppression of the second well region 31 which is the effect of the present invention cannot be achieved. Therefore, the second Schottky electrode 73 of the present invention has Schottky characteristics not only with respect to the fourth separation region 24 but also with respect to the second well region 31 and the auxiliary region 38 . In order to realize this, the surface concentration of the second well region 31 in contact with the auxiliary region 38 and the second Schottky electrode 73 is preferably 1×10 ¹⁹ cm ⁻³ or less, and more preferably 1×10 ¹⁸ cm ⁻³ or less. .

On the other hand, when the impurity surface density (the sum of the volume densities in the depth direction) of the second well region 31 in contact with the auxiliary region 38 and the second Schottky electrode 73 is small, the depletion electric field in the auxiliary region in the off state is small. Insufficient termination, a large electric field is applied to the interface of the SBD in the termination region. As a result, there is a possibility that the Schottky leakage current increases, the heat generation of the chip increases, or the reliability of the element deteriorates. Therefore, it is preferable that the second well region 31 in contact with the auxiliary region 38 and the second Schottky electrode 73 has a reverse distribution having a concentration peak of the second conductivity type impurity in a region deeper than the surface.

Embodiment 3.

In Embodiment 2, an example in which the auxiliary region 38 is connected to the second well region 31 has been described, but in this embodiment, a ground auxiliary region 39 is formed instead of the auxiliary region 38, and the ground auxiliary region 39 and the second well region 31 are not connected. , the second well region 31 is not connected to the source electrode 80 ohms, and the ground auxiliary region 39 is connected to the source electrode 80 ohms. In addition, an n-type fourth separation region 24 is formed inside or between the auxiliary grounding regions 39 . The other points are the same as those in Embodiments 1 and 2, so detailed description is omitted.

FIG. 19 schematically shows the cross section of the present embodiment from the source electrode 80 of FIG. 1 to the a-a' portion of the gate wiring 82 in the outer peripheral portion of the silicon carbide semiconductor device used in the description of the first embodiment. A schematic cross-sectional view of a silicon carbide semiconductor device. In addition, FIG. 20 is a schematic plan view of the semiconductor layer mainly describing the same region.

As shown in FIGS. 19 and 20 , in the silicon carbide semiconductor device of the present embodiment, the ground assist region 39 and the second well region 31 are separated from each other in plan view and cross-sectional view. An n-type fifth separation region 25 is formed between the ground assist region 39 and the second well region 31 , and a second Schottky straddle between the ground assist region 39 and the second well region 31 is formed on the fifth separation region 25 . Base electrode 73 . In addition, a second contact region 33 made of low-resistance p-type silicon carbide is formed on the silicon carbide surface side of the ground auxiliary region 39 , and a second ohmic electrode 74 is formed on the surfaces of the second contact region 33 and the auxiliary region 38 . , the ground auxiliary region 39 is 80 ohm connected to the source electrode.

The fourth separation region 24 is formed inside or between the ground auxiliary regions 39 , and the second Schottky electrode 73 is Schottky-connected to the fourth separation region 24 and the fifth separation region 25 .

It is assumed that the fifth separation region 25 is the same n-type as the drift layer 20 and has the same impurity concentration as the drift layer 20 . The n-type impurity concentration of the fifth separation region 25 may be higher than the n-type impurity concentration of the drift layer 20 .

In the silicon carbide semiconductor device of the present embodiment, the auxiliary region 38 is ohmically connected to the source electrode 80, but in the vicinity of the auxiliary region 38, a fifth separation is formed at a small interval smaller than the separation of the first separation region 21 in the active region. Area 25, 4th away from area 24. Therefore, it is possible to prevent bipolar current from flowing in the pn junction formed between the auxiliary region 38 and the drift layer 20 by flowing a sufficient SBD current to the drift layer 20 below the auxiliary region 38 .

Here, as described above, the ground auxiliary region 39 and the second well region 31 are separated from each other in plan view and cross-sectional view. In addition, the second Schottky electrode 73 spanning the ground auxiliary region 39 and the second well region 31 has a Schottky contact for each of them. Therefore, the ground auxiliary region 39 and the second well region 31 are electrically separated from each other. Therefore, as in Embodiments 1 and 2, the second well region 31 is not ohmically connected to the source electrode 80, and bipolar current can be prevented from flowing from the second well region 31 during the freewheeling operation.

On the other hand, in the present embodiment, since the ground assist region 39 is ohmically connected to the source electrode 80, the ground assist region 39 is not charged during the freewheeling operation, and the depletion layer does not spread from the ground assist region 39 side to the The fourth separation region 24 and the fifth separation region 25 are adjacent to the grounding auxiliary region 39 . Therefore, a larger SBD current can flow through the second Schottky electrode 73 through the fourth separation region 24 and the fifth separation region 25 than when the ground auxiliary region 39 is floating. As a result, bipolar conduction at the edge of the active region can be suppressed more strongly.

In addition, in the present embodiment, the ground auxiliary region 39 , the fourth separation region 24 , the fifth separation region 25 , the second Schottky electrode 73 , the second ohmic electrode 74 , and the second contact region 33 are formed as a single contact In the second well region contact hole 92 of the hole, the area occupied in the planar direction can be reduced compared with the case where these structures are formed by dividing into a plurality of contact holes, and the enlargement of the element size can be suppressed.

In addition, since the auxiliary ground region 39 is ohmically connected to the source electrode 80, this embodiment shows an example in which both the second contact region 33 and the second ohmic electrode 74 are formed. However, even if only the second contact region 33, Any one of the second ohmic electrodes 74 may be ohmically connected to the ground auxiliary region 39 and the source electrode 80 .

In addition, the second contact region 33 and the contact region 32 of the active region may be formed simultaneously in the same ion implantation step, and may have the same impurity concentration. Similarly, the second ohmic electrode 74 may be formed by silicide or the like in the same process as the ohmic electrode 70 in the active region.

In this way, by forming the second contact region 33 and the contact region 32 or the second ohmic electrode 74 and the ohmic electrode 70, respectively, in the same process, the manufacturing cost can be reduced.

Embodiment 4.

In the termination regions of the silicon carbide semiconductor devices according to Embodiments 1 to 3, it is mainly explained that the first well region 30 in the active region is separated from the second well region 31 of the termination structure in principle, and the second well region 31 is not connected to the source electrode 80 . Ohmic connection, but in this embodiment, the second well region 31 of the termination structure is connected to a part of the first well region 30 via the auxiliary connection region 34 . The other structures are the same as those in Embodiments 1 to 3, so detailed descriptions are omitted.

21 is a schematic plan view of the silicon carbide semiconductor device of the present embodiment. In FIG. 21 , the first well region 30 of the active region and the second well region 31 of the termination region are connected via auxiliary connection regions 34 of the second conductivity type. FIG. 21 is a diagram illustrating a case in which Embodiment 1 is applied.

The auxiliary connection region 34 of the second conductivity type may be formed simultaneously with the formation of the second well region 31 by changing the ion implantation mask.

When the first well region 30 of the active region and the second well region 31 of the termination structure are completely separated and the second well region 31 is completely floating, depending on the conditions and structure, the second well region 31 is charged, and the second well region 31 is charged. There is a possibility that the insulating film on the 2-well region 31 is destroyed by insulation.

According to the silicon carbide semiconductor device of the present embodiment, the second well region 31 is connected via the auxiliary connection region 34 , the insulation breakdown of the insulating film on the second well region 31 can be more reliably broken, and the reliability can be further improved.

At this time, in a region close to the auxiliary connection region 34 near the center of each side of the silicon carbide semiconductor device of FIG. 21, a current flows through the auxiliary connection region 34 without passing through the third separation region 23, so there is a possibility that the withstand voltage is degraded. possibility. On the other hand, in the regions near the auxiliary connection regions 34 in the vicinity of the corners of the silicon carbide semiconductor device of FIG. 19 , a current flows in the second well region 31 in the lateral direction of the plane for a long time, and the second well region 31 The voltage drop caused by the sheet resistance, bipolar energization is suppressed.

In FIG. 7 of the first embodiment, the first well region 30 and the second well region 31 are connected in a large number of places, but in this embodiment, the connection between the first well region 30 and the second well region 31 is limited, so There are also fewer parts where there is a possibility of the breakdown of the withstand voltage. Therefore, degradation of the withstand voltage due to the bipolar current flowing in the second well region 31 is also limited.

In this way, according to the silicon carbide semiconductor device of the present embodiment, the possibility of insulation breakdown due to the floating of the second well region 31 can be reduced, and the reliability reduction due to bipolar conduction of the second well region 31 can be reduced to Minimum.

In addition, the area where the auxiliary connection area 34 is provided is preferably shorter than the length of the third separation area 23, for example, 1/10 or less of the length of the third separation area 23. Thereby, the possibility of occurrence of breakdown voltage can be reduced to about 1/10 or less, and the reliability of the element can be improved remarkably.

In addition, in Embodiments 1 to 4, N is used as the n-type (first conductivity type) impurity, but phosphorus or arsenic may be used. Al is used as the p-type (second conductivity type) impurity, but boron or gallium may be used.

In the MOSFETs described in Embodiments 1 to 4, the gate insulating film 50 need not necessarily be an oxide film such as silicon oxide, and may be an insulating film other than an oxide film or a combination of an insulating film other than an oxide film and an oxide film. obtained film. In addition, as the gate insulating film 50, silicon oxide obtained by thermally oxidizing silicon carbide is used, but silicon oxide deposited by a CVD method may be used. Furthermore, the present invention can also be applied to a MOSFET having a superstructure.

In addition, in the above-mentioned embodiment, the MOSFET having the gate insulating film 50 has been described, but the present invention can be applied as long as it is a unipolar device. The present invention can also be used in field effect transistors) and MESFETs (Metal-Semiconductor Field Effect Transistor).

Furthermore, in the above-described embodiment, the ohmic electrode 70 and the first Schottky electrode 71 on the source side are separately formed, but they may be formed continuously from the same material or from different materials.

In addition, the first Schottky electrode 71 and the second Schottky electrode 73 may be formed of the same material, or may be formed of different materials.

In addition, in the above-mentioned embodiment, the crystal structure, the plane orientation of the main surface, the off angle, and the respective implantation conditions were described using specific examples, but the application range is not limited to these numerical ranges.

Embodiment 5.

In this embodiment, the silicon carbide semiconductor devices according to Embodiments 1 to 4 described above are applied to a power conversion device. The present invention is not limited to a specific power conversion device, but below, as Embodiment 5, a case where the present invention is applied to a three-phase inverter will be described.

FIG. 22 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to the present embodiment is applied.

The power conversion system shown in FIG. 22 includes a power source 100 , a power conversion device 200 , and a load 300 . The power supply 100 is a DC power supply, and supplies DC power to the power conversion device 200 . The power supply 100 can be constituted by various examples, for example, a DC system, a solar cell, and a storage battery, or a rectifier circuit and an AC/DC converter connected to an AC system. In addition, the power supply 100 may be constituted by a DC/DC converter that converts the DC power output from the DC system into predetermined power.

The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300 , converts the DC power supplied from the power source 100 into AC power, and supplies the AC power to the load 300 . As shown in FIG. 16 , the power conversion device 200 includes: a main conversion circuit 201 that converts DC power into AC power and outputs it; a drive circuit 202 that outputs a drive signal for driving each switching element of the main conversion circuit 201; and a control circuit 203, The control signal for controlling the driving circuit 202 is output to the driving circuit 202 .

The load 300 is a three-phase electric motor driven by the AC power supplied from the power conversion device 200 . In addition, the load 300 is not limited to a specific application, and is a motor mounted on various electrical equipment, for example, used as a motor for a hybrid vehicle, an electric vehicle, a railway vehicle, an elevator, or an air conditioner.

Hereinafter, the details of the power conversion device 200 will be described. The main conversion circuit 201 includes a switching element and a freewheeling diode (not shown), and by switching the switching elements, the DC power supplied from the power source 100 is converted into AC power and supplied to the load 300 . There are various examples of the specific circuit configuration of the main conversion circuit 201, but the main conversion circuit 201 of the present embodiment is a 2-level three-phase full-bridge circuit, and can include six switching elements and six switching elements in antiparallel to each other. Freewheeling diode. To each switching element of the main conversion circuit 201 , the silicon carbide semiconductor device according to any one of the above-mentioned Embodiments 1 to 6 is applied. Six switching elements are connected in series for every two switching elements to form upper and lower branches, and each of the upper and lower branches forms each phase (U-phase, V-phase, and W-phase) of the full bridge circuit. Furthermore, the output terminals of each of the upper and lower branches, that is, the three output terminals of the main conversion circuit 201 are connected to the load 300 .

The drive circuit 202 generates a drive signal for driving the switching element of the main conversion circuit 201 and supplies it to the control electrode of the switching element of the main conversion circuit 201 . Specifically, in accordance with a control signal from a control circuit 203 to be described later, a drive signal for turning on the switching element and a driving signal for turning off the switching element are output to the control electrodes of each switching element. When the switching element is maintained in the ON state, the drive signal is a voltage signal (on signal) that is equal to or higher than the threshold voltage of the switching element, and when the switching element is maintained in the OFF state, the driving signal becomes the threshold value of the switching element Voltage signal below the voltage (off signal).

The control circuit 203 controls the switching elements of the main conversion circuit 201 so as to supply desired electric power to the load 300 . Specifically, based on the power to be supplied to the load 300 , the time (on time) during which each switching element of the main conversion circuit 201 should be turned on is calculated. For example, the main conversion circuit 201 can be controlled by PWM control in which the on-time of the switching element is modulated according to the voltage to be output. Then, at each time point, a control command (control signal) is output to the drive circuit 202 so that an on signal is output to the switching element to be turned on and an off signal is output to the switching element to be turned off. The drive circuit 202 outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element in accordance with the control signal.

In the power conversion device according to the present embodiment, the silicon carbide semiconductor device according to Embodiments 1 to 4 is applied as the switching element of the main conversion circuit 201, so that power conversion with low loss and improved reliability of high-speed switching can be realized. device.

In the present embodiment, an example in which the present invention is applied to a two-level three-phase inverter is described, but the present invention is not limited to this, and can be applied to various power conversion devices. In this embodiment, a 2-level power conversion device is used, but a 3-level or multi-level power conversion device may be used, and when power is supplied to a single-phase load, a single-phase inverter may be used. The present invention is applied in the device. In addition, when power is supplied to a DC load or the like, the present invention can also be applied to a DC/DC converter or an AC/DC converter.

In addition, the power conversion device to which the present invention is applied is not limited to the case where the above-mentioned load is an electric motor. For example, it can be used as a power supply device for an electric discharge machine, a laser machine, an induction heating cooker, or a non-contact power supply system, and also as a power supply device for a non-contact power supply system. Power conditioners for solar power generation systems, power storage systems, etc.

Claims (16)

1. A silicon carbide semiconductor device is characterized by comprising:

a semiconductor substrate of silicon carbide of a 1 st conductivity type;

a drift layer of a 1 st conductive type formed on the semiconductor substrate;

a plurality of 1 st well regions of the 2 nd conductivity type provided on a surface layer of the drift layer;

a plurality of 1 st isolation regions of the 1 st conductivity type formed adjacent to the 1 st well region from the surface of the 1 st well region to the drift layer;

a 1 st schottky electrode provided on the 1 st isolation region and schottky-bonded to the 1 st isolation region;

the ohmic electrode is arranged on the 1 st well region;

a 2 nd well region of the 2 nd conductivity type provided on the surface layer of the drift layer independently of the 1 st well region;

a plurality of 4 th separated regions of the 1 st conductivity type formed adjacent to the 2 nd well region from the surface of the 2 nd well region to the drift layer at intervals shorter than the plurality of 1 st separated regions;

a 2 nd schottky electrode provided on the 4 th spaced-apart region and schottky-bonded to the 1 st spaced-apart region;

a source region of the 1 st conductivity type formed in a surface layer portion of the 1 st well region;

a gate insulating film formed on the 1 st well region and the 2 nd well region;

a gate electrode formed on the gate insulating film on the 1 st well region and on the 2 nd well region;

a gate pad connected to the gate electrode and formed above the 2 nd well region; and

and a source electrode electrically connected to the 1 st Schottky electrode, the 2 nd Schottky electrode, and the ohmic electrode, and non-ohmically connected to the 2 nd well region.

2. A silicon carbide semiconductor device is characterized by comprising:

a semiconductor substrate of silicon carbide of a 1 st conductivity type;

a drift layer of a 1 st conductive type formed on the semiconductor substrate;

a plurality of 1 st well regions of the 2 nd conductivity type provided on a surface layer of the drift layer;

a plurality of 1 st isolation regions of the 1 st conductivity type formed adjacent to the 1 st well region from the surface of the 1 st well region to the drift layer;

a 1 st schottky electrode provided on the 1 st isolation region and schottky-bonded to the 1 st isolation region;

the ohmic electrode is arranged on the 1 st well region;

a 2 nd well region of the 2 nd conductivity type provided on the surface layer of the drift layer independently of the 1 st well region;

a plurality of 4 th separated regions of the 1 st conductivity type formed adjacent to the 2 nd well region from the surface of the 2 nd well region to the drift layer and formed at a higher density in the planar direction than the 1 st separated regions;

a 2 nd schottky electrode provided on the 4 th spaced-apart region and schottky-bonded to the 1 st spaced-apart region;

a source region of the 1 st conductivity type formed in a surface layer portion of the 1 st well region;

a gate insulating film formed on the 1 st well region and the 2 nd well region;

a gate electrode formed on the gate insulating film on the 1 st well region and on the 2 nd well region;

a gate pad connected to the gate electrode and formed above the 2 nd well region; and

and a source electrode electrically connected to the 1 st Schottky electrode, the 2 nd Schottky electrode, and the ohmic electrode, and non-ohmically connected to the 2 nd well region.

3. The silicon carbide semiconductor device according to claim 1 or 2,

the 1 st well region and the 2 nd well region are separated.

4. The silicon carbide semiconductor device according to any one of claims 1 to 3,

the 2 nd well region is provided with a field insulating film having a thickness larger than that of the gate insulating film, and is provided with a 2 nd contact hole formed through the field insulating film and connecting the 2 nd Schottky electrode and the source electrode.

5. The silicon carbide semiconductor device according to claim 4,

a boundary of the gate insulating film and the field insulating film is between the 1 st isolation region and the 4 th isolation region.

6. The silicon carbide semiconductor device according to any one of claims 1 to 5,

the 2 nd well region has a silicon carbide conductive layer having a lower resistivity than the 2 nd well region at an upper layer portion thereof.

7. The silicon carbide semiconductor device according to any one of claims 1 to 6,

the gate electrode is provided above the 4 th isolation region.

8. The silicon carbide semiconductor device according to any one of claims 1 to 7,

the width of the gate electrode formed above the 4 th isolation regions is larger than the width of the gate electrode formed above the 1 st isolation regions in the vicinity of the 1 st well region.

9. The silicon carbide semiconductor device according to any one of claims 1 to 8,

the 2 nd schottky electrode is formed over a portion of the 2 nd well region,

the impurity concentration of a region of the 2 nd well region in contact with the 2 nd schottky electrode is lower than the impurity concentration of a region of the 2 nd well region apart from the 2 nd schottky electrode in a depth direction.

10. The silicon carbide semiconductor device according to claim 4,

the 2 nd Schottky electrode is formed over a plurality of the 4 th escape regions formed within the 2 nd contact hole and the auxiliary region of the 2 nd conductivity type formed between the 4 th escape regions,

the auxiliary region has an impurity concentration in a region in contact with the 2 nd Schottky electrode that is lower than an impurity concentration in a region of the auxiliary region that is apart from the 2 nd Schottky electrode in a depth direction.

11. The silicon carbide semiconductor device according to any one of claims 1 to 9,

and a second conductive type 2 ground auxiliary region adjacent to the second well region with the second isolation region of the first conductive type 1 interposed therebetween and ohmically connected to the source electrode.

12. The silicon carbide semiconductor device according to claim 11,

the 4 th separated region is provided inside or between the auxiliary grounding regions in plan view.

13. The silicon carbide semiconductor device according to claim 11 or 12,

the 2 nd schottky electrode is formed so as to straddle the 2 nd well region, the 5 th isolation region, and the ground auxiliary region.

14. The silicon carbide semiconductor device according to any one of claims 11 to 13,

a2 nd ohmic electrode is provided between the ground auxiliary region and the source electrode.

15. The silicon carbide semiconductor device according to any one of claims 11 to 14,

a2 nd contact region having a 2 nd conductivity type impurity concentration higher than that of the auxiliary grounding region is provided in an upper portion of the auxiliary grounding region.

16. A power conversion device is provided with:

a main converter circuit including the silicon carbide semiconductor device according to any one of claims 1 to 15, the main converter circuit converting an input power and outputting the converted power;

a drive circuit that outputs a drive signal for driving the semiconductor device to the semiconductor device; and

and the control circuit outputs a control signal for controlling the driving circuit to the driving circuit.

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