CN111446300A - A split-gate MOSFET structure in which the thickness of the inter-gate isolation dielectric is not affected by the thickness of the gate oxide and its preparation method - Google Patents

Abstract

The invention discloses a split gate MOSFET structure in which the thickness of an isolation medium between gates is not affected by the thickness of gate oxide and a preparation method thereof. The new thermal oxidation gate isolation dielectric production method makes the thickness of the gate isolation dielectric not affected by the thickness of the gate oxide, and avoids many problems such as gate-source leakage and large gate-source capacitance caused by the defects of the gate isolation dielectric produced by the conventional thermal growth method. . The thickness of the gate oxide does not affect the thickness and quality of the isolation dielectric between the gates. The thickness of the gate oxide layer can be freely selected according to the requirements of the device parameters, which solves the problem of gate-source leakage, reduces the gate-source capacitance, and enhances the switching speed of the device. Improve the applicability of MOSFET high frequency switching power supply field.

Description

A split-gate MOSFET junction with inter-gate isolation dielectric thickness independent of gate oxide thickness Structure and preparation method thereof

technical field

The invention belongs to the technical field of semiconductor devices and semiconductor manufacturing, and particularly relates to a new thermal oxidation growth method of a split-gate MOSFET gate-to-gate isolation medium.

Background technique

Split Gate MOSFET (SGT-MOSFET for short) power device is an improved trench power MOSFET based on conventional trench MOSFET (U-MOSFET). Compared with traditional trench MOSFET power devices, it has faster switching speed, lower switching losses and better device performance.

The traditional trench MOSFET has only one layer of polysilicon in the deep trench, while the split-gate MOSFET adopts a charge-coupled structure, that is, the deep trench of the split-gate MOSFET has two layers of polysilicon, the upper polysilicon is the gate, and the lower polysilicon is the source. As shown in Figure 1. A layer of silicon dioxide film IPO (Inter Poly Oxide) is used to isolate the gate and the source between the two layers of polysilicon. The thickness, uniformity and density of the film directly determine the isolation effect between the gate and the source. The leakage current between the gate and the source, if the thickness of the gate isolation oxide film is insufficient or there are voids, it will have an adverse effect on the gate-source leakage of the device.

At present, there are mainly two ways to isolate the dielectric between the gates: Thermal oxide (Thermal oxide) and High Density Plasma Chemical Vapor Deposition (HDPCVD, High Density Plasma Chemical Vapor Deposition). The schematic longitudinal cross-section of the primary thermal oxidation growth of the gate oxide (GOX) and the inter-gate isolation dielectric (IPO) shows that the thermal growth of silicon dioxide is performed by using thermal growth after wet etching of the bottom liner oxide (Liner Oxide). In this way, the gate isolation oxide layer and the gate oxide layer (GOX) are grown on the source polycrystalline pillar and the sidewall of the trench, which has the advantages of simple process flow, low cost, and good control of channel length uniformity. The wet etching of the bottom pad oxygen has isotropic characteristics. After etching, the source polycrystalline will form a polycrystalline column. Due to the narrow size of the polycrystalline column, the shape irregularity after polycrystalline etching, and the gate The growth thickness of the inter-isolation dielectric (IPO) is limited by the thickness of the gate oxide layer (GOX) (within 1000A). The quality of the thermal oxide silicon dioxide thin layer is prone to problems, and voids or layer cracks occur, resulting in an increase in gate-source leakage or invalid. The current method to solve this problem is to use high-density plasma vapor deposition oxide layer to avoid the above-mentioned defects that are easily generated by thermal oxidation. The method increases the complexity of the process flow and the manufacturing cost, and at the same time, the uniformity of the channel length is not as good as the former.

SUMMARY OF THE INVENTION

In order to solve the above problems, the present invention provides a split-gate MOSFET structure in which the thickness of the inter-gate isolation dielectric is not affected by the thickness of the gate oxide.

Another object of the present invention is to provide a new method for thermal oxidation growth of a split-gate MOSFET inter-gate isolation dielectric with the above structure.

The object of the present invention is achieved through the following scheme: a split-gate MOSFET structure in which the thickness of the inter-gate isolation dielectric is not affected by the thickness of the gate oxide, comprising a substrate silicon wafer and an N-type epitaxial layer on the substrate, wherein: in the N-type epitaxial layer The upper surface of the epitaxial layer is etched with a trench with a depth of 4-6um, the thickness of the oxygen layer at the bottom of the trench is 4000-7000A, the source polysilicon is deposited in the oxygen layer at the bottom of the trench, and the top of the gate isolation dielectric is formed The bottom of the gate polysilicon is in contact with the top protrusion of the isolation dielectric between the gates, and the periphery is covered by a gate oxide layer.

Further, the thickness of the inter-gate isolation dielectric may be between 2000-4000A.

The thickness of the isolation medium between the gates of the present invention is thicker, which can be increased by 2 to 4 times, thereby avoiding many problems such as gate-source leakage and large gate-source capacitance caused by defects of the gate isolation dielectric produced by the conventional thermal growth method.

The present invention also provides a method for preparing a split-gate MOSFET structure in which the thickness of the inter-gate isolation dielectric is not affected by the thickness of the gate oxide, comprising the following steps:

Step 1, growing an N-type epitaxial layer 2 on the substrate 1;

Step 2, etching trenches on the upper surface of the N-type epitaxial layer 2 to a trench depth of 4-6um;

Step 3, growing a bottom pad oxide layer on the surface of the trench and the N-type epitaxial layer by thermal oxidation, and the thickness of the pad oxide layer is 4000-7000A;

In step 4, the source polysilicon 5 is deposited. Since the source polysilicon is deposited into the deep trench, a pit is left in the center of the trench after the deposition is completed;

Step 5, performing etching and etching back on the source polysilicon 5 to etch out a groove depth of 1.4um, leaving space for the subsequent growth and filling of the gate isolation medium, gate oxide layer and gate polysilicon;

In step 6, thermal growth of the inter-gate isolation medium 6 is performed, and the thermal growth thickness exceeds the surface of the trench and a protrusion is formed on the top of the polycrystalline pillar due to the isolation effect of the oxygen layer at the bottom of the thick silicon dioxide layer of the polycrystalline boundary;

Step 7, performing high temperature curing of the polycrystalline oxide layer inter-gate isolation dielectric 6, performing simultaneous wet etching of the inter-gate isolation dielectric 6 and the bottom pad oxide layer, and reserving an inter-gate isolation dielectric with a thickness of 2000-4000 A;

In step 8, the oxide growth of the gate oxide layer 7 is carried out, the thickness of the gate oxide layer 7 is selected according to the requirements of the device parameters, and finally the gate polysilicon 8 is deposited to obtain a split gate MOSFET structure in which the thickness of the isolation dielectric between the gates is not affected by the thickness of the gate oxide. .

Further, in step 7, the conditions are 1100°C for 30 minutes, and the oxygen flow rate is 0.5-2 liters/min,

The invention proposes a split gate MOSFET structure in which the thickness of the isolation dielectric between the gates is not affected by the thickness of the gate oxide and a preparation method thereof. The thermal oxidation growth of the isolation dielectric between the gates and the thermal growth of the gate oxide layer are carried out separately. The new thermal oxidation gate isolation dielectric production method makes the thickness of the gate isolation dielectric not affected by the thickness of the gate oxide, and avoids many problems such as gate-source leakage and large gate-source capacitance caused by the defects of the gate isolation dielectric produced by the conventional thermal growth method. .

The beneficial effect of the present invention is that, on the basis of the traditional split-gate MOSFET thermally oxidized inter-gate isolation dielectric process, a new process is developed, and the inter-gate isolation dielectric and the thermal growth of the gate oxide layer are carried out separately, so that the thickness and quality of the inter-gate isolation dielectric are improved. Not limited and affected by the thickness of the gate oxide, the morphology of the isolation dielectric between the gates is greatly improved, the thickness of the oxide layer of the isolation dielectric between the gates is increased, the quality of the oxide layer of the isolation dielectric between the gates is improved, and the gate-source leakage is solved. It also reduces the gate-source capacitance, enhances the switching speed, and reduces the switching losses of the MOSFET.

Description of drawings

Figure 1 is a schematic longitudinal cross-sectional view of a traditional split-gate MOSFET gate oxide (GOX) and an inter-gate isolation dielectric (IPO) grown by a thermal oxidation;

2 is a schematic structural diagram of a split gate MOSFET in which the thickness of the inter-gate isolation dielectric is not affected by the thickness of the gate oxide, and the improved structure of the split-gate MOSFET gate isolation dielectric 6, gate oxide layer 7 and gate polysilicon 8 in the figure;

3 to 8 are schematic diagrams of each preparation step of the present invention;

Description of the labels in the figure:

1——N-type substrate;

2—N-type first epitaxial layer;

3 - groove;

4 - bottom cushion oxygen layer;

5 - source polysilicon;

6——Isolation medium between gates;

7 - gate oxide layer;

8 - Gate polysilicon.

Detailed ways

As shown in FIG. 2, a split-gate MOSFET structure in which the thickness of the inter-gate isolation dielectric is not affected by the thickness of the gate oxide includes a substrate silicon wafer, an N-type epitaxial layer 2 on a substrate 1, and an N-type epitaxial layer on the N-type epitaxial layer. 2. The trench 3 with a groove depth of 4-6um is etched on the upper surface. The thickness of the pad oxide layer 4 at the bottom of the trench 3 is 4000-7000A, and the source polysilicon 5 is deposited in the pad oxide layer 4 at the bottom of the trench. The top of the gate polysilicon 8 forms a protrusion, and the bottom of the gate polysilicon 8 is in contact with the top protrusion of the inter-gate isolation dielectric 6, and the periphery is covered by a gate oxide layer.

The present embodiment provides a split-gate MOSFET structure in which the thickness of the inter-gate isolation dielectric is not affected by the thickness of the gate oxide and a preparation method thereof, which is prepared according to the following steps:

Step 1, as shown in FIG. 3, etching trench 3 is performed on the N-type epitaxial layer 2 of substrate 1, and the trench depth is about 4-6um;

Step 2, as shown in FIG. 4, a bottom pad oxide layer 4 is grown on the trench and the silicon surface by thermal oxidation, and the thickness of the oxide layer is generally 4000-7000A;

Step 3, as shown in FIG. 5, the source polysilicon 5 is deposited. Since the source polysilicon is deposited into the deep trench 3, a pit is left in the center of the trench after the deposition is completed;

Step 4, as shown in FIG. 6, the source polysilicon 5 is etched and etched back, and a groove depth of about 1.4um is etched for the subsequent growth and filling of the inter-gate isolation dielectric, gate oxide layer and gate polysilicon leave space;

Step 5, as shown in FIG. 7, thermal growth of the inter-gate isolation dielectric 6 is performed. The thickness of the thermal growth exceeds the surface of the trench 3 and is at the top of the polycrystalline pillar due to the isolation effect of the pad oxide layer at the bottom of the thick silicon dioxide layer of the polycrystalline boundary. bulges will be formed;

Step 6, as shown in FIG. 8, perform high-temperature curing of the polycrystalline oxide layer inter-gate isolation dielectric 6 under conditions of 1100° C., 30 minutes, and an oxygen flow rate of 0.5-2 liters/min. After curing, the inter-gate isolation dielectric 6 is cured. The density increases and the corrosion rate decreases; perform synchronous wet etching of the inter-gate isolation dielectric 6 and the bottom pad oxide layer 4, and reserve a thickness of about 2000-4000 for the inter-gate isolation dielectric 6, which can vary with the gate-source capacitance of the MOSFET. Free adjustment according to parameter requirements;

In step 7, as shown in FIG. 2, the oxide growth of the gate oxide layer 7 is performed. The thickness of the gate oxide layer can be freely selected according to the requirements of the device parameters, and the deposition of the gate polysilicon 8 is performed. For a split-gate MOSFET affected by the oxygen thickness, the thickness of the gate oxide layer 7 does not affect the inter-gate isolation dielectric 6 .

Claims (4)

1. A split gate MOSFET structure with the thickness of an inter-gate isolation medium not affected by the thickness of gate oxide comprises a substrate silicon wafer and an N-type epitaxial layer 2 on a substrate 1, and is characterized in that: etching a groove 3 with the groove depth of 4-6 microns on the upper surface of the N-type epitaxial layer 2, wherein the thickness of an oxygen cushion layer 4 at the bottom of the groove 3 is 4000-7000A, depositing active polycrystalline silicon 5 in the oxygen cushion layer 4 at the bottom of the groove, forming a bulge at the top end of an inter-gate isolation medium 6, and connecting the bottom of a grid polycrystalline silicon 8 with the bulge at the top end of the inter-gate isolation medium 6, wherein the periphery of the grid polycrystalline silicon is coated by a grid oxide layer.

2. The split-gate MOSFET structure of claim 1 in which the thickness of the inter-gate isolation dielectric is not affected by the thickness of the gate oxide layer, wherein: the thickness of the isolation medium between the gates is 2000-4000A.

3. A method of fabricating a split-gate MOSFET structure according to claim 1 or 2, comprising the steps of:

step 1, growing an N-type epitaxial layer 2 on a substrate 1;

step 2, etching a groove on the upper surface of the N-type epitaxial layer 2 until the groove depth is 4-6 um;

step 3, growing a bottom pad oxygen layer on the surface of the groove and the N-type epitaxial layer by a thermal oxidation method, wherein the thickness of the pad oxygen layer is 4000-7000A;

step 4, depositing source polycrystalline silicon 5, wherein the source polycrystalline silicon is deposited to the deep groove, and a pit is reserved in the center of the groove after deposition is finished;

step 5, etching and back-etching the source electrode polycrystalline silicon 5 to form a groove depth of 1.4um, and reserving a space for the growth and filling of a subsequent inter-gate isolation medium, a gate oxide layer and gate polycrystalline silicon;

step 6, carrying out thermal growth of the inter-gate isolation medium 6, wherein the thermal growth thickness exceeds the surface of the groove, and a bulge is formed at the top end of the polycrystalline column due to the isolation effect of the oxygen cushion layer at the bottom of the polycrystalline boundary thick silicon dioxide layer;

step 7, carrying out high-temperature curing on the polycrystalline oxide layer inter-gate isolation medium 6, carrying out synchronous wet etching on the inter-gate isolation medium 6 and the bottom pad oxide layer, and reserving an inter-gate isolation medium with the thickness of 2000-4000A;

and 8, carrying out oxidation growth of the gate oxide layer 7, selecting the thickness of the gate oxide layer 7 according to the parameter requirements of the device, and finally carrying out deposition of the gate polycrystalline silicon 8 to obtain the split gate MOSFET structure with the thickness of the inter-gate isolation medium not influenced by the thickness of the gate oxide.

4. The method of manufacturing a split-gate MOSFET structure according to claim 1 or 2, wherein in step 7, the conditions are 1100 ℃ for 30 minutes and the flow of oxygen is 0.5 to 2 liters/minute.

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