CN111446179A - Method and device for testing wafers - Google Patents

Abstract

The invention discloses a wafer testing method and a device, wherein the method comprises the following steps: screening out a target chip set with the approximation degree of the front-layer optical spectrum meeting a preset approximation requirement according to the front-layer optical spectrum of each chip in the wafer set to be detected; executing a to-be-tested process on the to-be-tested wafer group to form a current layer structure, and acquiring a current layer optical spectrum of the current layer structure; screening out a chipset set to be tested, wherein the difference degree of the optical spectrum of the current layer meets the preset difference requirement, according to the optical spectrum of the current layer of each chip in the target chipset set; and taking the chipset set to be tested as a test sample, and verifying the optical model of the current layer structure. The method and the device provided by the invention are used for solving the technical problems that in the prior art, the accuracy of the verified optical model is poor and the accuracy of the optical measurement result is reduced because the test sample is selected only according to the position relation between the chip and the center and the edge of the wafer. The accuracy of the optical measurement result is effectively improved.

Description

Method and device for testing wafers

technical field

The present disclosure relates to the field of semiconductors, and in particular, to a wafer testing method and apparatus.

Background technique

In the field of semiconductor technology, optical metrology techniques are often used to monitor and inspect device structural parameters (eg, feature dimensions) during semiconductor manufacturing processes. In order to ensure the accuracy of optical measurement, it is necessary to establish a spectral library and an optical model through modeling and simulation. Therefore, it is necessary to use transmission electron microscopy and other means as a reference measurement technology to test and analyze the experimentally designed wafers to calibrate the optical model.

In order to ensure the comprehensiveness of the chip used as the test sample and to verify the optical model more accurately, it is often necessary to select chips with large differences in the morphology of the current layer structure for testing after the process to be tested is performed on the wafer to form the current layer structure. Used to validate optical models. At present, the method of selecting chips from the wafer to be tested for modeling verification is to consider that the morphology of the middle chip and the edge chip on the same wafer is very different, so the coordinates of the chip on the wafer are from the center of the wafer to the edge of the wafer. Chips are selected at intervals as test samples.

However, the test samples are only selected according to the positional relationship between the chip and the wafer center and edge, and it is difficult to select samples with large differences in the layer structure formed by the process to be tested, resulting in poor accuracy of the verified optical model, thereby reducing the optical quality. The accuracy of the measurement results.

SUMMARY OF THE INVENTION

The purpose of the present disclosure is, at least in part, to solve the technical problem that the chamber of the semiconductor processing equipment in the prior art is easily contaminated by impurity particles.

In a first aspect, the present disclosure provides a wafer testing method, comprising:

According to the front-layer optical spectrum of each chip in the wafer group to be tested, a target chip set set is screened, and the target chip set set is a chip set set whose approximation degree of the front-layer optical spectrum reaches a preset approximation requirement;

Performing a process to be tested on the wafer set to be tested to form a current layer structure, and acquiring the current layer optical spectrum of the current layer structure of each chip in the target chipset set;

According to the on-layer optical spectrum of each chip in the target chip set set, a set of chip sets to be tested is screened out, and the set of chip sets to be tested is the chip set whose degree of difference of the on-layer optical spectrum reaches a preset difference requirement gather;

The optical model of the current layer structure is verified by using the set of chipsets to be tested as a test sample.

Optionally, the number of chips in the target chipset set is evenly distributed on each wafer in the wafer set to be tested; the number of chips in the set of chips to be tested is evenly distributed on the on each wafer in the wafer set to be tested.

Optionally, according to the optical spectrum of the front layer of each chip in the wafer group to be tested, screening out the target chip group set includes: according to the front layer of each chip in each wafer in the wafer group to be tested. Optical spectrum, sorting the chips in each wafer according to the spectral values, and grouping the chips in each wafer into a plurality of chip groups according to the adjacent rules; Both perform the process of determining the most similar chip set, and select the most similar chip set with the highest degree of similarity from all the determined most similar chip sets, as the target chip set set; wherein, the determining the most similar chip set The process includes: determining the similar chip group with the highest similarity to each chip group on the i-th wafer in the wafer group to be tested on each other wafer in the wafer group to be tested, and assigning Each chip group on the i-th wafer and its corresponding similar chip group are regarded as a similar chip set; wherein, each chip group on the i-th wafer is on each of the other wafers There is a similar chip set; each chip set on the i-th wafer corresponds to a similar chip set; i is greater than or equal to 1 and less than or equal to the number of wafers in the wafer set to be tested; A similar chip set with the highest degree of approximation is determined among all the similar chip sets corresponding to each chip group on the i-th wafer, as the most similar chip set of the i-th wafer.

Optionally, the orderly adjacent rules group the chips in each wafer into multiple chip groups, including: the orderly adjacent rules, and the number of chips in each of the chip groups is 2m-1 to group the chips in each wafer into n-2m+2 chip groups, wherein at least one different chip exists in every two of the chip groups; wherein m is a natural number greater than 1 , n is the number of chips on each wafer.

Optionally, the determination of the similar chip group with the highest similarity with the chip group on the i-th wafer in the wafer group to be tested on other wafers in the wafer group to be tested, including : perform the process of determining similar chip groups on each chip group on the i-th wafer and on every other wafer in the wafer group to be tested, so as to obtain the Similar chip sets on each other wafer; wherein, the process of determining the similar chip set includes: according to the reference average value of the spectral values of the j th chip set on the i th wafer, from the to-be-to-be On the kth wafer of the measurement wafer group, screen out x groups of undetermined chip groups whose average value of spectral values is closest to the reference average value, wherein x is greater than 1, j is greater than or equal to 1 and less than or equal to the ith group The number of chipsets on a wafer; k is greater than or equal to 1 and less than or equal to the number of wafers in the wafer group to be tested, and k is not equal to i; from the x group of undetermined chipsets, determine the i-th The jth chip set on the wafer is a similar chip set on the kth wafer.

Optionally, determining from the x groups of undetermined chip groups the similar chip groups of the j-th chip group on the i-th wafer on the k-th wafer, including: judging: Whether the average value of the x groups of undetermined chipsets is equal to the reference average value; if it is equal, the chipset with the smallest mean square error of spectral values in the x groups of undetermined chipsets is used as the jth chipset in the Similar chip sets on the kth wafer; if not equal to, the chip set with the smallest coefficient of variation of the spectral values among the undetermined chip sets in the x group is used as the jth chip set on the kth wafer similar chipsets.

Optionally, a similar chip set with the highest degree of similarity is determined from all the similar chip sets corresponding to each chip set on the ith wafer, as the most similar chip set of the ith wafer, including: From all the similar chip sets corresponding to each chip group on the ith wafer, the similar chip set with the smallest mean square error of spectral values is determined as the most similar chip set of the ith wafer.

Optionally, selecting the most similar chip set with the highest degree of similarity from all the determined most similar chip sets, as the target chip set set, includes: screening out the spectrum from all the determined most similar chip sets. The most similar chip set with the smallest mean square error of the value is used as the target chip set set.

Optionally, the filtering out the set of chips to be tested according to the on-layer optical spectrum of each chip in the target chip set set includes: according to the on-layer optical spectrum of each chip in the target chip set set. , sort the chip sub-wafers in the target chipset set according to the spectral values; in each wafer of the wafer group to be tested, take a as the interval step size and screen out the chip according to the step size of the sorting and other steps The chip set to be tested of a wafer is composed of the chip set to be tested of each wafer to form the set of chip sets to be tested, and a is greater than or equal to 1.

In a second aspect, the present disclosure provides a wafer testing apparatus, including:

The first screening module is used to screen out a target chip set set according to the front-layer optical spectrum of each chip in the wafer group to be tested, and the target chip set set is that the approximation of the front-layer optical spectrum reaches a preset approximation requirement set of chipsets;

an acquisition module, configured to perform the process to be tested on the wafer group to be tested, form a current layer structure, and acquire the current layer optical spectrum of the current layer structure of each chip in the target chipset set;

The second screening module, according to the local optical spectrum of each chip in the target chip set set, filters out a set of chips to be tested, and the set of chips to be tested is such that the difference degree of the optical spectrum of the current layer reaches a preset level The set of chipsets required by the difference;

The test module is used for verifying the optical model of the current layer structure by using the chip set to be tested as a test sample.

One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages:

In the wafer testing method and device provided in the embodiments of the present application, considering that the obtained difference in the current layer optical spectrum quality inspection of the current layer structure includes not only the difference between the parameters to be tested in the current layer structure, but also the front layer structure difference between. In order to ensure the accuracy of the optical model of the current layer structure, first, according to the optical spectrum of the front layer of each chip in the wafer group to be tested, the target chipset set with the approximation degree that meets the preset approximation requirements is selected to ensure that the target chipset set is in the The topographic features between the front-layer structures of the chip are as close as possible, so as to reduce the interference of the front-layer structure on the optical spectrum of the current layer structure. After the process to be tested is performed to form the current layer structure, the set of chip sets to be tested whose degree of difference meets the preset difference requirement is screened from the set of target chipsets, and the set of chip sets to be tested is used as a test sample, and the set of chip sets to be tested is selected for the current layer. The optical model of the structure is verified. Therefore, it is ensured that the test sample is a chip with the structure and morphology of the front layer as close as possible, and the structure and morphology of the current layer are as different as possible, so as to ensure the accuracy of the optical simulation modeling of the current layer structure, thereby improving the accuracy of the optical measurement results.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present disclosure more clearly, the following briefly introduces the accompanying drawings used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only the embodiments of the present disclosure. , for those of ordinary skill in the art, other drawings can also be obtained according to the provided drawings without any creative effort.

1 is a flowchart of a wafer testing method according to one or more embodiments of the present disclosure;

2 is a flowchart of screening a set of target chipsets in accordance with one or more embodiments of the present disclosure;

3 is a schematic diagram of a wafer testing apparatus according to one or more embodiments of the present disclosure.

Detailed ways

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not to scale, some details have been exaggerated for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships are only exemplary, and in practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art should Regions/layers with different shapes, sizes, relative positions can be additionally designed as desired.

In the context of this disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. element. In addition, if a layer/element is "on" another layer/element in one orientation, then when the orientation is reversed, the layer/element can be "under" the other layer/element. In the context of the present disclosure, similar or identical components may be designated by the same or similar reference numerals.

In order to better understand the above-mentioned technical solutions, the above-mentioned technical solutions will be described in detail below in conjunction with specific implementations. For the definition of the technical solutions of the present application, the embodiments of the present application and the technical features in the embodiments may be combined with each other unless there is a conflict.

According to an aspect of the present disclosure, a wafer testing method is provided, as shown in FIG. 1 , including:

Step S101 , according to the front-layer optical spectrum of each chip in the wafer group to be tested, screen out a target chipset set, and the target chipset set is a chipset set whose approximation degree of the front-layer optical spectrum reaches a preset approximation requirement;

Step S102, performing the process to be tested on the wafer group to be tested, forming a current layer structure, and acquiring the current layer optical spectrum of the current layer structure of each chip in the target chipset set;

Step S103 , according to the optical spectrum of each chip in the target chipset set, filter out a set of chip sets to be tested, and the set of chip sets to be tested is a set of chip sets whose degree of difference of the optical spectrum of the current layer meets a preset difference requirement;

In step S104, the optical model of the current layer structure is verified by using the set of the chipset to be tested as a test sample.

The current optical model verification test often defaults that the topography and dimensions of the front-layer structure on the wafer are consistent before the process to be tested is performed on the wafer group to be tested, and the optical spectrum of the front-layer structure of the front-layer structure is also the same by default. After the process to be tested is performed on the wafer group to be tested to form the current layer structure, it is theoretically believed that the current layer optical spectrum of the current layer structure only represents the parameter difference of the current layer structure, so only the distance between the center and the edge of the chip on the wafer is calculated. location to sample. However, the topography and size of chips produced by the same process on the same wafer are also different, and the topography of chips on different wafers is even different. Therefore, according to the applicant's research, during the optical model simulation, the front layer structure The difference will affect and sacrifice the accuracy of the layer structure modeling and simulation, and reduce the accuracy of the optical measurement results. Therefore, in this application, when selecting chip samples for testing, the influencing factors of the front-layer structure and the distribution characteristics of the current-layer structure are comprehensively considered to ensure that the selected samples have the smallest difference in the front-layer structure and morphology as much as possible. Chipsets with as large a difference as possible to ensure the accuracy of modeling and simulation and improve the accuracy of optical measurement results.

The detailed execution steps of the wafer testing method provided by the present application are described below with a specific embodiment:

First, a wafer group to be tested needs to be prepared, and different experimental designs can be carried out according to the characteristics of the process to be tested, so as to determine the number h of wafers in the wafer group to be tested, where h is a natural number.

Then, step S101 is performed, and according to the optical spectrum of the front layer of each chip in the wafer group to be tested, a set of target chip groups whose degree of approximation meets the preset approximation requirement is screened out. Optionally, in order to ensure that the chip structure on each wafer can be fully verified and a sufficient number of chips to be tested can be sampled, the number of chips in the target chipset set can be set to be evenly distributed on the wafer to be tested. on each wafer in the group.

It should be noted that, according to the different processes to be tested, the optical spectrum of the front layer and the optical spectrum of the current layer in this application can be scattering spectra, reflection spectra or absorption spectra, etc. The abscissa of the corresponding spectral curve can be the wavelength, and the vertical The coordinates can be light scattering intensity, reflectance or absorption, etc., which are not limited here.

The purpose of screening the set of target chipsets is to select chips whose topography and features of the front layer structure are as close as possible before the process to be tested is performed on the wafer set to be tested. Specifically, different screening methods can be selected according to different requirements for the proximity of the front-layer structure. Two examples are listed below:

The first is to determine target chipsets by wafer, and then combine them into a set of target chipsets.

That is, the chips on each wafer can be grouped according to the number of chips in the target chipset that need to be screened on each wafer. After grouping, the spectral values of each chip in each group are calculated, and the chip group with the smallest mean square error of the spectral values is used as the target chip group on the wafer. The target chipset set is composed of the target chipsets of all wafers.

The spectral value of each chip may be the average value of the ordinate parameters of the spectral curve of the chip. Or the ordinate parameter value corresponding to a certain preset key abscissa of the chip, which is not limited here.

The second is to comprehensively consider the similarity of the target chipsets of all wafers in the wafer group to be tested.

The steps of screening out a target chipset set whose degree of approximation meets the preset approximation requirement includes S1011-S1014.

As shown in FIG. 2 , first, step S1011 is performed, and according to the optical spectrum of the front layer of each chip in each wafer in the wafer group to be tested, the chips in each wafer are sorted according to the spectral values, and in order Adjacent rules group the chips in each wafer into groups of chips. The spectral value of each chip may be the average value of the ordinate parameters of the spectral curve of the chip. Or the ordinate parameter value corresponding to a certain preset key abscissa of the chip, which is not limited here.

Specifically, there are h wafers in the wafer group to be tested. Taking the i-th wafer as an example, the chips in the i-th wafer are sorted according to their spectral values from large to small or from small to large. The chips in the i-th wafer are grouped in the order of adjacent rules and the number of chips in each chipset is 2m-1, and the maximum grouping number on the i-th wafer is n-2m+2 chips group, wherein, there is at least one different chip in every two chip groups; wherein, m is a natural number greater than 1, and n is the number of chips on the i-th wafer. Repeat the above grouping steps to complete the grouping of h wafers.

Of course, in the specific implementation process, the number of chips in each chipset may also be 2m, and correspondingly, the maximum number of groups on each wafer is n-2m+1 chipsets, which is not limited here.

Of course, it is also possible to directly perform exhaustive grouping without sorting the spectral values, but the execution efficiency will be much lower than the method of first sorting and then grouping according to the adjacent rules provided in this embodiment. The grouping of adjacent rules can ensure that the spectral values of the chips in the separated chip sets are relatively close, and a large number of chip sets with large differences in the spectral values of the chips are excluded, which greatly reduces the amount of calculation.

After the grouping of all the wafers is completed, the average value and the mean square error of the spectral values of each chip group can be calculated for use in subsequent steps. Wherein, the spectral values of the chips in the chip set can be added and divided by the number of reorganized chips to obtain the average value of the spectral values of the chip set, and then the mean square error can be further calculated.

Next, step S1012 is executed to determine the similar chip group with the highest similarity to each chip group on each wafer in the wafer group to be tested with the highest similarity to it on each other wafer, and assign each chip group to its corresponding similar chip group group as a collection of similar chips.

Specifically, taking the i-th wafer as an example, the average value of the spectral values of the j-th chip group on the i-th wafer is used as the reference average value, and the k-th wafer of the wafer group to be tested is screened. The x groups of undetermined chipsets whose average spectral value is closest to the reference average. From the x groups of undetermined chip groups, a similar chip group of the jth chip group on the kth wafer is selected. Wherein, x is greater than 1, j is greater than or equal to 1 and less than or equal to the number of chipsets on the i-th wafer; k is greater than or equal to 1 and less than or equal to the number of wafers in the wafer group to be tested, and k is not equal to i. ;

Preferably, the implementation of selecting similar chipsets from the undetermined chipsets of the x groups may be as follows: first determine whether the average value of the undetermined chipsets of the x groups is equal to the reference average; The chip set with the smallest mean square error is regarded as the similar chip set of the jth chip set on the kth wafer; if not equal, the chip set with the smallest coefficient of variation of spectral values in the undetermined chip set of the x set is regarded as the jth chip set on the kth wafer. Similar chipset on the kth wafer. Specifically, this method of selecting similar chip sets according to the situation can eliminate the influence of the measurement scale, so that the determined similar chip sets have a higher approximation degree with the jth chip set.

Of course, the method of selecting similar chipsets from the x groups of undetermined chipsets can also be random selection, the chipset with the smallest mean square error, or the chip whose average value is closest to the reference average value. group, which is not limited here.

In addition to the i value, the k value is set cyclically from 1 to h (h is the number of wafers in the wafer group to be tested), and the above method is repeated to determine that the jth chip group on the ith wafer is under test. Similar chipsets on other h-1 wafers except the i-th wafer in the wafer group correspond to h-1 similar chipsets in total. Take the h-1 similar chip sets and the jth chip set as a set of similar chips.

Then, set the j value cyclically from 1 to f (f is the number of chipsets in the ith wafer), and repeat the above method, the similar chip sets of all chipsets on the ith wafer can be determined. A single wafer has f similar chip sets in total.

Then, the value of i is set cyclically from 1 to h, and the above method is repeated to determine the similar chip sets of all chip groups on each wafer. Assuming that the number of chip groups on each wafer is f, then each chip Each wafer has f similar chip sets, and the wafer group to be tested has a total of f*h similar chip sets.

Next, step S1013 is performed, and a similar chip set with the highest degree of approximation is respectively determined from a plurality of similar chip sets of each wafer, as the most similar chip set of each wafer.

Specifically, taking the ith wafer as an example, the similar chip set with the highest spectral approximation is determined from all f similar chip sets corresponding to each chip set on the ith wafer, as the ith wafer Round most like chip set. Preferably, the set of similar chips with the highest degree of approximation is the set of similar chips with the smallest mean square error of spectral values. Of course, it can also be a set of similar chips with the smallest variance, which is not limited here.

Assuming that the number of chips in each chip set is 2m-1, there are h*(2m-1) chips in each similar chip set, that is, there are h*(2m-1) spectra. Then the mean square error of the spectral values of each similar chip set is obtained by calculating the mean square error of the spectral values of the h*(2m-1) chips. The mean square error of f similar chip sets is traversed and calculated, and the similar chip set with the smallest mean square error is selected as the most similar chip set.

The i value is set cyclically from 1 to h, and the above method is repeated, the most similar chip sets of each wafer in the wafer group to be tested can be determined, and a total of h most similar chip sets.

Next, step S1014 is performed, and the most similar chip set with the highest degree of similarity is selected from all the most similar chip sets of the determined wafer set to be tested, as the target chip set set.

Optionally, the most similar chip set with the smallest mean square error of spectral values among all the most similar chip sets may be used as the target chip set set. Of course, the most similar chip set with the smallest variance can also be used as the target chip set set, which is not limited here.

The target chipset determined by the second method above not only considers the approximation of the chips selected on each wafer, but also considers the approximation of the chips selected on all the wafers in the wafer set to be tested. It can better ensure that the topographic features of the front-layer structures of all chips in the target chipset are approaching, and when used for optical model verification, it can better represent the parameter characteristics of the current structure and ensure the accuracy of optical measurement results.

Of course, in the specific implementation process, it is not limited to the above two methods for determining the target chipset, which is not limited here.

After the target chipset is determined, continue to perform steps S102 and S103, perform the process to be tested on the wafer group to be tested, form the current layer structure, and obtain the current layer optical spectrum of each chip in the target chipset set. . According to the current layer optical spectrum of each chip in the target chip set set, the chip set set to be tested is screened, and the chip set set to be tested is the chip set set whose degree of difference of the current layer optical spectrum meets the preset difference requirement.

In a specific implementation process, the process to be tested may be deposition, polishing or etching, which is not limited herein. In the specific implementation process, in order to analyze the process to be tested more comprehensively, the experimental design of the wafer group to be tested can be carried out in advance, and some process parameters of the process to be tested implemented on each wafer can be adjusted to make the The processes to be tested on each wafer in the wafer group are slightly different, so as to analyze the influence of the process parameters on the current structural performance parameters, that is, different parameter settings are allowed for the processes to be tested implemented on each wafer. For example, suppose there are 3 wafers in the wafer group to be tested, in which wafer 1 uses the standard temperature to implement the process to be tested, wafer 2 uses the standard temperature to decrease by 5 degrees to implement the process to be tested, and wafer 3 uses the standard temperature to increase by 5 degrees. degree to implement the process to be tested.

Optionally, in order to ensure that the chip structure on each wafer can be fully verified and a sufficient number of chips to be tested can be sampled, the number of chips in the set of chips to be tested can be set to be evenly distributed on the wafer to be tested. on each wafer in the circle group.

The purpose of screening the set of chips to be tested is to select chips with as large a difference in the topographical characteristics of the current layer structure as possible. Specifically, different screening methods can be selected according to different requirements for the degree of difference in the structure of the current layer. The following two examples are listed below:

The first is to preset the minimum difference between the spectral values of the chip to be tested.

That is, the minimum difference is determined in advance based on experience or experiments, and from each wafer in the wafer group to be tested, a set of target chipsets is selected, and the absolute value of the difference between the spectral values between any two chips is the same. greater than the minimum difference. Therefore, it is ensured that the spectral difference of the current layer structure of the chip set to be tested selected on each wafer is sufficiently large.

The second is to extract the chips to be tested with equal steps after sorting.

That is, firstly, according to the optical spectrum of each chip in the target chipset set, the chip wafers in the target chipset set are sorted according to the spectral values. Then, in each wafer of the wafer group to be tested, the value a greater than or equal to 1 is used as the interval step, and the chip group to be tested of the wafer is screened according to the step size of the sorting and the like. The chipset under test constitutes a set of chipsets to be tested. Among them, the value of a is determined according to the required number of chips to be tested and the required difference degree of the current layer structure.

For example, the wafer set to be tested has h wafers, and the target chipset set has 2m-1 chips on each wafer. Sort the 2m-1 chips belonging to the target chipset set on the i-th wafer in ascending order or descending order according to their spectral values. Considering that each chip requires m chips to be tested, a=1 is set, and among the 2m-1 chips that have been sorted, the chips with a step size of 2 and an interval step size of 1 are selected to form the chip set to be tested. Specifically, the chip set to be tested includes m chips with serial numbers 1, 3, 5, . The above steps are performed on h wafers, and h chip sets to be tested are obtained to form a set of chip sets to be tested.

After the set of chipsets to be tested is screened out, step S104 is performed, and the set of chipsets to be tested is used as a test sample to verify the optical model of the current layer structure.

In the specific implementation process, the method provided in this embodiment can be applied to OCD optical modeling verification of each layer, and is especially suitable for OCD optical modeling verification of complex structures, such as the optical quantity of structures such as PSR, NSR, SiGe, EPI or SIP. Modeling verification.

Specifically, a set of target chipsets with small differences in the front layer structure and morphology obtained by screening before the process to be tested is implemented, and then after the process to be tested is implemented, select the set of target chipsets with relatively small differences in the layer structure spectrum from the set of target chipsets. A large collection of chipsets to be tested is used as a test sample for reference analysis to verify the optical model simulation of the layer structure. Although there is still a slight difference in the spectrum of the front layer structure, compared with the existing chip selection method, the test sample selected by the method provided in this embodiment not only satisfies the large difference in the outline of the layer structure, but also facilitates reference analysis and verification of the model. , it can also ensure that the difference in the contour of the front layer structure is small, which reduces the error caused by the difference in the front layer structure, and is beneficial to improve the accuracy of the structural parameters obtained by the current layer structure modeling.

In another aspect, the present disclosure provides a wafer testing apparatus, as shown in FIG. 3 , comprising:

The first screening module 301 is configured to screen out a target chip set set according to the front-layer optical spectrum of each chip in the wafer group to be tested, and the target chip set set is a chip set whose approximation degree of the front-layer optical spectrum reaches a preset approximation requirement gather;

The acquisition module 302 is configured to perform the process to be tested on the wafer group to be tested, form a current layer structure, and acquire the current layer optical spectrum of the current layer structure of each chip in the target chipset set;

The second screening module 303 , according to the current layer optical spectrum of each chip in the target chipset set, filters out a set of chips to be tested, and the set of chips to be tested is a chip set whose degree of difference of the optical spectrum of the current layer reaches a preset difference requirement gather;

The test module 304 is used for verifying the optical model of the current layer structure by using the set of the chipset to be tested as a test sample.

It should be noted that the above-mentioned wafer testing device is the device corresponding to the wafer testing method provided in the foregoing embodiments, and the technical features introduced in the description of the wafer testing method are applicable to the device, which will not be repeated here.

The technical solutions in the above embodiments of the present application have at least the following technical effects or advantages:

In the wafer testing method and device provided in the embodiments of the present application, considering that the obtained difference in the current layer optical spectrum quality inspection of the current layer structure includes not only the difference between the parameters to be tested in the current layer structure, but also the front layer structure difference between. In order to ensure the accuracy of the optical model of the current layer structure, first, according to the optical spectrum of the front layer of each chip in the wafer group to be tested, the target chipset set with the approximation degree that meets the preset approximation requirements is selected to ensure that the target chipset set is in the The topographic features between the front-layer structures of the chip are as close as possible, so as to reduce the interference of the front-layer structure on the optical spectrum of the current layer structure. After the process to be tested is performed to form the current layer structure, the set of chip sets to be tested whose degree of difference meets the preset difference requirement is screened from the set of target chipsets, and the set of chip sets to be tested is used as a test sample, and the set of chip sets to be tested is selected for the current layer. The optical model of the structure is verified. Therefore, it is ensured that the test sample is a chip with the structure and morphology of the front layer as close as possible, and the structure and morphology of the current layer are as different as possible, so as to ensure the accuracy of the optical simulation modeling of the current layer structure, thereby improving the accuracy of the optical measurement results.

In the above description, technical details such as patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as those described above. Additionally, although the various embodiments have been described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

It will be apparent to those skilled in the art that various changes and modifications can be made to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, provided that such modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to cover such modifications and variations.

Claims (10)

1. A wafer testing method, comprising:

screening out a target chip set according to the front-layer optical spectrum of each chip in the wafer set to be tested, wherein the target chip set is the chip set of which the approximation degree of the front-layer optical spectrum meets the preset approximation requirement;

executing a process to be tested on the wafer group to be tested to form a current layer structure, and acquiring a current layer optical spectrum of the current layer structure of each chip in the target chip group set;

screening a chipset set to be tested according to the current-layer optical spectrum of each chip in the target chipset set, wherein the chipset set to be tested is the chipset set with the difference degree of the current-layer optical spectrum meeting the preset difference requirement;

and taking the chipset set to be tested as a test sample, and verifying the optical model of the current layer structure.

2. The method of claim 1, wherein:

the number of chips in the target chip set is uniformly distributed on each wafer in the wafer set to be tested;

the number of chips in the chipset set to be tested is uniformly distributed on each wafer in the wafer set to be tested.

3. The method of claim 1, wherein screening out a set of target chip sets according to a front-layer optical spectrum of each chip in the wafer set to be tested comprises:

sorting the chips in each wafer according to the spectrum value according to the front-layer optical spectrum of each chip in each wafer in the wafer group to be detected, and grouping the chips in each wafer into a plurality of chip groups according to the adjacent rule in sequence;

executing a process of determining a most similar chip set for each wafer, and screening out the most similar chip set with the highest approximation degree from all the determined most similar chip sets to be used as the target chip set;

wherein the process of determining the most likely set of chips comprises:

determining similar chip sets with the highest approximation degree of each chip set on the ith wafer in the wafer set to be tested on other wafers in the wafer set to be tested, and taking each chip set on the ith wafer and the corresponding similar chip set as a similar chip set; each chipset on the ith wafer corresponds to a similar chipset on each of the other wafers; each chip set on the ith wafer corresponds to a similar chip set; i is more than equal to 1 and less than or equal to the number of the wafers in the wafer group to be tested;

and determining a similar chip set with the highest approximation degree from all similar chip sets corresponding to all chip sets on the ith wafer to serve as the most similar chip set of the ith wafer.

4. The method of claim 3, wherein the sequentially adjacent rule groups the chips in each wafer into a plurality of chip groups, comprising:

according to the adjacent rule in sequence, the chips in each wafer are grouped into n-2m +2 chip groups by the number of the chips of each chip group being 2m-1, wherein at least one different chip is arranged in each two chip groups; wherein m is a natural number greater than 1, and n is the number of chips on each wafer.

5. The method of claim 3, wherein the determining similar chip sets on other wafers in the set of wafers to be tested that each chip set on the ith wafer in the set of wafers to be tested has a highest degree of similarity thereto comprises:

executing a process of determining similar chip sets on each chip set on the ith wafer on each other wafer in the wafer set to be tested so as to obtain the similar chip sets of each chip set on each other wafer;

wherein the process of determining similar chipsets comprises:

screening x groups of undetermined chip sets with the average value of the spectrum values closest to the reference average value from the k wafer of the wafer group to be detected according to the reference average value of the spectrum values of the j chip set on the ith wafer, wherein x is larger than 1, j is larger than equal 1 and is smaller than or equal to the number of the chip sets on the ith wafer; k is more than or equal to 1 and less than or equal to the number of wafers in the wafer group to be tested, and k is not equal to i;

and determining a similar chip set of the jth chip set on the ith wafer on the kth wafer from the x groups of chip sets to be determined.

6. The method of claim 5, wherein said determining from said x sets of pending chip sets a similar chip set of said jth chip set on said ith wafer to said kth wafer comprises:

judging whether the average value of the x groups of the to-be-determined chip sets is equal to the reference average value or not;

if yes, taking the chip set with the minimum mean square error of the spectrum values in the x groups of undetermined chip sets as a similar chip set of the jth chip set on the kth wafer;

and if not, taking the chip set with the minimum coefficient of variation of the spectral values in the x groups of pending chip sets as a similar chip set of the jth chip set on the kth wafer.

7. The method of claim 3, wherein determining a similar chip set with the highest approximation degree from all similar chip sets corresponding to each chip set on the ith wafer as the most similar chip set of the ith wafer comprises:

and determining a similar chip set with the minimum mean square deviation of the spectral values from all similar chip sets corresponding to all chip sets on the ith wafer to serve as the most similar chip set of the ith wafer.

8. The method of claim 3, wherein the selecting a most similar chip set with a highest approximation from all the determined most similar chip sets as the target chip set comprises:

and screening out the minimum similar chip set with the minimum mean square error of the spectrum values from all the determined most similar chip sets as the target chip set.

9. The method of claim 1, wherein screening out the set of chipsets to be tested according to the current-layer optical spectrum of each chip in the target chipset set comprises:

sorting the chip sub-wafers in the target chipset set according to the current-layer optical spectrum of each chip in the target chipset set;

in each wafer of the wafer group to be tested, screening out the chip group to be tested of the wafer according to the sorting equal step length by taking a as an interval step length, and forming the chip group to be tested by the chip group to be tested of each wafer, wherein a is more than or equal to 1.

10. A wafer test apparatus, comprising:

the first screening module is used for screening a target chip set according to the front-layer optical spectrum of each chip in the wafer set to be tested, wherein the target chip set is the chip set of which the approximation degree of the front-layer optical spectrum meets the preset approximation requirement;

the acquisition module is used for executing a process to be tested on the wafer group to be tested, forming a current layer structure and acquiring a current layer optical spectrum of the current layer structure of each chip in the target chip group set;

the second screening module screens out a chipset set to be tested according to the current-layer optical spectrum of each chip in the target chipset set, wherein the chipset set to be tested is the chipset set of which the difference degree of the current-layer optical spectrum meets the preset difference requirement;

and the test module is used for verifying the optical model of the current layer structure by taking the chipset set to be tested as a test sample.

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