CN111446177A - System-in-package method and structure of heterogeneous integrated chip - Google Patents

Abstract

The invention provides a system-level packaging method and structure for heterogeneous integrated chips, comprising: pasting the bottom surfaces of a plurality of substrate chips on the carrier to form a first integrated transfer board; The board forms a first plastic sealing layer, and the substrate chip and the first plastic sealing layer form a first plastic sealing body; a mechanical or chemical polishing process is performed on the top of the first plastic sealing body to expose a plurality of electrical circuits of the substrate chips. lead-out part; forming a metal interconnection layer and a dielectric layer on the top surface of a plurality of the substrate chips, the metal interconnection layer is electrically connected with the electrical lead-out parts of the plurality of the substrate chips; connecting a plurality of the heterogeneous chips Interconnecting to the first integrated transfer board to form a second integrated transfer board; performing a mechanical or chemical polishing process on the top of the second integrated transfer board, so as to make the absolute same height; remove the first overmolded body from the slide.

Description

System-in-package method and structure of heterogeneous integrated chip

technical field

The present invention relates to the technical field of semiconductor packaging, in particular to a system-level packaging method and structure for heterogeneous integrated chips.

Background technique

As new semiconductor application fields such as 5G, artificial intelligence (AI), automotive electronics, Internet of Things (IoT), and high-efficiency computing (HPC) are in full bloom, the advanced wafer manufacturing process is moving towards 7, 5, and 3 nm, but with the gradual development of Moore's Law Approaching the physical limit, one of the best ways to extend Moore's Law is advanced packaging technology, including fan-out wafer level packaging (FOWLP), 2.5D/3DIC packaging, and further into 3D wafer stack packaging capable of heterogeneous integration. SiP packaged modules that meet heterogeneous integration requirements are bound to have greater energy requirements.

Through silicon via technology (TSV) realizes vertical interconnection between die and die, and interconnects between chips by drilling through holes on Si, without wire bonding, effectively shortening the length of interconnect lines, reducing signal transmission delay and loss , improve signal speed and bandwidth, reduce power consumption and package size, is to achieve multi-function, high performance, high reliability and lighter, thinner and smaller chip system-in-package. Since the 3D TSV packaging process is immature in design, mass production, testing and supply chain, and the process cost is high, the industry currently adopts the 2.5D connection layer packaging form between 2D and 3D. A connection layer is added in between, which greatly improves the input and output (I/O) signal density of the package.

As the size of solder joints gradually decreases to 3-5μm, the system-level integrated packaging of heterogeneous chips, including chips with different functions, different generations, and different packaging forms, has become an effective solution to the application problems of the emerging semiconductor industry. The traditional integration form cannot unify the chips of various heterogeneous concepts in the same package. It often realizes the joint application of different functions or generation chips through the PCB circuit board. The increase has a significant limiting effect, and many factors that affect the performance of the chip, such as parasitic capacitance and inductance, are prone to appear in the package, which is not conducive to signal transmission. To sum up, the existing technology cannot realize the heterogeneous integration of all packaged chips.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a system-level packaging method and structure for heterogeneous integrated chips, so as to solve the problem that the existing heterogeneous chips cannot be integrated and packaged.

In order to solve the above-mentioned technical problems, the present invention provides a system-level packaging method of a heterogeneous integrated chip, and the system-level packaging method of the heterogeneous integrated chip includes:

pasting the bottom surfaces of the plurality of substrate chips on the carrier to form a first integrated adapter board;

A first plastic encapsulation layer is formed on the first integrated transition board, and a first plastic encapsulation body is formed by the substrate chip and the first plastic encapsulation layer;

performing a mechanical or chemical polishing process on the top of the first plastic package to expose a plurality of electrical lead-out portions of the substrate chips;

A metal interconnection layer and a dielectric layer are fabricated on the top surfaces of the plurality of substrate chips, and the metal interconnection layer is electrically connected to the electrical lead-out portions of the plurality of substrate chips;

interconnecting a plurality of the heterogeneous chips to the first integrated interposer to form a second integrated interposer;

Carrying out a mechanical or chemical polishing process on the top of the second integrated interposer, so that the absolute heights of the plurality of heterogeneous chips are the same;

The first molding is removed from the slide.

Optionally, in the system-in-package method for heterogeneous integrated chips, performing a mechanical polishing process on the top of the second integrated transition board includes:

A second plastic encapsulation layer is formed on the second integrated transition board, and a second plastic encapsulation body is formed by the heterogeneous chip and the second plastic encapsulation layer;

A mechanical or chemical polishing process is performed on the top of the second plastic package to make the top of the second plastic package flat and smooth.

Optionally, in the system-in-package method for heterogeneous integrated chips, forming the first plastic encapsulation layer or the second plastic encapsulation layer includes:

The first plastic sealing layer or the second plastic sealing layer is formed by a compression molding process, a transfer molding process, a liquid sealing molding process, a vacuum lamination process, or a spin coating process;

The material of the first plastic sealing layer or the second plastic sealing layer includes one of polyimide, silica gel and epoxy resin.

Optionally, in the system-in-package method of the heterogeneous integrated chip, making a metal interconnection layer and a dielectric layer on top of a plurality of the substrate chips includes:

A chemical vapor deposition process or a physical vapor deposition process is used to form a deposition layer on the top surface of the substrate chip, and the deposition layer is etched to form a patterned dielectric layer;

A metal interconnection layer is formed on the surface of the dielectric layer by using a chemical vapor deposition process, an evaporation process, a sputtering process, an electroplating process or an electroless plating process, and the metal interconnection layer is etched and patterned;

The metal interconnect layer is made to lead out the electrical properties of the electrical leads of the substrate chip to the pins of the heterogeneous chip.

Optionally, in the system-in-package method for heterogeneous integrated chips, the metal interconnection layer includes a front-side re-distribution wiring layer or metal conductive bumps, and the electrical lead-out portion is electrically connected to the heterogeneous chip, The heterogeneous chip is disposed on the metal conductive bump by flip-chip bonding.

Optionally, in the system-in-package method of the heterogeneous integrated chip, the substrate chip also includes:

a conductive through hole, the conductive through hole is arranged through the inside of the substrate chip, and the conductive through hole is electrically connected to the electrical lead-out portion;

The back metal layer, the back metal layer realizes the electrical connection with the electrical lead-out portion by electrically connecting the conductive through holes;

The external solder balls are arranged on the external pads of the back metal layer.

Optionally, in the system-in-package method for heterogeneous integrated chips, an underfill layer is formed between the heterogeneous chips and the substrate chip.

Optionally, in the system-level packaging method for heterogeneous integrated chips, an adhesive film is provided on the carrier, and the material of the adhesive film is a bonding film.

Optionally, in the system-in-package method for heterogeneous integrated chips, the thickness of the first integrated transition board is 50 microns to 200 microns, and the thickness of the second integrated transition board is 100 microns to 100 microns. 300 microns.

The present invention also provides a system-level packaging structure of a heterogeneous integrated chip, comprising:

Multiple substrate chips;

a first plastic sealing layer, the first plastic sealing layer covers the substrate chip and the top of the carrier;

a plurality of electrical lead-out portions of the substrate chips exposed on the top of the first plastic sealing layer;

The metal interconnection layer and the dielectric layer are located on the top of the first plastic sealing layer, and the metal interconnection layer is electrically connected with the electrical lead-out portions of the plurality of substrate chips;

A plurality of heterogeneous chips are located on top of the metal interconnection layer and the dielectric layer and are electrically connected with the metal interconnection layer and the dielectric layer, and the absolute heights of the heterogeneous chips are the same.

In the system-level packaging method and structure for heterogeneous integrated chips provided by the present invention, multiple heterogeneous chips are welded on the first integrated transition board and polished, so that the absolute heights of the multiple heterogeneous chips are the same and satisfy the requirement of It meets the integration requirements of heterogeneous chips, and solves the problem that the thickness of heterogeneous chips is inconsistent and affects subsequent assembly.

Further, by pasting a plurality of silicon substrate chips on the carrier to form a first integrated transfer board, and forming a first plastic sealing layer on the first integrated transfer board and polishing, it is realized that a silicon substrate with good test performance is used for packaging, cost reduction effect.

Furthermore, by plastic-sealing the wafer on the first integrated adapter board, a reconstructed wafer is formed, which is conducive to subsequent patching, holding and chip thinning, and improves production efficiency; in addition, different systems are realized based on different adapter boards. interconnect, improve transmission efficiency and improve performance.

The invention separates the wafer plastic packaging process from the wafer tape-out process, avoids the influence of the plastic packaging wafer warpage on the packaging front process, does not require temporary bonding and debonding processes, reduces process difficulty and reduces process costs.

Description of drawings

1 to 10 are schematic diagrams of a system-in-package method for heterogeneous integrated chips according to an embodiment of the present invention;

As shown in the figure: 10- silicon substrate chip; 11- electrical lead-out part; 12- conductive silicon via; 13- external solder ball; 20- carrier; 21- adhesive film; 30- first plastic sealing layer; Interconnection layer and dielectric layer; 50-heterogeneous chip; 51-underfill layer; 52-micro bump; 60-second plastic sealing layer; 101-first integrated transfer board; 102-first plastic sealing body; 103 - the second integrated adapter board; 104 - the second plastic body.

Detailed ways

The system-level packaging method and structure of the heterogeneous integrated chip proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become apparent from the following description and claims. It should be noted that, the accompanying drawings are all in a very simplified form and in an inaccurate scale, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.

The core idea of the present invention is to provide a system-level packaging method and structure for heterogeneous integrated chips, so as to solve the problem that the existing heterogeneous chips cannot be integrated and packaged.

In order to realize the above idea, the present invention provides a system-level packaging method and structure for heterogeneous integrated chips. The system-level packaging method for heterogeneous integrated chips includes: pasting the bottom surfaces of a plurality of substrate chips on the carrier sheet, forming a first integrated transfer board; forming a first plastic encapsulation layer on the first integrated transfer board, and forming a first plastic encapsulation body with the substrate chip and the first plastic encapsulation layer; a mechanical or chemical polishing process, exposing the electrical lead-out parts of a plurality of the substrate chips; forming a metal interconnection layer and a dielectric layer on the top surfaces of the plurality of the substrate chips, the metal interconnection layer and the plurality of the substrates The electrical lead-out parts of the chips are electrically connected; a plurality of the heterogeneous chips are interconnected to the first integrated transfer board to form a second integrated transfer board; the top of the second integrated transfer board is mechanically or a chemical polishing process, so that the absolute heights of the plurality of heterogeneous chips are the same; and the first plastic package is removed from the carrier.

<Example 1>

This embodiment provides a system-level packaging method for a heterogeneous integrated chip. As shown in FIGS. 1 to 10 , the system-level packaging method for a heterogeneous integrated chip includes: fabricating a plurality of silicon substrate chips 10 ; The silicon substrate chip 10 faces away from a carrier 20 and is concentrated on the carrier 20 to form a first integrated transition board 101 ; as shown in FIG. 2 , a first plastic package is formed on the first integrated transition board 101 layer 30, the silicon substrate chip 10 and the first plastic sealing layer 30 form a first plastic sealing body 102; as shown in FIG. As shown in FIG. 4 , a metal interconnection layer and a dielectric layer 40 are formed on the top of the plurality of silicon substrate chips 10 , and the metal interconnection layer is connected with the plurality of The electrical lead-out portion 11 of the silicon substrate chip 10 is electrically connected; as shown in FIG. 5 , a plurality of heterogeneous chips 50 are provided; and a plurality of the heterogeneous chips 50 are interconnected to the first integrated transition board 101 to form The second integrated adapter plate 103; as shown in FIG. 6, a mechanical or chemical polishing process is performed on the top of the second integrated adapter plate 103, so that the absolute heights of the plurality of heterogeneous chips 50 are the same; as shown in FIG. As shown in FIG. 7 , the first plastic package 102 is removed from the carrier sheet 20 .

In an embodiment of the present invention, as shown in FIGS. 8 to 9 , in the system-in-package method for heterogeneous integrated chips, performing a mechanical polishing process on the top of the second integrated transition board 103 includes: A second plastic encapsulation layer 60 is formed on the second integrated transfer board 103 , and the foreign chip 50 and the second plastic encapsulation layer 60 form a second plastic encapsulation body 104 ; A mechanical or chemical polishing process is used to make the top of the second plastic package 104 flat and smooth. The purpose of this process is also to achieve the same absolute height of the plurality of heterogeneous chips 50; the first plastic package 102 is removed from the After the carrier 20 is removed, the system-in-package structure of the heterogeneous integrated chip is shown in FIG. 10 .

In another embodiment of the present invention, in the system-in-package method for heterogeneous integrated chips, forming the first plastic encapsulation layer 30 or the second plastic encapsulation layer 60 includes: adopting a compression molding process, transfer molding process, liquid sealing molding process, vacuum lamination process, or spin coating process to form the first plastic sealing layer 30 or the second plastic sealing layer 60; the material of the first plastic sealing layer 30 or the second plastic sealing layer 60 Including one of polyimide, silicone, epoxy and similar materials.

In an embodiment of the present invention, in the system-in-package method for heterogeneous integrated chips, fabricating a metal interconnection layer and a dielectric layer 40 on top of the plurality of silicon substrate chips 10 includes: using chemical vapor deposition process or physical vapor deposition process to deposit a deposition layer on the top surface of the silicon substrate chip 10, and etch the deposition layer to form a patterned dielectric layer; adopt chemical vapor deposition process, evaporation process, sputtering process process, electroplating process or electroless plating process to form a metal interconnection layer on the surface of the dielectric layer, and perform etching and patterning on the metal interconnection layer; The electrical properties of the electrical lead-out portion 11 are led out to the pins of the heterogeneous chip 50 .

In other embodiments of the present invention, in the system-in-package method for heterogeneous integrated chips, the metal interconnection layer includes a front-side redistribution wiring layer or metal conductive bumps, and the electrical lead-out portion 11 is electrically connected The heterogeneous chip 50 is disposed on the metal conductive bump by flip-chip bonding. In the system-in-package method for heterogeneous integrated chips, the silicon substrate chip 10 further includes: conductive through-silicon vias 12 , and the conductive through-silicon vias 12 are arranged through the inside of the silicon substrate chip 10 , so The conductive through-silicon hole 12 is electrically connected to the electrical lead-out portion 11; the back metal layer is electrically connected to the conductive through-silicon hole 12 to achieve electrical connection with the electrical lead-out portion 11; external solder balls 13. The external solder balls 13 are arranged on the external bonding pads of the back metal layer. In the above embodiments, the silicon substrate chip 10 is used for illustration, but those skilled in the art should understand that the substrate chip 10 may include various semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate chip 10 may also be made of an electrically non-conductive material such as glass, plastic, or a sapphire wafer.

In addition, in the system-in-package method for heterogeneous integrated chips, an underfill layer 51 is formed between the heterogeneous chips 50 and the silicon substrate chip 10 . In the system-in-package method for heterogeneous integrated chips, the carrier sheet 20 has an adhesive film 21, and the material of the adhesive film 21 can be a bonding film. In the system-in-package method for heterogeneous integrated chips, the thickness of the first integrated transition board 101 is 50 μm˜200 μm, and the thickness of the second integrated transition board 103 is 100 μm˜300 μm .

In the system-level packaging method and structure of the heterogeneous integrated chips provided by the present invention, the multiple heterogeneous chips 50 are soldered on the first integrated interposer 101 and polished so that the absolute height of the multiple heterogeneous chips 50 is equal to Similarly, the integration requirements of the heterogeneous chips 50 are met, and the problem that the thickness of the heterogeneous chips 50 is inconsistent and affects subsequent assembly is solved.

Further, by pasting a plurality of silicon substrate chips 10 on the carrier 20 to form a first integrated interposer 101 , and forming a first plastic encapsulation layer 30 on the first integrated interposer 101 and polishing, it is possible to achieve a good test performance. The silicon substrate is used for packaging, which has the effect of reducing cost.

Furthermore, by performing wafer plastic encapsulation on the first integrated adapter board 101 to form a reconstructed wafer, it is beneficial to subsequent patching, holding and chip thinning, thereby improving production efficiency; in addition, different systems can be realized based on different adapter boards. interconnect, improve transmission efficiency and improve performance.

The invention separates the wafer plastic packaging process from the wafer tape-out process, avoids the influence of the plastic packaging wafer warpage on the packaging front process, does not require temporary bonding and debonding processes, reduces process difficulty and reduces process costs.

To sum up, the above embodiments have described in detail different solutions of the system-in-package method for heterogeneous integrated chips. Of course, the present invention includes but is not limited to the configurations listed in the above embodiments, any configuration provided in the above embodiments. The content transformed on the basis of the type all belong to the scope of protection of the present invention. Those skilled in the art can draw inferences from the contents of the foregoing embodiments.

<Example 2>

This embodiment also provides a system-level packaging structure for heterogeneous integrated chips, as shown in FIG. 7 , including: a plurality of silicon substrate chips 10 ; a first plastic sealing layer 30 covering the silicon substrate The tops of the chip 10 and the carrier 20 ; the electrical lead-out portions 11 of the plurality of silicon substrate chips 10 are exposed on the top of the first plastic sealing layer 30 ; the metal interconnection layer and the dielectric layer 40 are located on the first A top of the plastic packaging layer 30, the metal interconnection layer is electrically connected to the electrical lead-out portions 11 of the plurality of silicon substrate chips 10; a plurality of heterogeneous chips 50 are located on the top of the metal interconnection layer and the dielectric layer 40 And electrically connected with the metal interconnection layer and the dielectric layer 40 , the absolute height of the heterogeneous chip 50 is the same. In another embodiment of the present invention, as shown in FIG. 10 , the system-in-package structure of the heterogeneous integrated chip may further include a second packaging layer 60 .

An embodiment of the present invention provides a system-in-package structure of a heterogeneous integrated chip, including: a silicon substrate chip 10, wherein a plurality of conductive through-silicon vias 12 are opened on the silicon substrate chip 10, and the silicon substrate chip 10 has The bottom is provided with a plurality of external solder balls 13 ; the heterogeneous chip 50 is provided with a plurality of small micro bumps 52 at the bottom, and the heterogeneous chip 50 is fixedly installed through the small micro bumps 52 On the silicon substrate chip 10, the heterogeneous chip 50 is electrically connected to the silicon substrate chip 10 through the small bumps 52; the heterogeneous chip 50 may include a 3D-IC chip, the 3D-IC chip The IC chip is flip-chip welded on the silicon substrate chip 10 through micro-bumps and the conductive through-silicon vias 12 , and the 3D-IC chip is connected to the silicon substrate through the micro-bumps and the conductive through-silicon vias 12 . The chip 10 is electrically connected.

In the system-in-package structure of the heterogeneous integrated chips described in the above-mentioned embodiments of the present invention, the silicon substrate chip 10 is used to carry various chips, and the silicon substrate chip 10 is provided with conductive lines for each heterogeneous chip The electrical connection between each other is realized; the silicon substrate chip 10 is adhered and mounted on the carrier board 20 through the external solder balls 13 , and the silicon substrate chip 10 is provided with a plurality of the conductive through-silicon holes 12 , The conductive through-silicon vias 12 are penetratingly provided from the upper surface to the lower surface of the silicon substrate chip 10 , and the conductive through-silicon vias 12 can conduct electricity, so the small bumps 52 are used in the form of flip-chip bonding The heterogeneous chip 50 mounted on the silicon substrate chip 10 can be electrically connected to the silicon substrate chip 10 through the conductivity of the small bumps 52 and the conductive through-silicon vias 12 . The heterogeneous chip 50 is a more advanced 3-5 μm bump chip; the 3D-IC chip is electrically and mechanically connected to the silicon substrate chip 10 through the micro-bumps and the conductive through-silicon vias 12 ; This part can be regarded as a COWOS package, the difference is that the inner 3D-IC chip and the more advanced 3-5 μm heterogeneous chip 50 are co-packaged on the silicon substrate chip 10 .

The silicon substrate chip may also be provided with a wire bonding chip, the bottom of the wire bonding chip 9 is coated with a TIM material, and the wire bonding chip is bonded to the silicon substrate chip through the TIM material. install.

Wherein, a wire bonding wire is provided on the wire bonding chip, and the wire bonding chip is electrically connected to the silicon substrate chip through the wire bonding wire.

In the system-in-package structure of the heterogeneous integrated chip according to the above-mentioned embodiment of the present invention, the bottom of the wire bonding chip is bonded to the silicon substrate chip through the TIM material, and the wire bonding wire connects the The wire bonding chip is connected to the silicon substrate chip, so that the wire bonding chip can be electrically connected to the silicon substrate chip; at the same time, the TIM material is provided at the bottom of the wire bonding chip, so the wire The bottom of the bonded chip has better heat dissipation performance.

Wherein, a flip chip may also be provided on the silicon substrate chip, the flip chip is mounted on the silicon substrate chip in the form of flip-chip bonding through the micro-bumps, and the flip chip is mounted on the silicon substrate chip through the micro-bumps. The micro-bumps are electrically connected to the silicon substrate chip.

In the system-in-package structure of the heterogeneous integrated chip described in the above-mentioned embodiment of the present invention, the flip-chip can also be mounted on the silicon substrate chip 10, and the flip-chip is a lower-generation chip such as MEMS, RFIC and other types of chips; the flip chip is electrically connected to the silicon substrate chip through the micro bumps, so the flip chip can be electrically connected to other chips through the micro bumps and the silicon substrate chip. connect.

Wherein, a passive device is mounted on the silicon substrate chip, and the passive device is electrically connected to the silicon substrate chip 10 .

In the system-in-package structure of the heterogeneous integrated chip according to the above-mentioned embodiment of the present invention, the passive device can also be mounted on the silicon substrate chip, so the silicon substrate chip realizes the integration of various components. Effective integration improves the integration of functions.

In the system-in-package structure of the heterogeneous integrated chip according to the above-mentioned embodiment of the present invention, the bottom of the silicon substrate chip is welded and fixed to the PCB board through the external solder balls, and the PCB board is used to carry the entire package structure body.

The system-in-package structure of the heterogeneous integrated chip described in the above-mentioned embodiment of the present invention utilizes the external solder balls 13 , micro-bumps, small micro-bumps 52 , conductive through-silicon vias 12 and silicon substrate chips 10 to combine different functions Chips, chips of different generations, chips of different packaging types and chips of different dimensions are packaged uniformly, and other passive devices 13 are also installed on the silicon substrate chip, which effectively improves the integration of functions and reduces the number of chips. Occupying space on the PCB board, and uniformly packaging different chips at the same time is conducive to saving processing steps, so that the packaging efficiency has been improved.

The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the various embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant part can be referred to the description of the method part.

The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention according to the above disclosure all belong to the protection scope of the claims.

Claims (10)

1. A system-in-package method of a heterogeneous integrated chip is characterized by comprising the following steps:

adhering the bottom surfaces of the substrate chips to the chip carrier to form a first integrated adapter plate;

forming a first plastic package layer on the first integrated adapter plate, wherein the substrate chip and the first plastic package layer form a first plastic package body;

carrying out mechanical or chemical polishing process on the top of the first plastic package body to expose the electric leading-out parts of the substrate chips;

manufacturing a metal interconnection layer and a dielectric layer on the top surfaces of the substrate chips, wherein the metal interconnection layer is electrically connected with the electric leading-out parts of the substrate chips;

interconnecting a plurality of said heterogeneous chips to said first integrated interposer to form a second integrated interposer;

performing a mechanical or chemical polishing process on the top of the second integrated interposer to make the absolute heights of the heterogeneous chips the same;

and removing the first plastic package body from the slide sheet.

2. The system-in-package method of a heterogeneous integrated chip according to claim 1, wherein the mechanical polishing process on the top of the second integrated interposer comprises:

forming a second plastic package layer on the second integrated adapter plate, wherein the heterogeneous chip and the second plastic package layer form a second plastic package body;

and carrying out mechanical or chemical polishing process on the top of the second plastic package body so as to enable the top of the second plastic package body to be flat and smooth.

3. The system-in-package method of a heterogeneous integrated chip according to claim 2, wherein forming the first molding compound layer or the second molding compound layer comprises:

forming the first plastic packaging layer or the second plastic packaging layer by adopting a compression molding process, a transfer molding process, a liquid seal molding process, a vacuum lamination process or a spin coating process;

the first plastic package layer or the second plastic package layer is made of one of polyimide, silica gel and epoxy resin.

4. The system-in-package method of a hetero-integrated chip according to claim 1, wherein the fabricating of the metal interconnection layer and the dielectric layer on top of the plurality of substrate chips comprises:

depositing a deposition layer on the top surface of the substrate chip by adopting a chemical vapor deposition process or a physical vapor deposition process, and etching the deposition layer to form a patterned dielectric layer;

forming a metal interconnection layer on the surface of the dielectric layer by adopting a chemical vapor deposition process, an evaporation process, a sputtering process, an electroplating process or a chemical plating process, and etching the metal interconnection layer for patterning;

and leading the electrical property of the electrical lead-out part of the substrate chip out to the pins of the heterogeneous chip by the metal interconnection layer.

5. The system-in-package method of a hetero-integrated chip according to claim 4, wherein the metal interconnection layer comprises a front-side redistribution wiring layer or a metal conductive bump, the electrical lead-out portion electrically connects the hetero-chip, and the hetero-chip is disposed on the metal conductive bump by flip-chip bonding.

6. The system-in-package method of a heterogeneous integrated chip according to claim 5, wherein the substrate chip further comprises:

the conductive through hole is arranged in the substrate chip and electrically connected with the electric leading-out part;

the back metal layer is electrically connected with the conductive through hole to realize the electrical connection with the electrical lead-out part;

and the external solder balls are arranged on the external bonding pads of the back metal layer.

7. The system-in-package method of a heterogeneous integrated chip according to claim 1, wherein an underfill layer is formed between the heterogeneous chip and the substrate chip.

8. The system-in-package method of a hetero-integrated chip according to claim 1, wherein the carrier has an adhesive film thereon, and the adhesive film is made of a bonding film.

9. The system-in-package method of a heterogeneous integrated chip according to claim 1, wherein the thickness of the first integrated interposer is 50 to 200 microns, and the thickness of the second integrated interposer is 100 to 300 microns.

10. A system-in-package structure of a heterogeneous integrated chip, comprising:

a plurality of substrate chips;

the first plastic packaging layer covers the top of the substrate chip and the top of the slide glass;

a plurality of electrical leads of the substrate chips exposed on top of the first molding layer;

the metal interconnection layer and the dielectric layer are positioned at the top of the first plastic package layer, and the metal interconnection layer is electrically connected with the electric leading-out parts of the substrate chips;

and the heterogeneous chips are positioned on the tops of the metal interconnection layer and the dielectric layer and are electrically connected with the metal interconnection layer and the dielectric layer, and the absolute heights of the heterogeneous chips are the same.

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