CN111435819B

CN111435819B - Step-down hysteresis type switch converter and control method thereof

Info

Publication number: CN111435819B
Application number: CN201911234370.0A
Authority: CN
Inventors: 陈钢; 翁建城; 魏荣臣
Original assignee: Zhuhai Jieli Technology Co Ltd
Current assignee: Zhuhai Jieli Technology Co Ltd
Priority date: 2019-12-05
Filing date: 2019-12-05
Publication date: 2021-11-23
Anticipated expiration: 2039-12-05
Also published as: CN111435819A

Abstract

The invention discloses a step-down hysteresis switching converter and a control method thereof, wherein the switching converter comprises: a switch control module for controlling the turn-on and turn-off of upper and lower switch tubes; the switch control module It has a low power consumption mode; the switching converter also includes: a low power consumption control logic module, which is connected to the switch control module. The low power consumption control logic module is used to detect the working state of the switch control module, and output and work state based on the working state The corresponding control signal is used to control the working power consumption mode of the switch control module; when the low power consumption control logic module detects that the working state meets the low power consumption condition, the low power consumption control logic module outputs the low power consumption control logic to the switch control module , so that the switch control module works in a low power consumption mode. While reducing the complexity of the circuit structure, the power consumption of the step-down hysteresis switching converter is reduced, and the conversion efficiency is improved.

Description

Step-down hysteresis type switch converter and control method thereof

Technical Field

The invention relates to the technical field of switch electronic circuits, in particular to a buck hysteresis type switch converter and a control method thereof.

Background

In recent years, with the rapid popularization of wireless true bluetooth headsets and the like, the problem of short endurance time existing in the use process is amplified infinitely due to the small battery capacity of the wireless true bluetooth headsets, and how to improve the endurance time of the battery, reduce the energy loss of a chip and improve the service efficiency of a power supply is the most urgent problem to be solved in many markets at present. There are three main types of buck switching converters currently available: voltage mode, current mode, hysteresis mode.

For the conventional current mode and voltage mode switching converters, both need to perform more complex loop compensation during normal operation, which not only increases the design difficulty of the converter, but also increases the minimum operating current of the converter, and because the gain bandwidth of the loop is small, the transient response performance is generally slower than that of the hysteretic switching converter.

In the field of wireless bluetooth, because the load required by the application environment is actually small, the switching power supply converter of the chip works in a Pulse Frequency Modulation (PFM) mode most of the time, and the traditional design method with high efficiency in the heavy current field is not very practical in the field. In addition, because the bluetooth true wireless is in a standby state or a periodic wake-up state for a large part of time, especially in the periodic wake-up state, the working current of the whole system is low, and most power supply products on the market at present have low efficiency in the environment. Therefore, the design of the buck switching converter with extremely low self current consumption and a simple control loop has very important significance.

The hysteresis type switching converter has a simple loop control structure, and the transient response is optimal in three modes. Due to the simple structure and composition, the system can realize the minimum modules to work under the condition of small system load, thereby improving the working efficiency as much as possible. The fast transient response enables the method to have great advantages in application environments with large transient load jump, and particularly has inherent advantages in power supply system architecture selection of microcontrollers, FPGA chips, CPU chips and the like.

The current buck hysteresis switching converter technology is mainly divided into the following:

1. a conventional buck hysteresis switch converter loop structure is shown in fig. 1, and the loop compares VOUT ' voltage with a hysteresis window composed of VREF ' + and VREF ', and an obtained PWM signal switches upper and lower switching tubes (PSW ', NSW ') of the loop. In practical applications, since the typical hysteresis mode control directly controls the output voltage ripple to ensure the normal operation of the system, an electrolytic capacitor with a relatively large Equivalent Series Resistance (ESR) is often required, or an external Resistor (RC) is connected in series to the output capacitor branch to generate the ripple. This not only increases the design cost, but also causes a certain power consumption to lower the conversion efficiency.

2. Because the traditional buck hysteresis type switching converter has various problems, a negative feedback control loop (FB') is usually designed to compensate a system in the design, as shown in fig. 2, the design method has a good effect in a PWM continuous mode, but the design difficulty is increased on a certain basis, and the lowest working current is increased.

3. In order to better improve the loop performance, the characteristics of the loop are better improved by utilizing a phase-locked loop (PLL) modulation technology on the basis of the second structure.

4. And the working state of the system in the third mode is digitally controlled by using the ADC and the digital control mode, so that the performance of the chip is better improved.

5. A Constant On Time (COT) control technique is utilized.

In the above schemes, the purpose of improving the efficiency under the heavy load state is achieved, the loop design is complex, and the application environments of the wireless true bluetooth headset and the like cannot be met. In addition, in the constant on-time control technology, due to the defect of a loop, a slope pulse modulation structure needs to be added to compensate a system, and certain complexity exists in design.

In the prior art, in order to reduce the power consumption of the buck hysteresis type switching converter, a zero current switching module is configured in a switching control module, and when it is detected that the output current of the switching converter is smaller than a bias signal (which may be regarded as a current zero crossing), the zero current switching module outputs a control signal to turn off a lower switching tube, thereby achieving the purpose of reducing the power consumption. To achieve zero-crossing detection of the output current of the switching converter, the zero-current switching module is usually required to be in an active detection state all the time, which also increases the power consumption of the switching converter.

Therefore, it is an urgent technical problem to provide a relatively simple circuit structure to reduce the power consumption of the buck hysteresis switching converter and improve the conversion efficiency.

Disclosure of Invention

In view of the above situation, a primary object of the present invention is to provide a buck-type hysteretic switching converter and a control method thereof, which can reduce the complexity of the circuit structure and reduce the power consumption of the buck-type hysteretic switching converter, thereby improving the conversion efficiency.

To achieve the above object, according to a first aspect, an embodiment of the present invention discloses a buck hysteresis switching converter, including: the upper and lower switch tubes are used for receiving input voltage and converting the input voltage into output voltage through the on and off of the switch to provide the output voltage for a load; the switch control module is used for controlling the on and off of the upper and lower switch tubes; the switch control module has a low power consumption mode; the switching converter further comprises: the low-power-consumption control logic module is connected with the switch control module and is used for detecting the working state of the switch control module and outputting a control signal corresponding to the working state based on the working state so as to control the working power consumption mode of the switch control module; when the low-power-consumption control logic module detects that the working state meets the low-power-consumption condition, the low-power-consumption control logic module outputs low-power-consumption control logic to the switch control module so that the switch control module works in a low-power-consumption mode.

Optionally, the switch control module comprises: a comparator circuit formed by a comparator and a switch control logic circuit; the comparison circuit generates a switch control signal according to a reference signal and a ramp signal to control the on and off of the upper and lower switch tubes, wherein the ramp signal is generated based on a feedback signal of the switch converter; and after the low-power consumption control logic module detects that the switch control module turns off the upper switch tube, the low-power consumption control logic module outputs a first control signal representing a low-power consumption mode to the comparator so as to enable the comparator to be in the low-power consumption mode.

Optionally, the comparator comprises: the input control network is used for receiving a first reference signal and a second reference signal, and the amplitude of the first reference signal is greater than that of the second reference signal; the fully differential amplifier is connected with the input control network and is used for receiving a ramp signal; the output logic is connected with the fully differential amplifier and used for outputting a comparison result of the ramp signal, the first reference signal and the second reference signal so that the switch control logic circuit controls the on and off of the upper and lower switch tubes based on the comparison result; and a bias unit connected with the fully differential amplifier, wherein the bias unit provides a smaller bias current to the fully differential amplifier in response to a first control signal indicating low power consumption relative to a non-low power consumption mode so as to enable the comparator to be in a low power consumption mode.

Optionally, the biasing unit comprises: the control electrode of the first bias switch is used for receiving a first control signal, and the second electrode of the first bias switch is used for being connected to a power supply through a current-limiting resistor; at least one first transistor, the first pole of which is connected to the first pole of the first bias switch, and the second pole is used for grounding; at least one second transistor, the first pole of which is connected to the second pole of the first bias switch, and the second pole is used for grounding; at least one third transistor, the first pole of which is connected to the fully differential amplifier and the second pole is used for grounding; the control electrode of the first transistor, the control electrode of the second transistor and the control electrode of the third transistor are connected to a power supply through a current limiting resistor; the first bias switch is closed in response to a first control signal indicating a low power consumption mode, and turns on a first pole and a second pole of the first bias switch to cause the third transistor to provide a smaller bias current to the fully differential amplifier.

Optionally, the first bias switch turns off the first and second poles of the first bias switch in response to the first control signal indicating the fast response mode to cause the third transistor to provide a larger bias current to the fully differential amplifier to place the comparator in the fast flip mode of operation.

Optionally, when the first control signal is at a high level, the fast response mode is indicated; when the first control signal is at a low level, a low power consumption mode is indicated.

Optionally, the number of the first transistors is N times that of the second transistors, where N is an integer greater than or equal to 2.

Optionally, the biasing unit comprises: the bias resistor, its one end is connected to power or ground through the current-limiting resistor; a control electrode of the second bias switch is used for receiving the first control signal, and a first electrode and a second electrode of the second bias switch are respectively connected to one end and the other end of the bias resistor; the second bias switch is turned off in response to the first control signal indicating the low power consumption mode so that the bias resistor and the current limiting resistor supply a smaller bias current to the fully differential amplifier; the second bias switch is closed in response to the first control signal indicating a fast response mode to cause the current limiting resistor to provide a greater bias current to the fully differential amplifier to place the comparator in a fast flip mode of operation.

Optionally, the resistance of the bias resistor is N times that of the current limiting resistor, where N is an integer greater than or equal to 2.

Optionally, the switch control module comprises: the zero current switch module is connected to the output end of the switch converter, and outputs a zero-crossing signal after detecting that the current output by the switch converter is lower than a preset value so as to disconnect a lower switch tube; the zero current switch module is also connected with the low power consumption control logic module; and after the zero-current switch module outputs the zero-crossing signal, the low-power-consumption control logic module outputs a second control signal for closing the zero-current switch module to the zero-current switch module so as to close the zero-current switch module.

Optionally, the low power consumption control logic module further includes: the counter is used for counting the zero-crossing signals output by the zero-current switch module; and when the zero-crossing signal reaches the counting capacity of the counter, the low-power-consumption control logic module outputs a second control signal for closing the zero-current switch module to the zero-current switch module after receiving each zero-crossing signal.

Optionally, the counter is cleared after the zero-crossing signal is not detected in a period before the lower switch tube is turned on.

Optionally, the method further comprises: the timer is connected with the low-power consumption control logic module, and is shared by the switch converter and a peripheral circuit of the switch converter; and within the preset time, counting that the number of times that the upper switch tube or the lower switch tube is triggered is less than the preset number of times, and outputting a second control signal representing the closing of the zero-current switch module to the zero-current switch module by the low-power-consumption control logic module so as to close the zero-current switch module.

Optionally, the low power consumption control logic module outputs a second control signal indicating to turn on the zero current switch module to the zero current switch module after the switch control module is turned on the upper switch tube, so that the zero current switch module is in a working state of detecting the output current of the switch converter.

Optionally, the method further comprises: a reference generating circuit for generating a first reference signal and a second reference signal, the first reference signal having a magnitude greater than a magnitude of the second reference signal; the digital control logic module is connected with the reference generating circuit; the digital control logic module is used for outputting an amplitude control signal to the reference generating circuit so as to adjust the amplitude of the first reference signal and/or the amplitude of the second reference signal.

According to a second aspect, an embodiment of the invention discloses an integrated circuit chip, comprising: the switching converter disclosed in any of the above first aspects.

According to a third aspect, an embodiment of the present invention discloses a control method for a buck-type hysteretic switching converter, where the switching converter includes: the upper and lower switch tubes are used for receiving input voltage and converting the input voltage into output voltage through the on and off of the switch to provide the output voltage for a load; the switch control module is used for controlling the on and off of the upper and lower switch tubes; the low-power consumption control logic module is connected with the switch control module; the control method comprises the following steps: s11, the switch control module controls the on-off state of an upper switch tube and a lower switch tube, and during the period, the low-power-consumption control logic module outputs a control signal corresponding to the working state based on the detected working state of the switch control module so as to control the working power consumption mode of the switch control module; and S12, when the low-power-consumption control logic module detects that the working state meets the low-power-consumption condition, the low-power-consumption control logic module outputs low-power-consumption control logic to the switch control module so that the switch control module works in a low-power-consumption mode.

Optionally, step S11 includes: s101, a switch control module conducts an upper switch tube to provide power for a load end of a switch converter, and during the period, a low-power consumption control logic module provides a first control signal (HCOMP _ CTL) representing a quick response mode for a comparator of the switch control module, so that the comparator works in a quick turnover working mode; s103, when the amplitude of the output voltage of the switch converter reaches the amplitude of the first reference signal, the switch control module turns off the upper switch tube and turns on the lower switch tube; step S12 includes: and S105, after the upper switching tube is turned off, the low-power-consumption control logic module outputs a first control signal (HCOMP _ CTL) representing a low-power-consumption mode to the comparator so as to enable the comparator to be in the low-power-consumption mode, wherein in the low-power-consumption mode, the overturning speed of the comparator is smaller than that in the rapid overturning working mode.

Optionally, step S101 further includes: the low-power consumption control logic module outputs a second control signal for starting the zero-current switch module to the zero-current switch module of the switch control module so as to enable the zero-current switch module to be in a working state for detecting the output current of the switch converter; further included after step S103 is: and S104, during the conduction period of the lower switching tube, when the zero current switch module detects that the zero-crossing signal is output, the low-power-consumption control logic module outputs a second control signal for closing the zero current switch module to the zero current switch module so as to close the zero current switch module.

Optionally, step S104 includes: s1041, counting the times of outputting a zero-crossing signal detected while a lower switching tube is in a conducting period; and S1042. when the frequency reaches the preset frequency, the low-power consumption control logic module outputs a second control signal for closing the zero-current switch module to the zero-current switch module so as to close the zero-current switch module.

According to the buck hysteresis type switch converter, the control circuit and the control method thereof disclosed by the embodiment of the invention, the control circuit is configured for the switch converter, the control circuit comprises a low-power consumption control logic module, and the low-power consumption control logic module is used for detecting the working state of the switch control module; and when the switch control module meets the low-power consumption condition, the low-power consumption control logic module outputs low-power consumption control logic to the switch control module so that the switch control module works in the low-power consumption module. Compared with the prior art that the switch control module is always in a normal working mode, the scheme disclosed by the embodiment of the invention can realize the switching of the working state of the switch control module through the low-power-consumption control logic module, namely, the switch control module can work in the low-power-consumption mode after meeting the low-power-consumption condition, so that the power consumption of the buck hysteresis type switch converter is reduced by adopting a relatively simple circuit structure.

In addition, for the comparator circuit, when the comparator is required to be rapidly turned over, a larger bias current is provided for a fully differential amplifier of the comparator, so that the comparator is in a rapidly turned over working mode, and the conversion efficiency of the switching converter is improved.

As an alternative, different numbers of transistors are configured in the bias unit, and different bias currents are provided in different modes through cooperation of the transistors, so that on one hand, accuracy of bias current provision can be improved, and on the other hand, the transistors are basically in a symmetrical structure, which is beneficial to layout.

As an optional scheme, the bias unit is implemented by the second bias switch and the bias resistor, the circuit structure is simplified, and different bias currents can be provided in two states, so that on one hand, power consumption can be reduced, and on the other hand, conversion efficiency can be improved when the switch converter works normally.

As an optional scheme, the zero current switch module is further connected to the low power consumption control logic module, and after the zero current switch module outputs the zero-crossing signal, the low power consumption control logic module outputs a second control signal indicating that the zero current switch module is turned off to the zero current switch module, so as to turn off the zero current switch module.

As an optional scheme, the zero-crossing signal output by the zero-current switch module is counted by a counter, when the zero-crossing signal reaches the counting capacity of the counter, it can be determined that the current load is relatively stable, and after the counter is full, the second control signal for turning off the zero-current switch module is triggered, so that the power consumption can be reduced, and the stability of the system operation can be improved.

As an optional scheme, the low power consumption control logic module counts the number of times that the upper switch tube or the lower switch tube is triggered through a timer, and generally, a conventional circuit system is provided with a processor or a clock circuit, so that the scheme of the application can multiplex the existing circuit resources to count the number of times that the upper switch tube or the lower switch tube is triggered, and then, the power consumption can be reduced without an additional complex circuit structure, and the stability of system operation is improved.

Other advantages of the present invention will be described in the detailed description, and those skilled in the art will understand the technical features and technical solutions presented in the description.

Drawings

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. In the figure:

fig. 1 is a schematic circuit diagram of a buck hysteresis switching converter in the prior art;

FIG. 2 is a schematic diagram of another buck hysteretic switching converter circuit of the prior art;

fig. 3 is a schematic circuit diagram of a buck hysteresis switch converter according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of an operating timing sequence of a buck hysteretic switching converter according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a frame structure of a comparator according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a bias unit according to an embodiment of the present invention;

fig. 7a and 7b are schematic structural diagrams of another bias unit according to an embodiment of the disclosure, wherein,

FIG. 7a shows one connection and FIG. 7b shows another connection;

fig. 8a is a flowchart of a control method of a buck hysteresis switch converter according to an embodiment of the present invention;

FIG. 8b is a flowchart illustrating another exemplary method for controlling a buck hysteretic switching converter in accordance with the present disclosure;

fig. 9 is a flowchart of a module for turning off a zero-current switch according to an embodiment of the present invention.

Detailed Description

In order to reduce the complexity of the circuit structure and simultaneously reduce the power consumption of the buck hysteresis switch converter and improve the conversion efficiency, this embodiment discloses a control circuit of the buck hysteresis switch converter, please refer to fig. 3, which is a schematic diagram of the circuit structure of the buck hysteresis switch converter disclosed in this embodiment, and the switch converter includes: upper and lower switch tube 1, switch control module 2 and low-power consumption control logic module 3, wherein:

the upper and lower switch tubes 1 are used for receiving an input voltage VIN and converting the input voltage VIN into an output voltage VOUT to be supplied to a load through the on and off of the switches (see R0 and C0 in fig. 3). In a specific embodiment, the input voltage (i.e., the power supply voltage) VIN may be filtered by a filter capacitor Cin. The upper and lower switch tubes 1 include an upper switch tube PSW and a lower switch tube NSW, and referring to fig. 3, the upper and lower switch tubes 1 are connected to the output end of the converter through an inductor L0, that is, one end of an inductor L0 is connected to the upper and lower switch tubes 1, and the other end of an inductor L0 is the output end of the converter; in a specific implementation, a voltage VSW at one end of the inductor L0 is equal to the power supply voltage VIN when the upper switch tube PSW is turned on, is equal to the ground voltage when the lower switch tube NSW is turned on, and is equal to the VOUT voltage when neither the upper switch tube PSW nor the lower switch tube NSW is turned off.

The switch control module 2 is used for controlling the on and off of the upper and lower switch tubes 1, in this embodiment, the switch control module 2 includes a comparison circuit formed by a comparator and a switch control logic; the comparison circuit generates a switch control signal according to a reference signal and a ramp signal to control the on and off of the upper and lower switch tubes 1, wherein the ramp signal is generated by the ramp circuit generator 5 based on a feedback signal of the switch converter, specifically, see the following description. In a specific embodiment, the switch control module 2 further includes a zero current switch module 4, and the zero current switch module 4 turns off the lower switching tube NSW after detecting a zero crossing of the current flowing through the inductor L0.

The general working flow of the switching converter is as follows: under the PWM signal output by the comparator, the switch control logic turns on the upper switching tube PSW, and at this time, the input voltage VIN supplies power to the output terminal through the inductor L0 through the turned on upper switching tube PSW; when the voltage output by the output end reaches the first reference signal VREF +, the upper switch tube PSW is disconnected and the lower switch tube NSW is switched on, and the voltage of the output end is reduced at the moment; when the voltage output by the output end reaches a certain threshold value, a new switching period can be started. In the above process, the comparator is always in the fast-flipping operating mode, and the zero-current switch module is always in the detection state, so that the power consumption of the whole switch control module 2 is large.

Referring to fig. 3, in the buck hysteresis type switching converter disclosed in this embodiment, the switch control module 2 has a low power consumption mode; the low-power-consumption control logic module 3 is connected with the switch control module 2, and the low-power-consumption control logic module 3 is used for detecting the working state of the switch control module 2 and outputting a control signal corresponding to the working state based on the working state so as to control the working power consumption mode of the switch control module 2; when the low power consumption control logic module 3 detects that the switch control module 2 meets the low power consumption condition, the low power consumption control logic module 3 outputs the low power consumption control logic to the switch control module 2, so that the switch control module 2 works in the low power consumption mode. In one embodiment, the low power consumption control logic module 3 may control the comparator to operate in the low power consumption mode; in another embodiment, the low power consumption control logic module 3 may also turn off the zero current switch 4; of course, the low power consumption control logic module 3 may also turn off the zero current switch 4 while controlling the comparator to operate in the low power consumption mode.

In this embodiment, the low power consumption control logic module 3 is used to detect the operating state of the switch control module 2, and after the low power consumption condition is met, the low power consumption control logic module 3 outputs the low power consumption control logic to the switch control module 2 (such as a comparator and a zero current switch), so that the switch control module 2 can operate in the low power consumption mode, and the power consumption of the switch converter is reduced.

Referring to fig. 3 and fig. 4, wherein fig. 4 is an operation timing diagram of a buck hysteresis switching converter disclosed in this embodiment, in an embodiment, the switch control module 2 includes: a comparator circuit formed by a comparator and a switch control logic circuit; the comparison circuit generates a switch control signal according to the reference signals (VREF + and VREF-) and a ramp signal Vramp to control the on and off of the upper and lower switch tubes (PSW, NSW), wherein the ramp signal Vramp is generated based on the feedback signals (VSW and VOUT) of the switch converter. Specifically, after detecting that the switch control module 2 turns off the upper switch tube PSW, the low power consumption control logic module 3 outputs a first control signal HCOMP _ CTL indicating a low power consumption mode to the comparator, so that the comparator is in the low power consumption mode. Referring to fig. 4, when the control signal PON output to the upper switching tube PSW by the switch control module 2 is at a high level, the first control signal HCOMP _ CTL output to the comparator by the low-power control logic module 3 is at a high level, so that the comparator operates in a fast-flipping operating mode, thereby improving the operating efficiency of the comparator; when the control signal PON output to the upper switching tube PSW by the switch control module 2 is changed from a high level to a low level, the upper switching tube PSW is turned off, and at this time, the first control signal HCOMP _ CTL output to the comparator by the low power consumption control logic module 3 is changed from a high level to a low level, so that the comparator operates in the low power consumption mode. In this embodiment, the low power consumption mode of the comparator means that the flip speed of the comparator is lower than that of the normal operating mode in the mode of the comparator, so that the power consumption of the comparator is reduced, and the purpose of reducing the power consumption is achieved.

In an embodiment, please refer to fig. 5, which is a schematic diagram of a frame structure of a comparator disclosed in this embodiment, the comparator includes: an input control network, a fully differential amplifier, output logic, and a bias unit, wherein:

the input control network is used for receiving a first reference signal VREF + and a second reference signal VREF-, and the amplitude of the first reference signal VREF + is larger than that of the second reference signal VREF-; the fully differential amplifier is connected with the input control network and is used for receiving a ramp signal VRAMP; the output logic is connected with the fully differential amplifier and is used for outputting a comparison result HCOMP of the ramp signal VRAMP and the first reference signal VREF + and the second reference signal VREF-, so that the switch control logic circuit controls the on-off of the upper switch tube and the lower switch tube based on the comparison result HCOMP; a bias unit is connected to the fully differential amplifier, the bias unit providing a smaller bias current to the fully differential amplifier relative to a non-low power mode in response to a first control signal HCOMP _ CTL indicating low power consumption to place the comparator in the low power mode.

In each of the above modules, the input control network, the fully differential amplifier and the output logic can be implemented by using the conventional comparator module. In this embodiment, the bias unit provides two bias currents to the fully differential amplifier, that is, when the upper switching tube PSW is turned on and the comparator needs to operate quickly (i.e., in a non-low power consumption mode), the bias unit provides a larger bias current to the fully differential amplifier, so that the comparator is in a quick-flip operating state, and the operating efficiency is improved; when the upper switching tube PSW is turned off, the bias unit provides a smaller bias current to the fully differential amplifier to place the comparator in a low power consumption mode, thereby reducing the power consumption of the comparator.

It should be noted that in the implementation, the bias unit provides a smaller bias current to the fully differential amplifier, which does not mean that the comparator does not perform the "comparison" operation any more, but is in a relatively "slow" operation mode. Specifically, the flip speed of the comparator is related to the magnitude of the bias current, and those skilled in the art can determine the magnitude of the bias current in the two modes based on actual needs according to the above description.

In the embodiment, the comparator circuit is operated in a low power consumption mode after meeting the low power consumption condition, so that the power consumption is reduced; when the comparator is required to be rapidly turned over, a larger bias current is provided for a fully differential amplifier of the comparator, so that the comparator is in a rapidly-turned working mode, and the conversion efficiency of the switching converter is improved.

In an embodiment, please refer to fig. 6, which is a schematic structural diagram of a bias unit disclosed in the present embodiment, the bias unit includes: a first bias switch S1, at least one first transistor MN0, at least one second transistor MN1, and at least one third transistor MN2, wherein,

a control pole (e.g., a gate) of the first bias switch S1 is configured to receive the first control signal HCOMP _ CTL, and a second pole (e.g., a drain) of the first bias switch S1 is configured to be connected to the power source VCC through a current limiting resistor Rs; a first pole (e.g., source) of the at least one first transistor MN0 is connected to a first pole (e.g., source) of the first bias switch S1, and a second pole (e.g., drain) is used for ground VSS; a first pole (e.g., source) of the at least one second transistor MN1 is connected to a second pole (e.g., drain) of the first bias switch S1, the second pole (e.g., drain) for ground VSS; a first pole (e.g., source) of the at least one third transistor MN2 is connected to the fully differential amplifier, and a second pole (e.g., drain) is used for ground VSS; a control electrode (e.g., gate) of the first transistor MN0, a control electrode (e.g., gate) of the second transistor MN1, and a control electrode (e.g., gate) of the third transistor MN2 are connected to the power supply VCC through a current limiting resistor Rs.

In the present embodiment, the first bias switch S1 turns on the first and second poles of the first bias switch S1 in response to the first control signal HCOMP _ CTL indicating the low power consumption mode being closed, so that the third transistor MN2 supplies a smaller bias current to the fully differential amplifier; the first bias switch S1 turns off the first and second poles of the first bias switch S1 in response to the first control signal HCOMP _ CTL indicating the fast response mode to make the third transistor MN2 supply a larger bias current to the fully differential amplifier to make the comparator in the fast flip operation mode. In a specific embodiment, when the first control signal HCOMP _ CTL is high, it indicates a fast response mode; when the first control signal HCOMP _ CTL is low, it indicates a low power consumption mode.

In the embodiment, the number of the first transistors MN0 is N times that of the second transistors MN1, where N is an integer greater than or equal to 2.

It should be noted that each transistor in the first transistor MN0 is a same type of transistor, and the connection manner is the same, that is, each transistor in the first transistor MN0 has a first electrode connected in parallel, a second electrode connected in parallel, and a control electrode connected in parallel; for the second transistor MN1 and the third transistor MN2, the same type of transistors are also used and connected in parallel, which is not described herein again.

In this embodiment, different numbers of transistors are configured in the bias unit, and different bias currents are provided in different modes through cooperation of the transistors, so that on one hand, the accuracy of providing the bias currents can be improved, and on the other hand, the transistors are basically in a symmetrical structure, which is beneficial to layout.

It should be noted that the level controlling the first bias switch S1 to be turned on or off is related to the transistor type of the first bias switch S1, and in other embodiments, the relationship between the high and low levels of the first control signal HCOMP _ CTL may be replaced.

To facilitate understanding by those skilled in the art, the control process of the comparator will be described exemplarily, please refer to fig. 4 and 6:

when the first control signal HCOMP _ CTL is at a high level, the first bias switch S1 is in an off state, and at this time, the bias current IBN of the comparator is a large value, so that the current consumption of the whole module is large, and the response is fast; after the upper switch PSW is turned off (PON is low in fig. 4), the first control signal HCOMP _ CTL is low, the first bias switch S1 is closed, and the comparator consumes lower current until the next time the upper switch PSW is turned on.

When the first control signal HCOMP _ CTL is high, the input current bias is:

wherein, I_bFor input current bias, VCC is the power supply, V_thIs the threshold voltage of the first bias switch S1, Rs is the resistance of the current limiting resistor; the magnitude of the bias current IBN to the fully differential amplifier is:

wherein, I_{comp_bias}C is the number of third transistors MN2, b is the number of second transistors MN1, in order to reflect the bias current IBN to the fully differential amplifier;

when the first control signal HCOMP _ CTL is low, the magnitude of the bias current IBN reflected to the fully differential amplifier is:

wherein, a is the number of the first transistors MN0, and comparing the formula (1) and the formula (2), it can be known that if the on time of the upper switch PON is very small in the whole cycle, the effect of low power consumption can be achieved.

In the states of HCOMP _ CTRL ═ 0 and HCOMP _ CTRL ═ 1, the current consumed by the comparator has the following proportional relationship:

if a is 9 times b, the current can be reduced to 0.1 times of normal under the condition that HCOMP _ CTRL is 0, and the effect of saving power is achieved.

In another embodiment, please refer to fig. 7a and fig. 7b, which are schematic structural diagrams of another bias unit disclosed in this embodiment, the bias unit includes: a bias resistor R0, a second bias switch S2, and a current limiting resistor Rs, wherein:

one end of the bias resistor R0 is connected to the power VCC or the ground VSS through the current limiting resistor Rs; a control electrode (e.g., a gate) of the second bias switch S2 is configured to receive the first control signal HCOMP _ CTL, and a first electrode (e.g., a source) and a second electrode (e.g., a drain) of the second bias switch S2 are respectively connected to one end and the other end of the bias resistor R0; the second bias switch S2 is turned off in response to the first control signal HCOMP _ CTL indicating the low power consumption mode, so that the bias resistor R0 and the current limiting resistor Rs provide a smaller bias current to the fully differential amplifier; the second bias switch S2 is closed in response to the first control signal HCOMP _ CTL indicating the fast response mode to cause the current limiting resistor Rs to provide a greater bias current to the fully differential amplifier to place the comparator in the fast flipping mode of operation.

In an embodiment, the resistance of the bias resistor R0 is N times larger than the current limiting resistor Rs, where N is an integer greater than or equal to 2.

In this embodiment, the bias unit is implemented by the second bias switch and the bias resistor, the circuit structure is simplified, and different bias currents can be provided in two states, so that on one hand, power consumption can be reduced, and on the other hand, conversion efficiency can be improved when the switch converter works normally.

To facilitate understanding by those skilled in the art, referring to fig. 4, fig. 7a and fig. 7b, when HCOMP _ CTRL is at a high level, the second bias switch S2 is in a closed state, and the current bias of the comparator is a large value, so that the overall current consumption of the module is large and the response is fast; after the upper switching tube PSW is turned off (PON is low), HCOMP _ CTRL is low, the second bias switch S2 is turned off, and the comparator consumes lower current until the next time the upper switching tube PSW is turned on.

In this embodiment, when HCOMP _ CTRL is at a high level, since the second bias switch S2 is in a closed state and the bias resistor R0 is in a short-circuited state, the bias current IBN reflected to the differential amplifier is:

wherein Vth is a threshold of the second bias switch S2;

when HCOMP _ CTRL is low, the second bias switch S2 is open, and the bias resistor R0 is connected in series with the current limiting resistor Rs, so that the bias current IBN reflected to the differential amplifier is:

comparing the formulas (3) and (4), it can be known that if the ratio of the on time of the upper tube PON in the whole period is very small, the effect of low power consumption can be achieved. If R0 is 9 times Rs, the current can be reduced to 0.1 times normal when HCOMP _ CTRL is 0, and the power saving effect is achieved. Wherein, the resistor R0 is an accessible resistor, and Rs is a normally accessible resistor.

In addition, in the states of HCOMP _ CTRL ═ 0 and HCOMP _ CTRL ═ 1, the comparator is capable of operating and flipping, but at different flipping speeds. Fig. 7a and 7b show two different implementations.

In order to implement zero-crossing detection of the output current of the switching converter, please refer to fig. 3, the switching control module 2 further includes a zero-current switching module 4, the zero-current switching module 4 is connected to the output end of the switching converter, and the zero-current switching module 4 outputs a zero-crossing signal ZCD after detecting that the output current of the switching converter is lower than a preset value, so as to disconnect the lower switching tube NSW.

In this embodiment, the zero current switch module 4 is further connected to the low power consumption control logic module 3; after the zero-crossing signal ZCD is output from the zero-current switch module 4, the low-power control logic module 3 outputs a second control signal ZCD _ CTL indicating that the zero-current switch module 4 is turned off to the zero-current switch module 4, so as to turn off the zero-current switch module 4.

After the switch control module 2 turns on the upper switching tube PSW, the low power consumption control logic module 3 outputs a second control signal ZCD _ CTL indicating to turn on the zero current switching module 4 to the zero current switching module 4, so that the zero current switching module 4 is in a working state of detecting the output current of the switch converter.

Referring to fig. 3 and 4, when the signal PON outputted by the switch control logic changes from a high level to a low level to turn off the upper switch tube PSW, the signal NON outputted by the switch control logic changes to a high level to turn on the lower switch tube NSW, at this time, the output voltage VOUT of the switch converter continuously decreases, and the current IL flowing through the inductor L0 also continuously decreases, so that the second control signal ZCD _ CTL outputted by the low power consumption control logic module 3 to the zero current switch module 4 is at a high level at this time, thereby making the zero current switch module 4 in the detection state. When the zero current switch module 4 detects that the current IL flowing through the inductor L0 crosses zero (i.e., is lower than the preset value), it outputs a pulse signal to the switch control logic to turn off the lower switch tube NSW, and at this time, the second control signal ZCD _ CTL output to the zero current switch module 4 changes from high level to low level, i.e., turns off the zero current switch module 4 until the next cycle.

In this embodiment, for zero current switch module is in opening, detection state always, the scheme of this application can reduce zero current switch module's consumption.

In order to trigger a state transition each time a current zero crossing is detected, in an alternative embodiment, the low power consumption control logic module 3 further comprises: the counter is used for counting the zero-crossing signal ZCD output by the zero current switch module 4; when the zero-crossing signal ZCD reaches the counting capacity of the counter, the low power consumption control logic module 3 outputs a second control signal ZCD _ CTL indicating that the zero-current switch module 4 is turned off to the zero-current switch module 4 every time the zero-crossing signal ZCD is received.

In an alternative embodiment, the counter is cleared after the zero-crossing signal ZCD is not detected in a period before the lower switching tube NSW is turned on.

In this embodiment, the zero-crossing signal output by the zero-current switch module is counted by the counter, when the zero-crossing signal reaches the counting capacity of the counter, it can be determined that the current load is relatively stable, and after the counter is full, the second control signal for turning off the zero-current switch module is triggered, so that the power consumption can be reduced, and the stability of the system operation can be improved.

In order to reuse the existing resources, in an alternative embodiment, the multiplexing may also be implemented by a timer, and the timer is connected to the low power consumption control logic module 3; the timer is shared by the switching converter and the peripheral circuit of the switching converter, that is, the timer of the present embodiment may be implemented by a processor or a clock circuit of the peripheral circuit. In this embodiment, after counting that the number of times that the upper switching tube PSW or the lower switching tube NSW is triggered is less than the preset number of times within the preset time duration, the low power consumption control logic module 3 outputs the second control signal ZCD _ CTL indicating that the zero current switching module 4 is turned off to the zero current switching module 4, so as to turn off the zero current switching module 4.

In this embodiment, the low power consumption control logic module counts the number of times that the upper switch tube or the lower switch tube is triggered through the timer, and generally speaking, conventional circuit systems are all provided with a processor or a clock circuit, so the scheme of the application can multiplex the existing circuit resources to count the number of times that the upper switch tube or the lower switch tube is triggered, and then, the stability of system operation can be improved while power consumption is reduced without an additional complex circuit structure.

Referring to fig. 3, the buck hysteresis switching converter disclosed in this embodiment further includes: a reference generation circuit 6 and a digital control logic module 7, wherein:

the reference generating circuit 6 is used for generating a first reference signal VREF + and a second reference signal VREF-, wherein the amplitude of the first reference signal VREF + is larger than that of the second reference signal VREF-; the digital control logic module 7 is connected with the reference generating circuit 6; the digital control logic module 7 is used for outputting an amplitude control signal to the reference generating circuit so as to adjust the amplitude of the first reference signal VREF + and/or the amplitude of the second reference signal VREF-.

In this embodiment, the ramp signal Vramp, the first reference signal VREF + and the second reference signal VREF-may be determined by the ramp circuit generator 5, the reference generating circuit 6 and the digital control logic module 7, specifically:

in a first step, the ramp coefficients of the rising and falling edges of the ramp generator are determined. In the buck hysteresis type switch converter structure, when the system works in a continuous mode, the conducting time of the upper tube and the conducting time of the lower tube are related to the duty ratio:

wherein Tnon is the conduction time of the lower switching tube NSW, Tpon is the conduction time of the upper switching tube PSW, and Period is the working Period of the switching converter in the continuous mode; since the comparator window is determined, its slope is inversely proportional to its on-time, respectively, and the rising edge and falling edge slope coefficients of the ramp circuit generator need to be determined according to this relationship in the design process.

Second, the Vramp voltage waveform in discontinuous mode is determined. In this embodiment, the ramp circuit generator 5 can generate the ramp signal Vramp according to the voltages VSW and VOUT at two ends of the inductor L0, referring to fig. 4, when the upper switch tube is turned on, the voltage of VSW is equal to the power voltage, when the lower tube is turned on, the voltage of VSW is equal to the ground voltage, and when neither the upper tube nor the lower tube is turned on, the voltage of VSW is equal to the voltage of VOUT.

And thirdly, determining the ripple magnitude of the output voltage VOUT. In the present invention, if there is a large variation range of the input voltage and a large variation range of the output voltage, the slope of Vramp will also have a large variation. Because a certain time delay exists in the re-triggering process of the comparator, VREF related compensation as shown in FIG. 3 is added in the ramp generating circuit in the design process, and a constant and small ripple factor can be ensured on a certain basis. The first reference signal VREF + and the second reference signal VREF-are the upper and lower limits of the hysteresis comparator, respectively. In addition, in this embodiment, the digital control logic module 7 is added to adjust the output voltage VOUT of the chip in a wide range.

The embodiment also discloses an integrated circuit chip comprising the buck hysteresis type switching converter disclosed in any embodiment.

Fig. 8a is a flowchart of a control method for a buck hysteresis switch converter disclosed in this embodiment, where the control method for the buck hysteresis switch converter includes:

and S11, the switch control module 2 controls the on and off states of the upper and lower switch tubes 1. Meanwhile, the low power consumption control logic module 3 outputs a control signal corresponding to the working state based on the detected working state of the switch control module 2 to control the working power consumption mode of the switch control module 2; and

and S12, enabling the switch control module 2 to work in a low power consumption mode by the low power consumption control logic module 3. When the low power consumption control logic module 3 detects that the working state meets the low power consumption condition, the low power consumption control logic module 3 outputs the low power consumption control logic to the switch control module 2, so that the switch control module 2 works in the low power consumption mode.

Specifically, referring to fig. 8b, which is a flowchart of a specific control method of the buck hysteresis switching converter disclosed in this embodiment, in the specific control process, step S11 includes step S101 and step S103, and step S12 includes step S105, where:

and S101, switching on the upper switching tube PSW, and enabling the comparator to work in a fast turnover working mode. The switch control module 2 turns on the upper switch tube PSW to supply power to the load end of the switch converter, and during the period, the low power consumption control logic module 3 provides the first control signal HCOMP _ CTL indicating the fast response mode to the comparator of the switch control module 2, so that the comparator operates in the fast-flipping operating mode.

In an alternative embodiment, step S101 further includes: the low power consumption control logic module 3 outputs a second control signal ZCD _ CTL indicating to turn on the zero current switch module 4 to the zero current switch module 4 of the switch control module 2, so that the zero current switch module 4 is in a working state of detecting an output current of the switch converter.

And S103, turning off the upper switching tube PSW and turning on the lower switching tube NSW. When the amplitude of the output voltage of the switching converter reaches the amplitude of the first reference signal VREF +, the switching control module 2 turns off the upper switching tube PSW and turns on the lower switching tube NSW.

And S105, enabling the comparator to be in a low power consumption mode by the low power consumption control logic module. After the upper switching tube PSW is turned off, the low power consumption control logic module 3 outputs a first control signal HCOMP _ CTL indicating a low power consumption mode to the comparator, so that the comparator is in the low power consumption mode, wherein in the low power consumption mode, the flipping speed of the comparator is smaller than that in the fast flipping mode.

In an alternative embodiment, after step S103, the method further includes:

and S104, closing the zero-current switch module 4. During the period that the lower switch NSW is turned on, after the zero current switch module 4 detects that the zero-crossing signal ZCD is output, the low power consumption control logic module 3 outputs a second control signal ZCD _ CTL indicating that the zero current switch module 4 is turned off to the zero current switch module 4, so as to turn off the zero current switch module 4.

In an alternative embodiment, please refer to fig. 9, which is a flowchart of a module for turning off a zero current switch disclosed in this embodiment, step S104 includes:

s1041, counting the times of outputting a zero-crossing signal ZCD detected during the conduction period of a lower switch NSW;

step s1042. when the number of times reaches the preset number of times, the low power consumption control logic module 3 outputs a second control signal ZCD _ CTL indicating to close the zero current switch module 4 to the zero current switch module 4, so as to close the zero current switch module 4.

According to the buck hysteresis type switch converter, the control circuit and the control method thereof disclosed by the embodiment, the control circuit is configured for the switch converter, the control circuit comprises a low-power-consumption control logic module, and the low-power-consumption control logic module is used for detecting the working state of the switch control module; and when the switch control module meets the low-power consumption condition, the low-power consumption control logic module outputs low-power consumption control logic to the switch control module so that the switch control module works in the low-power consumption module. Compared with the prior art that the switch control module is always in a normal working mode, the scheme disclosed by the embodiment of the invention can realize the switching of the working state of the switch control module through the low-power-consumption control logic module, namely, the switch control module can work in the low-power-consumption mode after meeting the low-power-consumption condition, so that the power consumption of the buck hysteresis type switch converter is reduced by adopting a relatively simple circuit structure.

It will be appreciated by those skilled in the art that the above-described preferred embodiments may be freely combined, superimposed, without conflict.

It will be understood that the embodiments described above are illustrative only and not restrictive, and that various obvious and equivalent modifications and substitutions for details described herein may be made by those skilled in the art without departing from the basic principles of the invention.

Claims

1. A buck hysteretic switching converter comprising:

the upper and lower switch tubes are used for receiving input voltage and converting the input voltage into output voltage through the on and off of the switch to provide the output voltage for a load; and

the switch control module (2) is used for controlling the on and off of the upper and lower switching tubes;

characterized in that the switch control module (2) has a low power consumption mode;

the switching converter further includes:

the low-power-consumption control logic module (3) is connected with the switch control module (2), and the low-power-consumption control logic module (3) is used for detecting the working state of the switch control module (2) and outputting a control signal corresponding to the working state based on the working state so as to control the working power consumption mode of the switch control module (2);

when the low-power-consumption control logic module (3) detects that the working state meets a low-power-consumption condition, the low-power-consumption control logic module (3) outputs a low-power-consumption control logic to the switch control module (2) so that the switch control module (2) works in a low-power-consumption mode;

the switch control module includes:

the zero current switch module (4) is connected to the output end of the switch converter, and the zero current switch module (4) outputs a zero-crossing signal (ZCD) after detecting that the current output by the switch converter is lower than a preset value so as to disconnect a lower switch tube (NSW);

the zero current switch module (4) is also connected with the low power consumption control logic module (3); the low power consumption control logic module (3) outputs a second control signal (ZCD _ CTL) representing the closing of the zero current switch module (4) to the zero current switch module (4) after the zero current switch module (4) outputs the zero crossing signal (ZCD) to close the zero current switch module (4).

2. Switching converter according to claim 1, characterized in that said switching control module (2) comprises:

a comparator circuit formed by a comparator and a switch control logic circuit; the comparison circuit generates a switch control signal according to a reference signal and a ramp signal to control the on and off of the upper and lower switching tubes, wherein the ramp signal is generated based on a feedback signal of the switching converter;

after the low-power consumption control logic module (3) detects that the switch control module (2) turns off the upper switch tube (PSW), a first control signal (HCOMP _ CTL) representing a low-power consumption mode is output to the comparator, so that the comparator is in the low-power consumption mode.

3. The switching converter of claim 2, wherein the comparator comprises:

-an input control network for receiving a first reference signal (VREF +) and a second reference signal (VREF-), the first reference signal (VREF +) having a magnitude being larger than the magnitude of the second reference signal (VREF-);

a fully differential amplifier connected to the input control network, the fully differential amplifier for receiving the ramp signal (VRAMP);

output logic, connected to the fully differential amplifier, for outputting a comparison result (HCOMP) of the ramp signal (VRAMP) with the first reference signal (VREF +), the second reference signal (VREF-), so that the switch control logic circuit controls the on and off of the upper and lower switch tubes based on the comparison result (HCOMP); and

a biasing unit connected to the fully differential amplifier, the biasing unit providing a smaller bias current to the fully differential amplifier relative to a non-low power mode in response to a first control signal (HCOMP _ CTL) indicating low power consumption to place the comparator in a low power mode.

4. The switching converter according to claim 3, wherein the bias unit comprises:

a first bias switch (S1) having a gate for receiving the first control signal (HCOMP _ CTL), a second gate of the first bias switch (S1) for connecting to a power supply through a current limiting resistor (Rs);

at least one first transistor (MN 0) having a first pole connected to a first pole of the first bias switch (S1) and a second pole for ground;

at least one second transistor (MN 1) having a first pole connected to a second pole of the first bias switch (S1), the second pole being for ground;

at least one third transistor (MN 2) having a first pole connected to the fully differential amplifier and a second pole for grounding;

a control electrode of the first transistor (MN 0), a control electrode of the second transistor (MN 1), and a control electrode of the third transistor (MN 2) are connected to a power supply through the current limiting resistor (Rs);

the first bias switch (S1) closes in response to a first control signal (HCOMP _ CTL) indicating a low power consumption mode, turning on a first pole and a second pole of the first bias switch (S1) to cause the third transistor (MN 2) to provide the smaller bias current to the fully differential amplifier.

5. The switching converter according to claim 4, wherein the first bias switch (S1) is responsive to a first control signal (HCOMP _ CTL) indicating a fast response mode to open the first and second poles of the first bias switch (S1) to cause the third transistor (MN 2) to provide a larger bias current to the fully differential amplifier to place the comparator in a fast flipping mode of operation.

6. A switching converter according to claim 5, characterized in that said first control signal (HCOMP _ CTL), when high, indicates a fast response mode; the first control signal (HCOMP _ CTL), when low, indicates a low power mode.

7. Switching converter according to any of claims 4-6, characterized in that the number of said first transistors (MN 0) is N times larger than the number of said second transistors (MN 1), wherein N is an integer equal to or larger than 2.

8. The switching converter according to claim 3, wherein the bias unit comprises:

a bias resistor (R0) having one end connected to a power supply or ground through a current limiting resistor (Rs);

a second bias switch (S2) having a control pole for receiving the first control signal (HCOMP _ CTL), the first pole and the second pole of the second bias switch (S2) being connected to one end and the other end of the bias resistor (R0), respectively;

the second bias switch (S2) is opened in response to a first control signal (HCOMP _ CTL) indicating a low power consumption mode to cause the bias resistor (R0) and the current limiting resistor (Rs) to provide the smaller bias current to the fully differential amplifier;

the second bias switch (S2) is closed in response to a first control signal (HCOMP _ CTL) indicating a fast response mode to cause the current limiting resistor (Rs) to provide a greater bias current to the fully differential amplifier to place the comparator in a fast slewing mode of operation.

9. The switching converter according to claim 8, characterized in that said biasing resistor (R0) has a value N times greater than said current limiting resistor (Rs), where N is an integer greater than or equal to 2.

10. Switching converter according to claim 1, characterized in that said low power consumption control logic module (3) further comprises:

a counter for counting the zero crossing signal (ZCD) output by the zero current switching module (4);

and when the zero-crossing signal (ZCD) reaches the counting capacity of the counter, the low-power consumption control logic module (3) outputs a second control signal (ZCD _ CTL) which represents that the zero-current switch module (4) is closed to the zero-current switch module (4) after receiving one zero-crossing signal (ZCD).

11. The switching converter according to claim 10, characterized in that said counter is cleared after said zero crossing signal (ZCD) is not detected in the period before said down switch (NSW) is turned on.

12. The switching converter of claim 1, further comprising:

the timer is connected with the low-power consumption control logic module (3);

within a preset time length, after counting that the number of times that an upper switching tube (PSW) or a lower switching tube (NSW) is triggered is smaller than a preset number of times, the low-power-consumption control logic module (3) outputs a second control signal (ZCD _ CTL) representing the closing of the zero-current switching module (4) to the zero-current switching module (4) so as to close the zero-current switching module (4).

13. The switching converter according to claim 12, wherein the timer is shared by the switching converter and peripheral circuitry of the switching converter.

14. The switching converter according to claim 1, characterized in that said low power consumption control logic module (3) outputs a second control signal (ZCD _ CTL) to said zero current switching module (4) after said switching control module (2) turns on the upper switching transistor (PSW), indicating to turn on said zero current switching module (4), so as to put said zero current switching module (4) in an operating state for detecting the output current of said switching converter.

15. A switching converter according to any one of claims 1-3, further comprising:

a reference generating circuit for generating a first reference signal (VREF +) and a second reference signal (VREF-), the magnitude of the first reference signal (VREF +) being larger than the magnitude of the second reference signal (VREF-); and

the digital control logic module is connected with the reference generating circuit;

the digital control logic module is used for outputting an amplitude control signal to the reference generating circuit so as to adjust the amplitude of the first reference signal (VREF +) and/or the amplitude of the second reference signal (VREF-).

16. An integrated circuit chip, comprising:

a switching converter as claimed in any one of claims 1 to 15.

17. A buck hysteretic switching converter control method, the switching converter comprising:

the low-power consumption control logic module (3) is connected with the switch control module (2);

the control method is characterized by comprising the following steps:

step S11, the switch control module (2) controls the on and off states of the upper and lower switch tubes, and during the period, the low power consumption control logic module (3) outputs a control signal corresponding to the working state based on the detected working state of the switch control module (2) so as to control the working power consumption mode of the switch control module (2); wherein:

the low-power consumption control logic module (3) outputs a second control signal (ZCD _ CTL) which represents that the zero-current switch module (4) is started to a zero-current switch module (4) of the switch control module (2), so that the zero-current switch module (4) is in a working state of detecting the output current of the switch converter;

during the conduction period of a lower switching tube (NSW), after the zero current switching module (4) detects that a zero-crossing signal (ZCD) is output, the low-power consumption control logic module (3) outputs a second control signal (ZCD _ CTL) which represents the closing of the zero current switching module (4) to the zero current switching module (4) so as to close the zero current switching module (4);

and step S12, when the low-power consumption control logic module (3) detects that the working state meets the low-power consumption condition, the low-power consumption control logic module (3) outputs low-power consumption control logic to the switch control module (2) so as to enable the switch control module (2) to work in a low-power consumption mode.

18. The control method according to claim 17,

the step S11 includes:

step S101, the switch control module (2) conducts an upper switch tube (PSW) to provide power for a load end of the switch converter, and during the period, the low-power consumption control logic module (3) provides a first control signal (HCOMP _ CTL) representing a quick response mode for a comparator of the switch control module (2) so that the comparator works in a quick turnover working mode; and

step S103, when the amplitude of the output voltage of the switch converter reaches the amplitude of a first reference signal (VREF +), the switch control module (2) turns off the upper switch tube (PSW) and turns on the lower switch tube (NSW);

the step S12 includes:

and S105, after the upper switching tube (PSW) is turned off, the low-power-consumption control logic module (3) outputs a first control signal (HCOMP _ CTL) representing a low-power-consumption mode to the comparator so as to enable the comparator to be in the low-power-consumption mode, wherein in the low-power-consumption mode, the overturning speed of the comparator is smaller than that in the fast overturning working mode.

19. The control method according to claim 18,

the step S101 further includes:

step S102, the low-power consumption control logic module (3) outputs a second control signal (ZCD _ CTL) which represents that the zero-current switch module (4) is started to the zero-current switch module (4) of the switch control module (2), so that the zero-current switch module (4) is in a working state of detecting the output current of the switch converter;

after the step S103, the method further includes:

step S104, during the conduction period of the lower switching tube (NSW), after the zero current switch module (4) detects that a zero-crossing signal (ZCD) is output, the low-power-consumption control logic module (3) outputs a second control signal (ZCD _ CTL) which represents that the zero current switch module (4) is closed to the zero current switch module (4) so as to close the zero current switch module (4).

20. The control method according to claim 19, wherein the step S104 includes:

step S1041, counting the times of outputting a zero-crossing signal (ZCD) detected at the same time during the conduction period of the lower switching tube (NSW); and

step S1042, when the frequency reaches a preset frequency, the low power consumption control logic module (3) outputs a second control signal (ZCD _ CTL) representing closing of the zero current switch module (4) to the zero current switch module (4) so as to close the zero current switch module (4).