CN1114258C - Digital switch converter with quantization error compensation function - Google Patents

Abstract

A digital switching converter with a quantization error compensation function, including a power switch, an attenuator, an A/D converter, an adder, a regulator, a switch controller, a driver, and a first adder, a second adder, a quantizer and The compensation controller of the delayer, which stores and accumulates the mantissa of the quantization error of the switching controller in time, and compensates the switching pulse time value accordingly, so as to significantly improve the digital pulse control accuracy of the switching converter .

Description

Digital Switching Converter with Quantization Error Compensation

The present invention relates to digital switching converters.

All kinds of power electronic power supplies (including AC/DC power supplies, DC/DC power supplies, inverters, etc.) are widely used in various electrification equipment, and the switching converter is the core part of this kind of power supply. The switching converter is also the core component of the switching power amplifier. The switching converter realizes the control of electric energy by frequently switching the power semiconductor switches in it. In recent years, with the development of digital signal processing chips (DSP), microprocessor chips (MPU), microcomputers (MCU), and programmable logic gate arrays (PLA), digital control technology has begun to be used in switching converters. application. Commonly used control methods include pulse width modulation (PWM) control, fixed pulse width variable frequency control, fixed frequency phase shift control, etc., among which PWM control is more typical. Take the current digital switching converter as an example (see Figure 1), which usually includes a power switch, an attenuator, an A/D converter that can convert an analog signal into a digital signal, and a regulator (usually proportional-integral-differential Regulator), switch controller (usually with counter) and drive module. The output voltage (current) is reduced by the attenuator and converted into digital quantity by A/D. The output signal of the A/D is compared with the given quantity V _f to generate an error signal through the adder, which is processed by the regulator. The output signal of the regulator is sent to the switch controller, thereby generating the switch pulse regulation signal. Finally, the power switch of the converter is controlled by the drive module, thereby affecting the output V _o of the converter. In the above process, the signal sent to the switch controller is a digital quantity, and the resolution of the output switch pulse width depends on the control word length of the switch controller. Usually, the output resolution of the regulator can reach more than 16Bits, which is much higher than the word length of the counter in the switch controller. Quantization errors in pulse width appear as truncation errors in the controller output signal. Take the 20kHz switching converter with PWM control mode as an example, its cycle is 50μs, in order to realize the PWM resolution of 16Bits, the clock frequency of the counter must reach 2 ¹⁶ × 20 × 10 ³ kHz = 1.31GHz. However, the DSP and MPU currently used in switching converters generally have a clock frequency of only about 5-50 MHz, which is far from the above-mentioned requirements. When the switching frequency of PWM increases, the converter will have higher requirements on the clock frequency of the digital controller. For example, if a DSP with a clock frequency of 20MHz is used, when the switching frequency is 50kHz, the resolution of its PWM is only 400 (the length of the control word is lower than 9Bits). This has a big gap for the realization of high-precision control requirements. What's more serious is that the quantization error will lead to the limit cycle oscillation in the control process of the switching converter, and the limit cycle oscillation will amplify the output error of the switching converter many times.

The object of the present invention is to improve the digitized pulse control precision of the digitized switching converter, and to propose a digitized switching converter with quantization error compensation function.

The digital switching converter with quantization error compensation function of the present invention is formed by adding a compensation controller to the existing digital switching converter, and it includes a power switch, an attenuator, an A/D converter, an adder, and a regulator A switch controller and a driver are characterized in that a compensation controller is connected between the regulator and the switch controller, and the compensation controller includes a first adder, a second adder, a quantizer and a time delay device, and the first adder One of the input terminals is connected to the output terminal of the regulator, and the other input terminal is connected to the output terminal of the delayer. The output of the first adder is respectively input to the quantizer and the second adder. The output of the quantizer is divided into two paths, one of which is The input is to the second adder, the other is connected to the input end of the switch controller, and the output end of the second adder is connected to the input end of the delayer.

The function of the delayer in the compensation controller is to delay the data by one switching cycle, and its function can be realized by the program beat or by hardware. The quantizer is a memory with the same control word length as the switch controller.

Further illustrate the present invention below in conjunction with accompanying drawing.

Figure 1 is a block diagram of an existing digital switching converter;

Fig. 2 is a block diagram of the present invention;

Fig. 3 is a kind of concrete example of the present invention;

FIG. 4 is a schematic diagram of a DSP chip used in the example of FIG. 3 .

Referring to Fig. 1, the digitized switching converter with quantization error compensation function of the present invention comprises power switch 1, attenuator 2, A/D converter 3, adder 4, regulator 5, switch controller 6 and driver 7, its The feature is that a compensation controller 8 is connected between the regulator 5 and the switch controller 6, and the compensation controller includes a first adder 9, a second adder 10, a quantizer 11 and a delayer 12, and the first adder 9 One input terminal of one input terminal is connected to the output terminal of the regulator 5, and the other input terminal is connected to the output terminal of the delayer 12, and the output of the first adder is respectively input to the quantizer 11 and the second adder 10, and the output of the quantizer 11 is divided into Two paths, one of which is input to the second adder 10 , the other is connected to the input end of the switch controller 6 , and the output end of the second adder 10 is connected to the input end of the delayer 12 .

Usually, switch controller 6, compensation controller 8, regulator 5, adder 4 and A/D converter 3 can be specially integrated on one chip, or integrated digital signal processing such as DSP or MPU or MCU or PLA can be used chip.

When working, the output voltage (current) is reduced by the attenuator 2, and converted into a digital quantity by the A/D converter 3, and the output signal of the A/D is compared with the given value V _f to generate an error signal by the adder 4, which is adjusted Processed by the converter 5 and sent to the compensation controller 8, the switching time of the switching converter is quantized and compensated, and the switching pulse signal after the quantization error compensation is controlled by the switch controller 6 and the driver 7 to control the power switch 1 of the converter, thereby affecting the conversion tor output V _o .

Let x _n be the input quantity of the compensation controller, y _n be the output quantity, and the subscript of each variable is the time series label. y _n ^* is the truncated part of the data sent to the switch controller, and y _n-1 ^* is y _n ^* delayed by one switching cycle, and the meaning of y _n-1 ^* is to keep the truncated part continuously. At the same time, the compensation controller output y _n is the integer part of the sum of the regulator output and the last truncated error. The function of the compensation controller is:

1) When the input quantity does not contain the mantissa, y _n-1 ^* will remain unchanged;

2) When the mantissa of the input quantity is added to the last mantissa and no carry is generated, the mantissa is integrated in each switching cycle;

3) When a carry is generated when the mantissa of the input quantity is added to the last mantissa, the integer part is taken out to compensate the truncation error of the controller, and the remaining mantissa is used for the next calculation.

4) The mantissa y _n ^* is determined by the difference between the input quantity and the output quantity of the quantizer, and is related to the selected quantization function. The above expression can be supplemented by the following formula: ${\mathrm{the\; y}}_{\mathrm{no}}^{*}=x_{\mathrm{no}}+{\mathrm{the\; y}}_{\mathrm{no}-1}^{*}-{\mathrm{the\; y}}_{\mathrm{no}}---\left(1\right)$ ${\mathrm{the\; y}}_{\mathrm{no}}=\mathrm{Trunc}(x_{\mathrm{no}}+{\mathrm{the\; y}}_{\mathrm{no}-1}^{*})---\left(2\right)$ In Formula 2, Trunc is a quantization function, and its function is to take the integer part of the variable. The quantization error at the switching moment of the switching converter can be compensated by using the compensation controller.

The rounding of the quantization function can usually adopt the method of discarding the mantissa (that is, rounding off the mantissa) or rounding or rounding up (that is, as long as there is a mantissa, one digit is carried).

Fig. 3 is a specific example of the present invention, the top of Fig. 3 is a step-up switching power converter with capacitors C _i , C ₀ , inductance L, diode D, power semiconductor main switch S, and the bottom of Fig. 3 is a digital pulse control Part, the driver in this example uses a gate drive module, which is connected to the gate of the power semiconductor main switch S, the switch controller uses a digital control PWM module, the regulator is a PID unit, and the attenuator connected to the output terminal of the power converter is divided by a resistor. A/D is a digital-to-analog converter, V _f is a given voltage value in digital form, the structure of the compensation controller is the same as that in Figure 2, and the quantizer is a memory with the same control word length as the switch controller , the delayer is implemented with a program beat or by hardware. Among them, the digital control PWM, compensation controller, PID, adder and A/D can also adopt the DSP integrated digital signal processing chip whose model is TMS320F240 as shown in Fig. 4 . The DSP chip has a built-in CPU (central processing unit), timer, and hardware parts such as A/D and PWM. The modules communicate through the bus. The program and constants are placed in the read-only memory (ROM), and the variables are placed in the random access memory (RAM). )middle. Among them, PID and compensation functions are realized by using DSP programs. The digital pulse control device can control the output voltage through the switching control of the main switch of the power semiconductor. Tests have shown that by adopting the present invention, the ring-limited voltage fluctuations caused by quantization errors can be successfully reduced by 90%.

The present invention stores and accumulates the mantissa of the time quantization error of the digitized pulse control unit in the switching converter, and compensates the pulse time value accordingly, thereby effectively reducing the control error caused by digital quantization and significantly improving Control accuracy of switching converters. The present invention can be used for pulse time variable (such as pulse width) adjustment in switching converters, and can increase the effective control word length of the pulse controller and refine and advance the resolution without increasing the clock frequency. It is helpful to realize digital precision control on various switching converters, which is particularly important for the development and promotion of digital control technology for high-frequency switching power converters.

The invention is not limited to compensating the truncation error of PWM, but also can compensate the pulse quantization error of switching converters adopting other control modes. For example, the present invention can be used to compensate the truncation error of the pulse control for the digitally controlled switching converters with variable frequency fixed pulse width control, fixed frequency phase shift control and other schemes.

Claims (4)

1. the digital switch converter that has quantization error compensation function, comprise power switch [1], attenuator [2], A/D converter [3], adder [4], adjuster [5], on-off controller [6] and driver [7], it is characterized in that between adjuster [5] and on-off controller [6], inserting compensating controller [8], this compensating controller comprises first adder [9], second adder [10], quantizer [11] and delayer [12], the output of an input termination adjuster [5] of first adder [9], the output of another input termination delayer [12], the output of first adder inputs to quantizer [11] and second adder [10] respectively, the output of quantizer [11] divides two the tunnel, the one road inputs to second adder [10], another road links to each other with the input of on-off controller [6], the input of the output termination delayer [12] of second adder [10].

2. by the described digital switch converter of claim 1, it is characterized in that said quantizer [11] is one and has and on-off controller control word appearance memory together.

3. by the described digital switch converter of claim 1, it is characterized in that said on-off controller [6], compensating controller [8], adjuster [5], adder [4] and A/D converter [3] are digital signal processing chip or microprocessor chip or microcomputer or programmable gate array integrated digital signal processing chip.

4. by the described digital switch converter of claim 1, it is characterized in that said on-off controller [6], compensating controller [8], adjuster [5], adder [4] and A/D converter [3] are integrated on a slice chip specially.

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