CN111403406A - Three-dimensional memory and preparation method thereof - Google Patents

Abstract

The invention provides a three-dimensional memory and a preparation method thereof, belonging to the field of semiconductor memory design and manufacture. The first block storage area of the three-dimensional memory includes a first core area and a first stepped area, the second storage area includes a second core area and a second stepped area, and the first and second core areas are adjacently arranged along the first direction and Isolated from each other, the first and second step areas are adjacently arranged along the second direction and isolated from each other, the first step area has a first step widening portion extending to the inside of the second core area along the first direction; the second step area has The second step widening portion reversely extends to the inside of the first core region along the first direction. Through the novel gate line gap (GLS) design of the present invention, the step area of the block storage area has a step widening portion extending into the core area of the adjacent block storage area, thereby increasing the width of the step area of a single block storage area, which is beneficial to partitioning The increase in the number can reduce the design difficulty of the memory architecture.

Description

Three-dimensional memory and preparation method thereof

technical field

The invention belongs to the field of semiconductor memory design and manufacture, and in particular relates to a three-dimensional memory and a preparation method thereof.

Background technique

With the development of planar flash memory, the production process of semiconductors has made great progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limits, existing development technology limits, and storage electron density limits. In this context, in order to solve the difficulties encountered by planar flash memory and pursue lower production costs per unit of memory cells, three-dimensional memory structures emerge as the times require. The three-dimensional memory structure can enable each memory die in a memory device to have a larger number of memory chips. memory unit.

In non-volatile memory, such as NAND memory, one way to increase memory density is through the use of vertical memory arrays, namely 3D NAND memory, and CTF (Charge Trap Flash, charge trap flash) type 3D NAND memory is currently more advanced , and memory technology with great development potential.

3D NAND memory typically includes one or more plane memory areas. On both sides of the chip storage area, there are usually symmetrical connection areas for extracting the gate. Typically, the connection region has a Stair-Step shape. The slice storage area and the connection area are usually divided into multiple blocks to form multiple block storage areas (Block).

In the existing 3D NAND memory, the area occupied by the step area of each block storage area is only the area of one block storage area, which limits the architectural design of the step area.

SUMMARY OF THE INVENTION

In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a three-dimensional memory and a preparation method thereof, which are used to solve the problem of the stepped area of the block storage area in the prior art.

In order to achieve the above object and other related objects, the present invention provides a three-dimensional memory, the three-dimensional memory includes a first storage area and a second storage area, the first storage area includes a first core area and a storage area located in the A first step area in the middle of the first core area, the second storage area includes a second core area and a second step area in the middle of the second core area, the first core area and the second core area are along the The first step area and the second step area are adjacently arranged along the second direction and isolated from each other, wherein the first step area has a length extending to A first step widening part inside the second core area, the first step widening part is isolated from the second core area by a first gate line gap; the second step area has a reverse extension along the first direction to the second step widening portion inside the first core region, the second step widening portion is isolated from the first core region by a second gate line gap.

Optionally, the first core area includes a first sub-core area and a second sub-core area located at both ends of the first step area and the second step area, the first sub-core area and the first step area. The second core area includes a third sub-core area and a fourth sub-core area located at both ends of the first step area and the second step area, and the fourth core area is connected to the second step area ; The first block storage area also includes a first bridge wall on one side of the first step area and the second step area, and the first bridge wall connects the first step area and the first sub-core. area and a second sub-core area, the second block storage area further includes a second bridge wall on the other side of the first step area and the second step area, the second bridge wall is connected to the second step region, the third sub-core region and the fourth sub-core region.

Optionally, the first sub-core region and the third sub-core region are isolated by a first inter-block gate line gap, the first inter-block gate line gap is connected to the first gate line gap, and the The second sub-core region is isolated from the fourth sub-core region by a second inter-block gate line gap, and the second inter-block gate line gap is connected to the second gate line gap.

Optionally, the first step widening portion extends to be adjacent to the second bridging wall, and is isolated from the second bridging wall by a third grid line gap, and the first grid line gap is connected to the second bridging wall. Three gate line gaps are connected to each other, the second step widening portion extends to be adjacent to the first bridge wall, and is isolated from the first bridge wall by a fourth gate line gap, and the fourth gate line gap is connected to the first bridge wall. the second gate line gap connection.

Optionally, both the first core area and the second core area include a plurality of finger storage areas, and the finger storage areas are isolated by inter-finger gate line gaps.

Optionally, the width of the first step widening portion extending to the inside of the second core region is an integer multiple of the width of the finger storage region.

Optionally, the widths of the first bridging wall and the second bridging wall are between the width of 0.5 finger storage areas and the width of 2 finger storage areas.

Optionally, the steps of the first step area and the second step area are sequentially lowered from the corresponding core area toward the isolation belt between the first step area and the second step area, and are cut off at the isolation belt. .

Optionally, the first direction and the second direction are perpendicular to each other.

Optionally, the first core region and the second core region include a stack structure and an array of channel storage structures penetrating the stack structure, the channel storage structures including a channel hole penetrating the stack structure and a channel hole located in the stack structure. The memory film and the channel layer in the channel hole are described.

The present invention also provides a method for preparing a three-dimensional memory, including the steps of: providing a substrate, forming a stack structure on the substrate; forming a first storage area and a second storage area in the stack structure, so that the The first block storage area includes a first core area and a first step area located in the middle of the first core area, and the second storage area includes a second core area and a second step area located in the middle of the second core area. the first core area and the second core area are adjacently arranged along the first direction and isolated from each other, the first step area and the second step area are adjacently arranged along the second direction and isolated from each other, Wherein, the first step region has a first step widening portion extending into the second core region along a first direction, and the first step widening portion is isolated from the second core region by a first gate line gap ; The second step area has a second step widening portion extending reversely to the inside of the first core area along the first direction, and the second step widening portion is connected to the first core area through a second gate line gap isolation.

Optionally, the first core area includes a first sub-core area and a second sub-core area located at both ends of the first step area and the second step area, the first sub-core area and the first step area. The second core area includes a third sub-core area and a fourth sub-core area located at both ends of the first step area and the second step area, and the fourth core area is connected to the second step area ; The first block storage area also includes a first bridge wall on one side of the first step area and the second step area, and the first bridge wall connects the first step area and the first sub-core. area and a second sub-core area, the second block storage area further includes a second bridge wall on the other side of the first step area and the second step area, the second bridge wall is connected to the second step region, the third sub-core region and the fourth sub-core region.

Optionally, the first sub-core region and the third sub-core region are isolated by a first inter-block gate line gap, the first inter-block gate line gap is connected to the first gate line gap, and the The second sub-core region is isolated from the fourth sub-core region by a second inter-block gate line gap, and the second inter-block gate line gap is connected to the second gate line gap.

Optionally, the first step widening portion extends to be adjacent to the second bridging wall, and is isolated from the second bridging wall by a third grid line gap, and the first grid line gap is connected to the second bridging wall. Three gate line gaps are connected to each other, the second step widening portion extends to be adjacent to the first bridge wall, and is isolated from the first bridge wall by a fourth gate line gap, and the fourth gate line gap is connected to the first bridge wall. the second gate line gap connection.

Optionally, both the first core area and the second core area include a plurality of finger storage areas, and the finger storage areas are isolated by inter-finger gate line gaps and extend to the second core area inside the second core area. The width of a step widening portion is an integer multiple of the width of the finger storage area, the width of the first bridge wall is between 0.5 of the width of the finger storage area to 2 of the width of the finger storage area, The width of the second bridging wall is between 0.5 of the width of the finger storage areas to the width of 2 of the finger storage areas.

Optionally, the steps of the first step area and the second step area are sequentially lowered from the corresponding core area toward the isolation belt between the first step area and the second step area, and are cut off at the isolation belt. .

As mentioned above, the three-dimensional memory of the present invention and the preparation method thereof have the following beneficial effects:

In the present invention, through the novel gate line gap (GLS) design, the step area of the block storage area has a step widening portion extending into the core area of the adjacent block storage area, so that a single block storage area can be located in the first direction (for example, the Y direction). ) increase in the width of the upper step area.

The increase of the width of the step area in the Y direction of the single block storage area of the present invention is beneficial to the increase of the number of partitions, and at the same time, the bridge wall can have a larger design width, and the increase in the width of the bridge wall can reduce the area of the step contact area, thereby reducing the cost of The design difficulty of the architecture of the invented three-dimensional memory.

Description of drawings

FIG. 1 is a schematic diagram showing the layout structure of a three-dimensional memory.

FIG. 2 is a schematic structural diagram of the three-dimensional memory of the present invention.

FIG. 3 is a schematic diagram of a layout structure of the three-dimensional memory of the present invention.

FIG. 4 is a schematic diagram showing another layout structure of the three-dimensional memory of the present invention.

Component label description

11, 12 memory areas

111 Core Area

112 Step area

113 Bridge Wall

21 The first memory area

211 The first sub-core area

212 Second sub-core area

213 First Step Area

214 First step widening

215 First Bridge Wall

22 Second memory area

221 The third sub-core area

222 Fourth sub-core area

223 Second Step Area

224 Second step widening

225 Second Bridge Wall

241 first grid line gap

242 The first inter-block gate line gap

243 The second inter-block gate line gap

244 Third gate line gap

245 Second gate line gap

246 Fourth gate line gap

247 Separator

248 Finger Grid Gap

23 refers to the memory area

31 Third memory area

32 Fourth memory area

41, 42, 43, 44 memory blocks

414 First step widening

424 Second step widening

Detailed ways

The embodiments of the present invention are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

When describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional views showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the protection scope of the present invention. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in the actual production.

For convenience of description, spatially relative terms such as "below," "below," "below," "below," "above," "on," etc. may be used herein to describe an element shown in the figures or The relationship of a feature to other components or features. It will be understood that these spatially relative terms are intended to encompass other directions of the device in use or operation than those depicted in the figures. In addition, when a layer is referred to as being 'between' two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, descriptions of structures where a first feature is "on" a second feature can include embodiments in which the first and second features are formed in direct contact, and can also include further features formed over the first and second features. Embodiments between the second features such that the first and second features may not be in direct contact.

It should be noted that the diagrams provided in this embodiment are only to illustrate the basic concept of the present invention in a schematic way, so the diagrams only show the components related to the present invention rather than the number, shape and the number of components in the actual implementation. For dimension drawing, the type, quantity and proportion of each component can be changed at will in actual implementation, and the component layout may also be more complicated.

FIG. 1 is a schematic structural diagram of a three-dimensional memory (3D NAND), which includes a plurality of block storage areas 11 and 12 , each block storage area includes a core area 111 and a step area 112 , and the step area 112 is arranged in the core area 111 In the middle, the step area 112 cooperates with a bridging wall 113, so that the step area 112 is connected to the core areas 111 at both ends at the same time. In the three-dimensional memory, the area occupied by the step area of each block storage area is only the area of one block storage area. For example, one block storage area of the three-dimensional memory includes 3 finger storage areas, and the width of the step area can only be designed to be no larger than The width of 3 finger storage areas, and the bridge wall also needs to occupy a certain width of finger storage area, so that the width of the step area in the Y direction is limited, which limits the architectural design of the steps and the design of the bridge wall.

The present invention provides a three-dimensional memory. Through the novel gate line gap (GLS) design, the step area of the block storage area has a step widening portion extending into the core area of the adjacent block storage area, so that a single block storage area can be placed in the first An increase in the width of the stepped region in the direction (eg, the Y direction).

As shown in FIG. 2 to FIG. 3 , this embodiment provides a three-dimensional memory. The three-dimensional memory includes a plurality of block storage areas (Block). For example, as shown in FIG. 3 , the three-dimensional memory may include a first block storage area. 21. The second block storage area 22 The third block storage area and the fourth block storage area, of course, in the actual device design, the three-dimensional memory may include more block storage areas, such as 8 block storage areas, 16 block storage area or more, not limited to the examples in the figures herein.

For a more convenient and detailed description, in this embodiment, two block storage areas are taken as an example. As shown in FIG. 2, the three-dimensional memory includes a first block storage area 21 and a second block storage area 22, so The first block storage area 21 and the second block storage area 22 are isolated from each other. The first block storage area 21 includes a first core area and a first step area 213 located in the middle of the first core area. The second storage area includes a second core area and a second step area 223 located in the middle of the second core area. The first core area and the second core area are arranged adjacent to each other along the first direction and isolated from each other. The first step area 213 and the second step area 223 are adjacently arranged along the second direction and isolated from each other, wherein the first step area 213 has a first step area extending to the inside of the second core area along the first direction. A step widening portion 214, the first step widening portion 214 is isolated from the second core region by the first gate line gap 241; the second step region 223 has a reverse extending in the first direction to the first The second step widening part 224 inside the core area, the second step widening part 224 is isolated from the first core area by the second gate line gap 245 , specifically, as shown in FIG. 2 , the first step widening part 224 is The portion 214 and the second step widening portion 224 are arranged in a staggered manner. The first direction and the second direction are preferably perpendicular to each other. For example, as shown in FIG. 2 , the first direction may be selected as the Y direction, and the second direction may be selected as the X direction.

As shown in FIG. 2 , the first core region includes a first sub-core region 211 and a second sub-core region 212 located at both ends of the first stepped region 213 and the second stepped region 223 . The first sub-core region 211 is connected to the first step area 213, the second core area includes a third sub-core area 221 and a fourth sub-core area 222 located at both ends of the first step area 213 and the second step area 223, the The fourth core area is connected to the second step area 223 ; the first block storage area 21 further includes a first bridge wall 215 located on one side of the first step area 213 and the second step area 223 . A bridging wall 215 connects the first step area 213 , the first sub-core area 211 and the second sub-core area 212 , and the second block storage area 22 further includes the first step area 213 and the second sub-core area 212 . A second bridging wall 225 on the other side of the step area 223 connects the second step area 223 , the third sub-core area 221 and the fourth sub-core area 222 . Of course, the layout of the first sub-core area 211 , the second sub-core area 212 , the third sub-core area 221 , the fourth sub-core area 222 , the first step area 213 and the second step area 223 is not limited to the above For example, for example, the first step area 213 may also be connected to the second sub-core area 212, and connected to the first sub-core area 211 through a first bridge wall 215. Similarly, the first sub-core area 211 The second step area 223 can also be connected to the third sub-core area 221, and is connected to the third sub-core area through the second bridge wall 225. For the structure, please refer to the third storage area and the fourth block in FIG. 3 . The structure of the storage area is shown.

As shown in FIG. 2 , the first sub-core region 211 and the third sub-core region 221 are isolated by a first inter-block gate line gap 242 , and the first inter-block gate line gap 242 is separated from the first gate line The line gaps 241 are connected, and the second sub-core region 212 and the fourth sub-core region 222 are isolated by a second inter-block gate line gap 243, which is connected to the second gate line Gap 245 is connected.

As shown in FIG. 2 , the first step widening portion 214 extends to be adjacent to the second bridging wall 225 and is isolated from the second bridging wall 225 by a third grid line gap 244 . The first grid The line gap 241 is connected to the third gate line gap 244 , the second step widening portion 224 extends to be adjacent to the first bridging wall 215 , and is connected to the first bridging wall through the fourth gate line gap 246 215 is isolated, and the fourth gate line gap 246 is connected to the second gate line gap 245 .

As shown in FIG. 2 , the steps of the first step area 213 and the second step area 223 are sequentially lowered from the corresponding core area to the isolation belt 247 between the first step area 213 and the second step area 223 , And after the isolation belt 247 is cut off, for example, after the steps are lowered in sequence, at the isolation belt 247, the substrate surface under the stepped area is exposed, and the first stepped area 213 and the second stepped area 223 are realized. cut off isolation.

Specifically, as shown in FIG. 2 , for the first block storage area 21 and the second block storage area 22 , the main isolation structure in this embodiment includes a first inter-block gate line gap 242 , a first The gate line gap 241, the third gate line gap 244, the isolation strip 247, the fourth gate line gap 246, the second gate line gap 245 and the second inter-block gate line gap 243, wherein the first inter-block gate line gap 242 extends along the second direction (X direction) for isolating the first sub-core region 211 and the third sub-core region 221, the first gate line gap 241 extends along the first direction (Y direction), For isolating the first step region 213 and the third sub-core region 221, the third gate line gap 244 extends along the second direction (X direction) for isolating the first step region 213 and all The second bridging wall 225, the isolation strip 247 extends along the first direction (Y direction) for isolating the first step area 213 and the second step area 223, the fourth gate line gap 246 is along the The second direction (X direction) extends for isolating the second step region 223 from the first bridging wall 215, and the second gate line gap 245 extends along the first direction (Y direction) for isolating all the The second step region 223 and the second sub-core region 212, and the inter-block gate line gap extends along the second direction (X direction) for isolating the second sub-core region 212 and the fourth sub-core region 212 Sub-core area 222. In the present invention, through the novel gate line gap (GLS) design, the step area of the block storage area has a step widening portion extending into the core area of the adjacent block storage area, so that a single block storage area can be located in the first direction (for example, the Y direction). ) The increase of the width of the upper step area is beneficial to the increase of the number of partitions and reduces the design difficulty of the structure of the three-dimensional memory of the present invention. The above-mentioned gate line gaps may only be filled with an insulating layer, or an array common source (Array Common Source, ACS) may be set in the gate line gaps to provide a common source electrode for the memory array. An insulating layer may be disposed between the array common source and the sidewall of the gate line gap.

Both the first core area and the second core area include a plurality of finger storage areas 23, and each finger storage area 23 is isolated by an inter-finger gate line gap 248. At this time, in order to more effectively utilize the device area, the extension The width of the first step widening portion 214 to the inside of the second core region is an integer multiple of the width of the finger storage region 23 . In addition, due to the overall widening of the step area, the width of the first bridging wall 215 in this embodiment can be designed to be between 0.5 of the width of the finger storage areas 23 to the width of two of the finger storage areas 23 . , the width of the second bridging wall 225 can be designed to be between 0.5 of the width of the finger storage areas 23 to the width of two of the finger storage areas 23 . The increase of the width of the step area in the Y direction of the single block storage area of the present invention can make the bridge wall have a larger design width, and the increase of the width of the bridge wall can reduce the area of the step contact area, thereby reducing the design of the structure of the three-dimensional memory of the present invention. difficulty.

As shown in FIG. 2 , in a specific embodiment, the first core area and the second core area each include three finger storage areas 23 , including bridge walls, the first step area 213 and the In addition to occupying the width of the three finger storage areas 23 in the corresponding core area, the second step area 223 also extends into the adjacent core area and additionally occupies the width of two finger storage areas 23, that is, the first step area 223 extends into the adjacent core area. The step widening portion 214 and the second step widening portion 224 have the width of two finger storage areas 23 , and the area occupied by the first step area 213 and the second step area 223 is the width of five finger storage areas 23 , The first bridging wall 215 and the second bridging wall 225 each occupy a width of one finger storage area 23 .

As shown in FIG. 4 , in another specific embodiment, the three-dimensional memory includes four block storage areas 41 , 42 , 43 and 44 , and each core area includes two finger storage areas, including bridge walls. , the first step area 213 and the second step area 223 not only occupy the width of the two finger storage areas of their corresponding core areas, but also extend into the adjacent core areas, occupying an additional finger storage area. Width, that is, the first step widening portion 414 and the second step widening portion 424 have a width of one finger storage area, and the area occupied by the first step area 213 and the second step area 223 is three fingers. The width of the storage area, wherein the first bridge wall 215 and the second bridge wall 225 each occupy a width of a storage area.

According to the idea of the present invention, the three-dimensional memory can be applied to the scene where one block storage area includes only one finger storage area, or the scene where one block storage area includes 4 or more finger storage areas, and is not limited to Examples listed above.

In this embodiment, the three-dimensional memory may be a 3D NAND memory, wherein the first core region and the second core region include a stack structure on a substrate and an array of channel memory structures penetrating the stack structure, The channel memory structure includes a channel hole penetrating the stack structure and a memory film and a channel layer located in the channel hole.

In this embodiment, the substrate is typically a silicon-containing substrate, such as Si, SOI (silicon-on-insulator), SiGe, SiC, etc., but is not limited to the above examples. Some peripheral devices such as field effect transistors, capacitors, inductors and/or diodes can be arranged on the substrate as required, and these peripheral devices are used as different functional devices of the memory, such as buffers, amplifiers, decoders, and the like. The stacked structure includes a stack of sacrificial dielectric layers and gate dielectric layers, for example, the stacked structure includes alternately stacked silicon nitride layers and silicon oxide layers. The sacrificial dielectric layer is removed in the subsequent process and replaced with a gate layer at the corresponding position. The gate layer can be, for example, polysilicon, copper, aluminum, tungsten, titanium, titanium nitride, tantalum, and tantalum nitride. and other materials, but are not limited to the examples listed here.

In this embodiment, the memory film includes a blocking layer, a charge trapping layer and a tunneling layer, wherein the blocking layer is located on the sidewall surface of the channel hole, and the charge trapping layer is located on the surface of the blocking layer, The tunneling layer is located on the surface of the charge trapping layer. For example, the material of the blocking layer may be silicon dioxide, the material of the charge trapping layer may be silicon nitride, and the material of the tunneling layer may be silicon dioxide. An exemplary material for the channel layer is polysilicon. It is understood, however, that other materials may be selected for these layers. For example, the material of the barrier layer may include a high-K oxide layer; the material of the channel layer may include semiconductor materials such as single crystal silicon, single crystal germanium, SiGe, SiC, SiGeC, SiGeH, and the like.

As shown in FIG. 2 and FIG. 3 , the present embodiment also provides a method for preparing a three-dimensional memory, including the steps:

First, step 1) is performed, a substrate is provided, and a stack structure is formed on the substrate.

In this embodiment, the substrate is typically a silicon-containing substrate, such as Si, SOI (silicon-on-insulator), SiGe, SiC, etc., but is not limited to the above examples. Some peripheral devices such as field effect transistors, capacitors, inductors and/or diodes can be arranged on the substrate as required, and these peripheral devices are used as different functional devices of the memory, such as buffers, amplifiers, decoders, and the like. The stacked structure includes a stack of sacrificial dielectric layers and gate dielectric layers, for example, the stacked structure includes alternately stacked silicon nitride layers and silicon oxide layers. The sacrificial dielectric layer is removed in the subsequent process and replaced with a gate layer at the corresponding position. The gate layer can be, for example, polysilicon, copper, aluminum, tungsten, titanium, titanium nitride, tantalum, and tantalum nitride. and other materials, but are not limited to the examples listed here.

Then step 2) is performed, a first block storage area 21 and a second block storage area 22 are formed in the stacked structure, and the first block storage area 21 includes a first core area and a core area located in the middle of the first core area. The first step area 213, the second storage area includes a second core area and a second step area 223 located in the middle of the second core area, the first core area and the second core area are adjacent in the first direction Arranged and isolated from each other, the first stepped area 213 and the second stepped area 223 are arranged adjacent to each other along the second direction and isolated from each other, wherein the first stepped area 213 has an extension along the first direction to all The first step widening portion 214 inside the second core region, the first step widening portion 214 is isolated from the second core region by the first gate line gap 241; the second step region 223 has a direction along the first direction The second step widening portion 224 reversely extends to the inside of the first core region, and the second step widening portion 224 is isolated from the first core region by a second gate line gap 245 .

The first core region includes a first sub-core region 211 and a second sub-core region 212 located at both ends of the first step region 213 and the second step region 223. The first sub-core region 211 and the first sub-core region 211 The step area 213 is connected, the second core area includes a third sub-core area 221 and a fourth sub-core area 222 located at both ends of the first step area 213 and the second step area 223, and the fourth core area is connected to the the second step area 223 is connected; the first storage area 21 further includes a first bridge wall 215 located on one side of the first step area 213 and the second step area 223, the first bridge wall 215 is connected to the The first step area 213 , the first sub-core area 211 and the second sub-core area 212 , and the second block storage area 22 further includes the first step area 213 and the second step area 223 on the other side The second bridge wall 225 connects the second step area 223 , the third sub-core area 221 and the fourth sub-core area 222 . The first sub-core region 211 and the third sub-core region 221 are isolated by a first inter-block gate line gap 242, and the first inter-block gate line gap 242 is connected to the first gate line gap 241, so The second sub-core region 212 and the fourth sub-core region 222 are isolated by a second inter-block gate line gap 243 , and the second inter-block gate line gap 243 is connected to the second gate line gap 245 . The first step widening portion 214 extends to be adjacent to the second bridging wall 225, and is isolated from the second bridging wall 225 by a third grid line gap 244, and the first grid line gap 241 is connected to the second bridging wall 225. The third gate line gap 244 is connected, the second step widening portion 224 extends to be adjacent to the first bridging wall 215 , and is isolated from the first bridging wall 215 by a fourth gate line gap 246 . The four gate line gaps 246 are connected to the second gate line gap 245 .

In this embodiment, forming the first core region and the second core region includes: forming a stack structure on a substrate, and forming a channel memory structure array penetrating the stack structure in the stack structure, the The channel memory structure includes a channel hole penetrating the stack structure and a memory film and a channel layer located in the channel hole. The memory film includes a blocking layer, a charge trapping layer and a tunneling layer, wherein the blocking layer is located on the sidewall surface of the channel hole, the charge trapping layer is located on the surface of the blocking layer, and the tunneling layer is located on the sidewall surface of the channel hole. the surface of the charge trapping layer. For example, the material of the blocking layer may be silicon dioxide, the material of the charge trapping layer may be silicon nitride, and the material of the tunneling layer may be silicon dioxide. An exemplary material for the channel layer is polysilicon. It is understood, however, that other materials may be selected for these layers. For example, the material of the barrier layer may include a high-K oxide layer; the material of the channel layer may include semiconductor materials such as single crystal silicon, single crystal germanium, SiGe, SiC, SiGeC, SiGeH, and the like.

In the process of forming the channel hole structure, the above-mentioned first inter-block gate line gap 242 , the first gate line gap 241 , the third gate line gap 244 , the fourth gate line gap 244 , the fourth gate line gap 244 and the fourth gate line gap The gate line gap 246, the second gate line gap 245 and the second inter-block gate line gap 243, wherein the first inter-block gate line gap 242 extends along the second direction (X direction) for isolating the first inter-block gate line gap 242 The sub-core region 211 and the third sub-core region 221, the first gate line gap 241 extends along the first direction (Y direction), and is used to isolate the first step region 213 and the third sub-core region 221, the third gate line gap 244 extends along the second direction (X direction) for isolating the first step region 213 and the second bridge wall 225, and the fourth gate line gap 246 extends along the second direction (X direction) for isolating the second step region 223 from the first bridging wall 215, the second gate line gap 245 extending along the first direction (Y direction) for isolating the first The second step region 223 and the second sub-core region 212, and the inter-block gate line gap extends along the second direction (X direction) for isolating the second sub-core region 212 and the fourth sub-core region District 222.

In the above process, a plurality of inter-finger gate line gaps 248 may be formed in the stacked structure at the same time, so as to isolate a plurality of finger storage regions in both the first core region and the second core region. At this time, in order to utilize the device area more effectively, the width of the first step widening portion 214 extending to the inside of the second core region is an integer multiple of the width of the finger storage region. In addition, due to the overall widening of the step area, the width of the first bridging wall 215 in this embodiment can be designed to be between 0.5 of the width of the finger storage areas 23 to the width of two of the finger storage areas 23 . , the width of the second bridging wall 225 may be designed to be between 0.5 of the width of the finger storage areas and the width of two of the finger storage areas. The increase of the width of the step area in the Y direction of the single block storage area of the present invention can make the bridge wall have a larger design width, and the increase of the width of the bridge wall can reduce the area of the step contact area, thereby reducing the design of the structure of the three-dimensional memory of the present invention. difficulty.

As shown in FIG. 2 , in a specific embodiment, the first core area and the second core area each include three finger storage areas, including the bridge wall, the first step area 213 and all the finger storage areas. The second step area 223 not only occupies the width of the three finger storage areas in the core area corresponding to itself, but also extends into the adjacent core area and additionally occupies the width of two finger storage areas, that is, the first step widening portion. 214 and the second step widening portion 224 have the width of 2 finger storage areas, and the area occupied by the first step area 213 and the second step area 223 is the width of 5 finger storage areas. A bridging wall 215 and the second bridging wall 225 each occupy the width of one finger storage area.

As shown in FIG. 4 , in another specific embodiment, both the first core area and the second core area include two finger storage areas, including bridge walls, the first step area 213 and The second step area 223 not only occupies the width of two finger storage areas in its corresponding core area, but also extends into the adjacent core area and additionally occupies the width of one finger storage area, that is, the first step is widened. The portion 214 and the second step widening portion 224 have the width of one finger storage area, and the area occupied by the first step area 213 and the second step area 223 is the width of three finger storage areas, wherein the The first bridging wall 215 and the second bridging wall 225 each occupy a width of one finger storage area.

According to the idea of the present invention, the three-dimensional memory can be applied to the scene where one block storage area includes only one finger storage area, or the scene where one block storage area includes 4 or more finger storage areas, and is not limited to Examples listed above.

Next, the first step area 213 and the second step area 223 are formed by a step etching process, and the steps of the first step area 213 and the second step area 223 go from the corresponding core area to the first step area. The isolation belt 247 between the step area 213 and the second step area 223 is lowered in sequence, and is cut off at the isolation belt 247 . The isolation strip 247 extends along the first direction (Y direction) for isolating the first step area 213 and the second step area 223 .

As mentioned above, the three-dimensional memory of the present invention and the preparation method thereof have the following beneficial effects:

In the present invention, through the novel gate line gap (GLS) design, the step area of the block storage area has a step widening portion extending into the core area of the adjacent block storage area, so that a single block storage area can be located in the first direction (for example, the Y direction). ) increase in the width of the upper step area.

The increase of the width of the step area in the Y direction of the single block storage area of the present invention is beneficial to the increase of the number of partitions, and at the same time, the bridge wall can have a larger design width, and the increase in the width of the bridge wall can reduce the area of the step contact area, thereby reducing the cost of The design difficulty of the architecture of the invented three-dimensional memory.

Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

The above-mentioned embodiments merely illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed in the present invention should still be covered by the claims of the present invention.

Claims (16)

1. A three-dimensional memory, characterized in that, the three-dimensional memory includes a first block storage area and a second block storage area, and the first block storage area includes a first core area and a core area located in the middle of the first core area. a first step area, the second storage area includes a second core area and a second step area located in the middle of the second core area, the first core area and the second core area are arranged adjacent to each other along the first direction and isolated from each other, the first stepped region and the second stepped region are adjacently arranged along a second direction and isolated from each other, wherein the first stepped region has a feature extending to the second core region along the first direction an inner first step widening part, the first step widening part is isolated from the second core area by a first gate line gap; the second step area has a reverse extending to the first core along a first direction A second step widening portion inside the region, the second step widening portion being isolated from the first core region by a second gate line gap. 2 . The three-dimensional memory according to claim 1 , wherein the first core region comprises a first sub-core region and a second sub-core region located at both ends of the first stepped region and the second stepped region, and the The first sub-core area is connected to the first step area, the second core area includes a third sub-core area and a fourth sub-core area located at both ends of the first step area and the second step area, the The fourth core area is connected with the second step area; the first storage area further includes a first bridge wall on one side of the first step area and the second step area, and the first bridge wall is connected to the second step area. the first step area, the first sub-core area and the second sub-core area, the second block storage area further includes a second bridge wall on the other side of the first step area and the second step area, The second bridge wall connects the second step area, the third sub-core area and the fourth sub-core area. 3 . The three-dimensional memory according to claim 2 , wherein the first sub-core region and the third sub-core region are separated by a first inter-block gate line gap, and the first inter-block gate line gap connected to the first gate line gap, the second sub-core region and the fourth sub-core region are isolated by a second inter-block gate line gap, the second inter-block gate line gap and the second gate Line gaps are connected. 4 . The three-dimensional memory of claim 3 , wherein the first step widening portion extends to be adjacent to the second bridging wall, and is isolated from the second bridging wall by a third gate line gap. 5 . , the first gate line gap is connected to the third gate line gap, the second step widening portion extends to be adjacent to the first bridging wall, and is connected to the first bridge through the fourth gate line gap wall isolation, the fourth gate line gap is connected with the second gate line gap. 5 . The three-dimensional memory according to claim 2 , wherein the first core area and the second core area each include a plurality of finger storage areas, and the finger storage areas are isolated by inter-finger gate line gaps. 6 . . 6 . The three-dimensional memory according to claim 5 , wherein the width of the first step widening portion extending to the inside of the second core region is an integer multiple of the width of the finger storage region. 7 . 7 . The three-dimensional memory according to claim 5 , wherein the width of the first bridge wall and the second bridge wall is between 0.5 of the finger storage area and 2 of the finger storage area. 8 . between the widths. 8 . The three-dimensional memory according to claim 1 , wherein the steps of the first step area and the second step area are directed from the corresponding core area to the space between the first step area and the second step area. 9 . The separators are sequentially lowered and cut off at the separators. 9 . The three-dimensional memory of claim 1 , wherein the first direction and the second direction are perpendicular to each other. 10 . 10 . The three-dimensional memory of claim 1 , wherein the first core region and the second core region comprise a stack structure and an array of channel memory structures penetrating the stack structure, the channel memory structures comprising A channel hole penetrating the stack structure and a memory film and a channel layer located in the channel hole. 11. A method for preparing a three-dimensional memory, comprising the steps of: providing a substrate on which a stacked structure is formed; A first block storage area and a second block storage area are formed in the stacked structure, the first block storage area includes a first core area and a first step area located in the middle of the first core area, the second block area The storage area includes a second core area and a second step area located in the middle of the second core area, the first core area and the second core area are adjacently arranged along a first direction and isolated from each other, the first step area The first step area and the second step area are arranged adjacent to each other along the second direction and isolated from each other, wherein the first step area has a first step widening portion extending to the inside of the second core area along the first direction, so The first step widening portion is isolated from the second core region by a first gate line gap; the second step widening portion has a second step widening portion reversely extended to the inside of the first core region along the first direction, The second step widening portion is isolated from the first core region by a second gate line gap. 12 . The method for manufacturing a three-dimensional memory according to claim 11 , wherein the first core region comprises a first sub-core region and a second sub-core region located at both ends of the first stepped region and the second stepped region. 13 . The first sub-core region is connected to the first stepped region, and the second core region includes a third sub-core region and a fourth sub-core region located at both ends of the first stepped region and the second stepped region , the fourth core area is connected to the second step area; the first block storage area further includes a first bridge wall located on one side of the first step area and the second step area, the first bridge The wall connects the first step area, the first sub-core area and the second sub-core area, and the second block storage area further includes a second step area on the other side of the first step area and the second step area. A bridging wall, the second bridging wall connects the second step area, the third sub-core area and the fourth sub-core area. 13 . The method for manufacturing a three-dimensional memory according to claim 12 , wherein the first sub-core region and the third sub-core region are isolated by a first inter-block gate line gap, and the first inter-block A gate line gap is connected to the first gate line gap, the second sub-core region and the fourth sub-core region are separated by a second inter-block gate line gap, and the second inter-block gate line gap is connected to the The second gate line gap is connected. 14 . The method for manufacturing a three-dimensional memory according to claim 13 , wherein the first step widening portion extends to be adjacent to the second bridge wall, and is connected to the second bridge wall through a third gate line gap. 15 . A bridge wall is isolated, the first gate line gap is connected to the third gate line gap, the second step widening portion extends to be adjacent to the first bridge wall, and is connected to the third gate line gap through a fourth gate line gap The first bridge wall is isolated, and the fourth gate line gap is connected to the second gate line gap. 15 . The method for preparing a three-dimensional memory according to claim 12 , wherein the first core region and the second core region both comprise a plurality of finger storage regions, and finger-to-digital gates pass between the finger storage regions. 16 . Line gap isolation, the width of the first step widening portion extending to the inside of the second core area is an integer multiple of the width of the finger storage area, and the width of the first bridge wall is between 0.5 of the finger storage area The width of the second bridging wall is between the width of 0.5 and the width of the two finger storage areas. 16 . The method for manufacturing a three-dimensional memory according to claim 11 , wherein the steps of the first step area and the second step area are directed from the corresponding core area to the first step area and the second step area. 17 . The separators between them are sequentially lowered and cut off at the separators.

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