CN111403292A - Manufacturing method of self-aligned contact hole shielded gate power MOSFET device and formed device - Google Patents

Abstract

The present invention relates to a method for manufacturing a self-aligned contact hole shielded gate power MOSFET device. Silicon fills the gap between the shielding gate dielectric layers to form a third dielectric layer covering the first polysilicon and the shielding gate dielectric layer, and forms a second gate dielectric layer on the exposed silicon surface in the trench to form a filling trench The second polysilicon in the gap, the first dielectric layer is etched back and implanted in the horizontal direction to form the source region, the fourth dielectric layer is formed, and the first contact hole with the second polysilicon exposed at the bottom is formed. the second contact hole of the first dielectric layer on the side, remove the exposed first dielectric layer, form a contact area at the bottom of the second contact hole, and perform horizontal etching back on the fourth dielectric layer to form an enlarged first contact hole and The enlarged second contact hole forms a metal contact to form a source electrode and a gate electrode, so that the device has high reliability and small size.

Description

Self-aligned contact hole shielded gate power MOSFET device and method for making the same device

technical field

The invention relates to a semiconductor manufacturing process, in particular to a manufacturing method of a self-aligned contact hole shielded gate power MOSFET device.

Background technique

Shielded gate power MOSTET devices are commonly used devices in semiconductor integrated circuits. In the manufacturing process of semiconductor integrated circuits, as the technology node of semiconductor manufacturing continues to advance, it is expected that the device size will continue to shrink.

For common shielded gate power MOSTET devices, contact holes are often punched on the top of the polysilicon and source regions to lead out the polysilicon and source regions to form gates and sources, but lithography technology has the minimum lithography line width and registration. Deviation, the lithography and etching of the polysilicon and the source region contact holes need to consider the registration deviation. When the width of the polysilicon and the source region does not meet the registration deviation, it will cause the contact hole and the polysilicon and the source region to connect deviation or even short-circuit. risk and affect device performance. In addition, the size of the device must have a certain margin to make up for the registration deviation in the photolithography and etching process, and to meet the requirements of the device channel and performance.

SUMMARY OF THE INVENTION

A method for manufacturing a self-aligned contact hole shielded gate power MOSFET device provided by the present invention includes: S1: providing a semiconductor substrate, forming a first conductive type epitaxial layer on the surface of the semiconductor substrate, and performing ion implantation on the surface of the semiconductor substrate. A well region of the second conductivity type is formed on the surface of the semiconductor substrate; S2: the first gate dielectric layer, the first dielectric layer and the second dielectric layer are formed in sequence, a trench pattern is formed by photolithography, and the silicon surface of the trench pattern region is removed. the first gate dielectric layer, the first dielectric layer and the second dielectric layer, and the first dielectric layer and the second dielectric layer are used as hard mask layers to perform a trench silicon etching process to form a trench in the semiconductor substrate ; S3: forming a shielding gate dielectric layer on the bottom surface and side surface of the trench, the shielding gate dielectric layer does not completely fill the trench and forms a gap region in the central region of the trench; S4: perform polysilicon depositing a first polysilicon in the trench to completely fill the gap region in the trench, and performing a first polysilicon etch back to etch away part of the first polysilicon in the trench polysilicon; S5: forming a third dielectric layer, so that the third dielectric layer covers the sidewall of the trench and above the first polysilicon and the shielding gate dielectric layer, and removes the surface covering the trench For the third dielectric layer on the sidewall, only the third dielectric layer overlying the first polysilicon and the shielding gate dielectric layer remains, and the second dielectric layer on the first dielectric layer is removed; S6 : forming a second gate dielectric layer on the exposed silicon surface in the trench, performing polysilicon deposition to form a second polysilicon in the trench, so as to completely fill the gap in the trench, and performing the first step Two polysilicon etchbacks; S7: perform etchback in the horizontal direction of the first dielectric layer to form a source region implantation region, and perform source region implantation to respectively form source regions in the well regions on both sides of the trench; S8: form a second Four dielectric layers, so that the fourth dielectric layer covers the surface of the first dielectric layer, the first gate dielectric layer, the second gate dielectric layer and the second polysilicon; S9: perform photolithography etching forming a first contact hole and a second contact hole, wherein the bottom of the first contact hole exposes the second polysilicon, and the bottom of the second contact hole exposes the first dielectric layer on at least one side of the trench; S10: Remove the exposed first dielectric layer, and perform contact hole implantation to form a heavily doped well contact region of the second conductivity type at the bottom of the second contact hole, and perform horizontal recovery of the fourth dielectric layer. engraving, the first contact hole is further enlarged to form an enlarged first contact hole, the second contact hole is further enlarged to expose the source region to form an enlarged second contact hole, and the enlarged second contact hole is removed a first gate dielectric layer at the bottom of the hole; and S11: forming a front-side metal layer, the front-side metal layer covering the fourth dielectric layer, and filling the enlarged first contact hole and the enlarged second contact hole, to Photolithography is performed on the front side metal layer to form a source electrode and a gate electrode, the source electrode contacts the source region through the enlarged second contact hole, and the gate electrode passes through the enlarged first contact hole in contact with the second polysilicon.

Still further, the thickness of the third dielectric layer separates the first polysilicon and the second polysilicon from each other.

Furthermore, the shielded gate trench power MOSTET device is an N-type device, the first conductivity type is N-type, the second conductivity type is P-type, and the semiconductor substrate is N-type doped.

Further, the shielded gate trench power MOSTET device is a P-type device, the first conductivity type is P-type, the second conductivity type is N-type, and the semiconductor substrate is P-type doped.

Furthermore, in step S4, the remaining first polysilicon is located in the semiconductor substrate under the well region.

Further, the first dielectric layer is a silicon nitride layer.

Further, the second dielectric layer, the first gate dielectric layer, the shielding gate dielectric layer, the third dielectric layer, the second gate dielectric layer and the fourth dielectric layer are oxide layers .

Furthermore, in step S6, the second polysilicon is etched back to remove the second polysilicon outside the trench.

Furthermore, the thickness of the third dielectric layer prevents leakage current between the first polysilicon and the second polysilicon.

The present invention also provides a self-aligned contact hole shielded gate power MOSFET device, the self-aligned contact hole shielded gate power MOSFET device is manufactured according to the above-mentioned manufacturing method of the self-aligned contact hole shielded gate power MOSFET device.

In the method for manufacturing a self-aligned contact hole shielded gate power MOSFET device provided by the present invention, a well region is formed on the surface of a substrate, a trench is formed in the substrate, a shielded gate dielectric layer is formed at the bottom and side of the trench, and the first multiple Silicon fills the gap between the shielding gate dielectric layers to form a third dielectric layer covering the first polysilicon and the shielding gate dielectric layer, and forms a second gate dielectric layer on the exposed silicon surface in the trench to form a filled trench The second polysilicon in the middle gap, the first dielectric layer is etched back and implanted in the horizontal direction to form the source region, the fourth dielectric layer is formed, the first contact hole with the second polysilicon exposed at the bottom, and the bottom exposed in the trench is formed The second contact hole of the first dielectric layer on one side is removed, the exposed first dielectric layer is removed, a contact area is formed at the bottom of the second contact hole, and the fourth dielectric layer is etched back in the horizontal direction to form an enlarged first contact hole The source electrode and the gate electrode are formed by forming metal contact with the enlarged second contact hole, so that the device has high reliability and small size.

Description of drawings

1 to 12 are schematic diagrams of devices in a manufacturing process of a self-aligned contact hole shielded gate power MOSFET according to an embodiment of the present invention.

The main components in the figure are described as follows:

110, semiconductor substrate; 130, trench; 124, shield gate dielectric layer; 131, first polysilicon; 125, third dielectric layer; 132, second polysilicon; 111, well region; 126, second gate dielectric layer; 140, source region; 160, well region contact region; 121, first gate dielectric layer; 122, first dielectric layer; 127, fourth dielectric layer; 172, gate electrode; 171, source electrode; 151a, The enlarged first contact hole; 152a, the enlarged second contact hole.

Detailed ways

The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present invention.

In an embodiment of the present invention, a method for manufacturing a self-aligned contact hole shielded gate power MOSFET device is provided, including: S1: providing a semiconductor substrate, and forming a first conductivity type epitaxial layer on the surface of the semiconductor substrate , perform ion implantation to form a well region of the second conductivity type on the surface of the semiconductor substrate; S2: sequentially form a first gate dielectric layer, a first dielectric layer and a second dielectric layer, form a trench pattern by photolithography, and remove the trench The first gate dielectric layer, the first dielectric layer and the second dielectric layer on the silicon surface of the pattern area, and the first dielectric layer and the second dielectric layer are used as the hard mask layer, and the trench silicon etching process is performed to form the semiconductor lining. A trench is formed in the bottom; S3: A shielding gate dielectric layer is formed on the bottom surface and side surfaces of the trench, and the shielding gate dielectric layer does not completely fill the trench and forms a gap in the central area of the trench S4: perform polysilicon deposition to form a first polysilicon in the trench to completely fill the gap in the trench, and perform an etchback of the first polysilicon to etch away the trench Part of the first polysilicon in the trench; S5: forming a third dielectric layer, so that the third dielectric layer covers the sidewall of the trench and above the first polysilicon and the shielding gate dielectric layer, and removes the cover On the third dielectric layer on the sidewall of the trench, only the third dielectric layer overlying the first polysilicon and the shielding gate dielectric layer remains, and the first dielectric layer is removed. A second dielectric layer; S6: forming a second gate dielectric layer on the exposed silicon surface in the trench, and performing polysilicon deposition to form a second polysilicon in the trench, so as to close the gap in the trench Completely fill, and perform a second polysilicon etchback; S7: perform a horizontal etchback of the first dielectric layer to form a source region implantation region, and perform source region implantation to respectively form sources in the well regions on both sides of the trench region; S8: forming a fourth dielectric layer, so that the fourth dielectric layer covers the surface of the first dielectric layer, the first gate dielectric layer, the second gate dielectric layer and the second polysilicon; S9 : performing photolithography to form a first contact hole and a second contact hole, wherein the bottom of the first contact hole exposes the second polysilicon, and the bottom of the second contact hole exposes at least one side of the trench the first dielectric layer; S10: remove the exposed first dielectric layer, and perform contact hole implantation to form a second conductive type heavily doped well region contact region at the bottom of the second contact hole, and perform the first dielectric layer. The four dielectric layers are etched back in the horizontal direction, the first contact hole is further enlarged to form an enlarged first contact hole, the second contact hole is further enlarged to expose the source region to form an enlarged second contact hole, and all the second contact holes are removed. forming a first gate dielectric layer at the bottom of the enlarged second contact hole; and S11: forming a front side metal layer, the front side metal layer covering the fourth dielectric layer, and filling the enlarged first contact hole and the enlarged a second contact hole, a source electrode and a gate electrode are formed by photolithographic etching of the front metal layer, the source electrode is in contact with the source region through the enlarged second contact hole, and the gate electrode is connected to the source region through the enlarged second contact hole The enlarged first contact hole is in contact with the second polysilicon.

More specifically, please refer to FIGS. 1 to 12 . FIGS. 1 to 12 are schematic diagrams of devices in the manufacturing process of the self-aligned contact hole shielded gate power MOSFET according to an embodiment of the present invention. A method for manufacturing a self-aligned contact hole shielded gate power MOSFET device according to an embodiment of the present invention includes:

S1 : As shown in FIG. 1 , a semiconductor substrate 110 is provided, a first conductivity type epitaxial layer is formed on the surface of the semiconductor substrate 110 , and ion implantation is performed to form a well region of the second conductivity type on the surface of the semiconductor substrate 110 111.

In one embodiment, the semiconductor substrate 110 is a silicon substrate.

S2: As shown in FIG. 2, the first gate dielectric layer 121, the first dielectric layer 122 and the second dielectric layer 123 are sequentially formed, a trench pattern is formed by photolithography, and the first gate dielectric layer on the silicon surface of the trench pattern area is removed 121, the first dielectric layer 122 and the second dielectric layer 123, the first dielectric layer 122 and the second dielectric layer 123 are used as hard mask layers, and a trench silicon etching process is performed to form a trench in the semiconductor substrate 110 Slot 130.

In one embodiment, the first dielectric layer 122 is a silicon nitride layer, and the second dielectric layer 123 is an oxide layer, such as a silicon oxide layer.

In one embodiment, the first gate dielectric layer 121 is an oxide layer, such as a silicon oxide layer.

S3 : As shown in FIG. 3 , a shielding gate dielectric layer 124 is formed on the bottom surface and the side surface of the trench 130 . The shielding gate dielectric layer 124 does not completely fill the trench 130 but is located on the side of the trench 130 . The central region forms a gap region.

In one embodiment, the shielding gate dielectric layer 124 is an oxide layer, such as a silicon oxide layer.

S4: As shown in FIG. 4, polysilicon deposition is performed to form a first polysilicon 131 in the trench 130, so as to completely fill the gap area in the trench 130, as shown in FIG. 5, and the first polysilicon 131 is formed. A polysilicon 131 is etched back to etch away part of the first polysilicon 131 in the trench 130 .

In one embodiment, the remaining first polysilicon 131 is located in the semiconductor substrate 110 below the well region 111 .

S5: As shown in FIG. 6, a third dielectric layer 125 is formed, so that the third dielectric layer 125 covers the sidewall of the trench 130 and the top of the first polysilicon 131 and the shielding gate dielectric layer 124, and is removed The third dielectric layer 125 covering the sidewalls of the trench 130, and only the third dielectric layer 125 covering the first polysilicon 131 and the shielding gate dielectric layer 124 remains, and removed The second dielectric layer 123 on the first dielectric layer 122 .

In one embodiment, the third dielectric layer 125 is an oxide layer, such as a silicon oxide layer. In one embodiment, the material of the third dielectric layer 125 and the shielding gate dielectric layer 124 is the same.

S6: As shown in FIG. 7, a second gate dielectric layer 126 is formed on the exposed silicon surface in the trench 130, and polysilicon is deposited to form a second polysilicon 132 in the trench 130, so that the The gaps in the trenches 130 are completely filled, and the second polysilicon 132 is etched back.

In one embodiment, the second polysilicon 132 is etched back to remove the second polysilicon 132 outside the trench 130 .

In one embodiment, the second gate dielectric layer 126 is an oxide layer, such as a silicon oxide layer.

S7 : as shown in FIG. 8 , perform etchback in the horizontal direction of the first dielectric layer 122 to form source implantation regions, and perform source implantation to form source regions 140 in the well regions 111 on both sides of the trench 130 respectively.

In one embodiment, the source region 140 is a heavily doped region of the first conductivity type.

S8: As shown in FIG. 9, a fourth dielectric layer 127 is formed, so that the fourth dielectric layer 127 covers the first dielectric layer 122, the first gate dielectric layer 121, the second gate dielectric layer 126 and the The surface of the second polysilicon 132 .

In one embodiment, the fourth dielectric layer 127 is an oxide layer, such as a silicon oxide layer. In one embodiment, the material of the fourth dielectric layer 127 is the same as that of the shielding gate dielectric layer 124 .

S9: As shown in FIG. 10, photolithography is performed to form a first contact hole 151 and a second contact hole 152, wherein the bottom of the first contact hole 151 exposes the second polysilicon 132, and the bottom of the second contact hole 152 is exposed The first dielectric layer 122 on at least one side of the trench 130 is exposed.

S10 : As shown in FIG. 11 , remove the exposed first dielectric layer 122 , and perform contact hole implantation to form a second conductive type heavily doped well contact region 160 at the bottom of the second contact hole 152 , and perform The fourth dielectric layer 127 is etched back in the horizontal direction to further expand the first contact hole 151 to form an enlarged first contact hole 151a, and to further expand the second contact hole 152 to expose the source region 140 to form an enlarged first contact hole 151a. the second contact hole 152a, the first gate dielectric layer 121 at the bottom of the enlarged second contact hole 152a is removed.

At this time, without etching the surface of the semiconductor substrate 110, the enlarged second contact hole 152a can be in contact with the source region 140 and the well region contact region 160 at the same time.

S11: As shown in FIG. 12, a front metal layer is formed, the front metal layer covers the fourth dielectric layer 127, and fills the enlarged first contact hole 151a and the enlarged second contact hole 152a. The front side metal layer is lithographically etched to form a source electrode 171 and a gate electrode 172, the source electrode 171 contacts the source region 140 through the enlarged second contact hole 152a, and the gate electrode 172 passes through the enlarged second contact hole 152a. The first contact hole 151 a is in contact with the second polysilicon 132 .

In an embodiment of the present invention, the thickness of the third dielectric layer 125 is such that the first polysilicon 131 and the second polysilicon 132 are spaced apart from each other. Furthermore, the thickness of the third dielectric layer 125 prevents leakage between the first polysilicon 131 and the second polysilicon 132 .

In an embodiment of the present invention, it is not necessary to consider the lithography and etching registration deviation of the contact holes between the polysilicon and the source region. As mentioned above, even if there is a registration deviation, the source electrode can still be in contact with the source and well regions. The gate is fully contacted with the second polysilicon without causing the connection deviation between the contact hole and the polysilicon and the source region. Therefore, the above embodiments of the present invention are used to avoid the influence of the registration deviation. In addition, the device size does not need to leave a margin for the registration deviation, so the device size can be reduced. Moreover, the contact hole corresponding to the source electrode of the present invention does not need to pass through the source region to form a connection, that is, the enlarged second contact hole is connected to the source region and the well region contact region through surface contact, so the process of the present invention can be made simpler. .

In one embodiment, the shielded gate trench power MOSTET device is an N-type device, the first conductivity type is N-type, the second conductivity type is P-type, and the semiconductor substrate 110 is N-type doped. In one embodiment, the shielded gate trench power MOSTET device is a P-type device, the first conductivity type is P-type, the second conductivity type is N-type, and the semiconductor substrate 110 is P-type doped.

In an embodiment of the present invention, a self-aligned contact hole shielded gate power MOSFET device is also provided, which is formed by the above-mentioned manufacturing method of a self-aligned contact hole shielded gate power MOSFET device.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features thereof can be equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the embodiments of the present invention. scope.

Claims (10)

1. a kind of manufacture method of self-aligned contact hole shielded gate power MOSFET device, is characterized in that, comprises: S1: providing a semiconductor substrate, forming an epitaxial layer of a first conductivity type on the surface of the semiconductor substrate, and performing ion implantation to form a well region of the second conductivity type on the surface of the semiconductor substrate; S2: Form a first gate dielectric layer, a first dielectric layer and a second dielectric layer in sequence, form a trench pattern by photolithography, and remove the first gate dielectric layer, the first dielectric layer and the second dielectric on the silicon surface of the trench pattern area layer, the first dielectric layer and the second dielectric layer are used as hard mask layers, and a trench silicon etching process is performed to form a trench in the semiconductor substrate; S3: forming a shielding gate dielectric layer on the bottom surface and side surfaces of the trench, the shielding gate dielectric layer does not completely fill the trench and forms a gap region in the central region of the trench; S4: perform polysilicon deposition to form first polysilicon in the trench to completely fill the gap in the trench, and perform first polysilicon etch back to etch away the trench part of the first polysilicon; S5: forming a third dielectric layer so that the third dielectric layer covers the sidewalls of the trench and above the first polysilicon and the shielding gate dielectric layer, and removes all the sidewalls covering the trenches the third dielectric layer, only the third dielectric layer covering the first polysilicon and the shielding gate dielectric layer remains, and the second dielectric layer on the first dielectric layer is removed; S6: forming a second gate dielectric layer on the exposed silicon surface in the trench, performing polysilicon deposition to form a second polysilicon in the trench, so as to completely fill the gap in the trench, and performing The second polysilicon is etched back; S7: performing etchback in the horizontal direction of the first dielectric layer to form a source region implantation region, and performing source region implantation to respectively form source regions in the well regions on both sides of the trench; S8: forming a fourth dielectric layer, so that the fourth dielectric layer covers the surfaces of the first dielectric layer, the first gate dielectric layer, the second gate dielectric layer and the second polysilicon; S9: Perform photolithography to form a first contact hole and a second contact hole, wherein the bottom of the first contact hole exposes the second polysilicon, and the bottom of the second contact hole exposes at least one of the trenches located at the bottom the first dielectric layer on the side; S10: Remove the exposed first dielectric layer, and perform contact hole implantation to form a heavily doped well contact region of the second conductivity type at the bottom of the second contact hole, and perform horizontal recovery of the fourth dielectric layer. engraving, the first contact hole is further enlarged to form an enlarged first contact hole, the second contact hole is further enlarged to expose the source region to form an enlarged second contact hole, and the enlarged second contact hole is removed a first gate dielectric layer at the bottom of the hole; and S11: forming a front metal layer, covering the fourth dielectric layer, filling the enlarged first contact hole and the enlarged second contact hole, and performing photolithography on the front metal layer to form A source electrode is in contact with the source region through the enlarged second contact hole, and the gate electrode is in contact with the second polysilicon through the enlarged first contact hole. 2 . The method for manufacturing a self-aligned contact hole shielded gate power MOSFET device according to claim 1 , wherein the thickness of the third dielectric layer is such that the first polysilicon and the second polysilicon have a thickness. 3 . The silicon is spaced apart from each other. 3. The method for manufacturing a self-aligned contact hole shielded gate power MOSFET device according to claim 1, wherein the shielded gate trench power MOSFET device is an N-type device, the first conductivity type is N-type, and the second conductivity type is N-type. The type is P-type, and the semiconductor substrate is N-type doped. 4. The method for manufacturing a self-aligned contact hole shielded gate power MOSFET device according to claim 1, wherein the shielded gate trench power MOSFET device is a P-type device, the first conductivity type is P-type, and the second conductivity type is P-type. The type is N-type, and the semiconductor substrate is P-type doped. 5 . The method of claim 1 , wherein in step S4 , the remaining first polysilicon is located in the semiconductor substrate under the well region. 6 . 6 . The method for manufacturing a self-aligned contact hole shielded gate power MOSFET device according to claim 1 , wherein the first dielectric layer is a silicon nitride layer. 7 . 7 . The method for manufacturing a self-aligned contact hole shielded gate power MOSFET device according to claim 1 , wherein the second dielectric layer, the first gate dielectric layer, the shielded gate dielectric layer, the The third dielectric layer, the second gate dielectric layer and the fourth dielectric layer are oxide layers. 8 . The method for manufacturing a self-aligned contact hole shielded gate power MOSFET device according to claim 1 , wherein in step S6 , the second polysilicon is etched back to remove the second polysilicon outside the trench. 9 . polysilicon. 9 . The method for manufacturing a self-aligned contact hole shielded gate power MOSFET device according to claim 1 , wherein the thickness of the third dielectric layer is such that the first polysilicon and the second polysilicon have a thickness. 10 . There is no leakage between silicon. 10. A self-aligned contact hole shielded gate power MOSFET device, wherein the self-aligned contact hole shielded gate power MOSFET device is according to the self-aligned contact hole shielded gate of any one of claims 1 to 10. Manufacturing method of power MOSFET device.

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