CN111402942A - Nonvolatile memory and method of making the same - Google Patents

Abstract

The present invention relates to a non-volatile memory including stacked layers and a memory cell array. The stacked layers include stacked first and second stacks and a connection layer between the first and second stacks, the first and second stacks respectively including alternately stacked gate layers and dielectric layers. The memory cell array includes a plurality of memory strings, each memory string includes a first substring and a second substring, the first substring vertically extends through the first stack, and the second substring extends vertically through the second substring stack, the first substring includes a first channel layer, the second substring includes a second channel layer, the first channel layer is electrically connected to the second channel layer; wherein the connection The layer is opposite to the channel connection parts of the first channel layer and the second channel layer in the extending direction of the stacked layers, and a dielectric layer is formed between the connection layer and the channel connection part .

Description

Nonvolatile memory and method of making the same

This case is a divisional application of the Chinese patent application with the application number "201910728547.6", which was submitted on August 8, 2019

technical field

The present invention relates to the technical field of semiconductor devices, and in particular, to a non-volatile memory and a manufacturing method thereof.

Background technique

With the development of technology, the size requirements of electronic products are getting smaller and smaller, and at the same time, storage devices are required to be small in size and high in capacity. Non-volatile memory can retain stored data in the event of a power outage. In order to improve the integration degree of non-volatile memory, a 3D non-volatile memory device in which memory cells are vertically stacked from a silicon substrate is proposed.

For a 3D NAND type non-volatile memory with a vertical channel structure, there is a stack structure formed by alternately stacking dielectric layers and gate layers, and a channel hole penetrating the stack structure. As the number of stacked layers increases, deep hole etching becomes more and more difficult. A common practice is to connect two or more stack structures in a vertical direction to form a stack structure with more layers. An oxide layer is used to connect different stack structures, and then the functional layer inside the channel hole is deposited once. The usual layup sequence of the functional layer is from the sidewall of the channel hole to the center of the channel hole, the barrier layer, the storage layer and the tunneling layer are sequentially deposited, and then the conductive layer is deposited. Due to the deep channel holes formed by connecting multiple stack structures, the thickness of the functional layers formed by one deposition will be inconsistent up and down, and the consistency of the composition of each layer will be poor, resulting in poor electrical performance of the memory. . On the other hand, due to the increase of the number of layers, the problem of program disturbance in the programming stage of the non-volatile memory with multiple stack structures will be more serious.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention is to provide a non-volatile memory with better functional layer consistency and a manufacturing method thereof, which can reduce programming interference.

The present invention provides a non-volatile memory including stacked layers and a memory cell array. The stacked layers include stacked first and second stacks and a connection layer between the first and second stacks, the first and second stacks respectively including alternately stacked gate layers and dielectric layers. The memory cell array includes a plurality of memory strings, each memory string includes a first substring and a second substring, the first substring vertically extends through the first stack, and the second substring vertically extends through the second substring stack, the first substring includes a first channel layer, the second substring includes a second channel layer, the first channel layer is electrically connected to the second channel layer; wherein the connection The layer is opposite to the channel connection parts of the first channel layer and the second channel layer in the extending direction of the stacked layers, and a dielectric layer is formed between the connection layer and the channel connection part .

In an embodiment of the invention, the first substring includes a first charge storage layer, the second substring includes a second charge storage layer, wherein the first charge storage layer and the second charge storage layer The layer does not extend to the region between the connection layer and the channel connection.

In an embodiment of the present invention, the channel connecting portions of the first channel layer and the second channel layer are hollow columnar or solid columnar.

In an embodiment of the present invention, the connection layer and the channel connection portion constitute an intermediate string selection transistor without memory cells, which is electrically connected between the first substring and the second substring. between.

In an embodiment of the present invention, the above-mentioned non-volatile memory further includes a controller configured to: during programming, apply a programming voltage to selected memory cells of each memory string, and apply a first conduction voltage to unselected memory cells A turn-on voltage is applied, and a second turn-on voltage is applied to the middle string selection transistor, wherein in at least a part of the programming period, the second turn-on voltage is greater than the first turn-on voltage.

In an embodiment of the present invention, the waveform of the second turn-on voltage is the same as the waveform of the programming voltage, and the ratio of the second turn-on voltage to the programming voltage is between 0.9 and 1.1.

In an embodiment of the present invention, the waveform of the second turn-on voltage is the same as the waveform of the first turn-on voltage, and the second turn-on voltage and the programming voltage are less than or equal to 1.1.

The present invention also provides a method for manufacturing a non-volatile memory, comprising the following steps: forming a first stack, the first stack including alternately stacked first material layers and second material layers; forming a vertical penetration through the first material layer a first substring of a stack, the first substring including a first channel layer; a connection layer is formed on the first stack; a second stack is formed on the connection layer, the second stack includes alternating stacks a first material layer and a second material layer of the second channel layer, wherein the channel connection parts of the first channel layer and the second channel layer are opposite to the connection layer in the extending direction of the stacked layers, and the channel connection Between the part and the connection layer is a dielectric layer; wherein the first material layer is a gate layer or a dummy gate layer, and the second material layer is a dielectric layer.

In an embodiment of the present invention, the first substring further includes a first charge storage layer, the second substring further includes a second charge storage layer, wherein the first charge storage layer and the second charge storage layer The charge storage layer does not extend to the region between the connection layer and the channel connection.

In an embodiment of the present invention, after forming a connection layer on the first stack, the method further includes: forming a channel connection part contacting the first channel layer; and when forming the second substring, the The second channel layer contacts the channel connection.

In an embodiment of the present invention, the channel connecting portion is in the shape of a hollow column or a solid column.

In an embodiment of the present invention, the connection layer and the channel connection portion constitute an intermediate string selection transistor without memory cells, which is electrically connected between the first substring and the second substring. between.

According to the manufacturing method of the non-volatile memory of the present invention, the functional layer and the conductive channel layer in each stack are formed respectively, and the upper and lower uniformity and consistency of the functional layer and the conductive channel layer are improved.

Description of drawings

In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein:

FIG. 1A is a schematic structural diagram of a 3D NAND memory with a functional layer formed by one deposition;

FIG. 1B is a schematic circuit diagram of the memory shown in FIG. 1A;

1C is a schematic diagram of the programming timing of the memory shown in FIG. 1A;

2A is a schematic block diagram of a structure of a nonvolatile memory according to an embodiment of the present invention;

2B is a schematic circuit diagram of a memory string in a non-volatile memory according to an embodiment of the present invention;

3A and 3B are schematic diagrams of programming timing of a nonvolatile memory according to an embodiment of the present invention;

4A is a schematic structural diagram of a nonvolatile memory according to an embodiment of the present invention;

4B is a schematic structural diagram of a nonvolatile memory according to another embodiment of the present invention;

FIG. 5 is an exemplary flowchart of a method for manufacturing a nonvolatile memory according to an embodiment of the present invention;

6A is a schematic diagram of a process of forming a first stack in a method for manufacturing a nonvolatile memory according to an embodiment of the present invention;

6B and 6C are schematic diagrams of a process of forming a first substring in a method for manufacturing a nonvolatile memory according to an embodiment of the present invention;

6D and 6E are schematic diagrams of a process of forming a connection layer in a method for manufacturing a nonvolatile memory according to an embodiment of the present invention;

6F is a schematic diagram of a process of forming a second stack in a method for manufacturing a nonvolatile memory according to an embodiment of the present invention;

7A-7C are schematic diagrams of a process of forming a second substring in a method for manufacturing a nonvolatile memory according to an embodiment of the present invention;

8A-8C are schematic diagrams of a process of forming a second substring in a method for manufacturing a nonvolatile memory according to another embodiment of the present invention.

Detailed ways

In order to make the above objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Numerous specific details are set forth in the following description to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways than those described herein, and thus the present invention is not limited by the specific embodiments disclosed below.

As shown in this application and in the claims, unless the context clearly dictates otherwise, the words "a", "an", "an" and/or "the" are not intended to be specific in the singular and may include the plural. Generally speaking, the terms "comprising" and "comprising" only imply that the clearly identified steps and elements are included, and these steps and elements do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

When describing the embodiments of the present invention in detail, for the convenience of description, the cross-sectional views showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the protection scope of the present invention. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in the actual production.

For convenience of description, spatially relative terms such as "below", "below", "below", "below", "above", "on", etc. may be used herein to describe an element shown in the figures or the relationship of a feature to other elements or features. It will be understood that these spatially relative terms are intended to encompass other directions of the device in use or operation than those depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "below" can encompass both an orientation of above and below. Devices may also have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being 'between' two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, descriptions of structures where a first feature is "on" a second feature can include embodiments in which the first and second features are formed in direct contact, as well as further features formed on the first and second features. Embodiments between the second features such that the first and second features may not be in direct contact.

It will be understood that when an element is referred to as being "on," "connected to," "coupled to," or "contacting" another element, it can be directly between the other element on, connected to or coupled to, or in contact with the other component, or an intervening component may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to," or "directly in contact with" another element, there are no intervening elements present. Likewise, when a first component is referred to as being "in electrical contact" or "electrically coupled to" a second component, there is an electrical path between the first component and the second component that allows current to flow. The electrical path may include capacitors, coupled inductors, and/or other components that allow current to flow, even without direct contact between conductive components.

Flowcharts are used in this application to illustrate operations performed by a manufacturing method according to an embodiment of the present invention. It should be understood that the preceding operations are not necessarily performed in exact order. Rather, the various steps may be processed in reverse order or concurrently. At the same time, other actions are either added to these processes, or a step or steps are removed from these processes.

FIG. 1A is a schematic structural diagram of a 3D NAND memory in which a functional layer is formed after one deposition. Referring to FIG. 1A , the memory is composed of two stack structures, namely, a lower stack 110 and an upper stack 120 . Each stack structure includes a stack of alternately stacked first material layers 141 and second material layers 142 .

The first material layer 141 and the second material layer 142 may be selected from the following materials and include at least one insulating medium, such as silicon nitride, silicon oxide, amorphous carbon, diamond-like amorphous carbon, germanium oxide, aluminum oxide, etc. and its combination. The first material layer 141 and the second material layer 142 have different etch selectivities. For example, it may be a combination of silicon nitride and silicon oxide, a combination of silicon oxide and undoped polysilicon or amorphous silicon, a combination of silicon oxide or silicon nitride and amorphous carbon, and the like. The deposition method of the first material layer 141 and the second material layer 142 of the stack structure may include chemical vapor deposition (CVD, PECVD, LPCVD, HDPCVD), atomic layer deposition (ALD), or physical vapor deposition methods such as molecular beam epitaxy (MBE) ), thermal oxidation, evaporation, sputtering and other methods. One of the first material layer 141 and the second material layer 142 may serve as a gate sacrificial layer, such as a silicon nitride layer. The stack as the gate sacrificial layer can also be other conductive layers, such as metal tungsten, cobalt, nickel and the like. Another material layer that does not serve as the gate sacrificial layer may be a dielectric material such as silicon oxide, such as aluminum oxide, hafnium oxide, tantalum oxide, and the like. In the embodiment of the present invention, the stack structure may be alternately formed of materials serving as gate sacrificial layers and oxide layers, or alternately formed of metal layers and oxide layers.

Channel holes 150 for forming memory cells are also formed in each stack structure. The channel hole 150 may be formed in the stack structure by using a photomask and a corresponding etching process. FIG. 1A is not intended to limit the shape, location and number of channel holes. In fact, a plurality of channel holes may be formed in the stacked structure through the stacked structure.

The upper stack 120 is located above the lower stack 110 , and the two are connected by an oxide layer 130 . The channel holes of the upper stack 120 and the channel holes of the lower stack 110 are aligned with each other, forming new channel holes 150 . Due to the limitation of the process and the high aspect ratio of the channel hole, the channel hole 150 formed in practice is not a cylindrical hole with the same upper and lower diameters, but has a larger upper aperture and a smaller lower aperture. A functional layer is deposited in the channel hole 150 , and the functional layer includes a barrier layer 154 , a charge trapping layer 153 , a tunneling layer 152 and a conductive layer 151 sequentially deposited from the sidewall of the channel hole to the center of the channel hole. Referring to FIG. 1A , the functional layers formed in this way are not uniformly distributed up and down in the channel hole 150 , which will affect the electrical performance of the memory.

FIG. 1B is a schematic circuit diagram of the memory shown in FIG. 1A . Referring to FIG. 1B , the memory circuit includes two memory cell groups, which are a first memory cell group 160 and a second memory cell group 170 respectively. The first memory cell group 160 corresponds to the lower stack 110 in FIG. 1A , and the second memory cell group 170 corresponds to the upper stack 120 in FIG. 1A . Each memory cell group includes a plurality of memory cells (Memory Cell, MC) and a plurality of dummy memory cells (Dummy Memory Cell, DMC). Wherein, the first storage unit group 160 also includes a bottom selector (Bottom Select Transistor, BST) connected to the source (Source), and the second storage unit group 170 also includes an upper selector connected to the drain (Drain). tube (TopSelect Transistor, TST). Dummy memory cells have a similar structure to memory cells, but are not used as memory cells.

Referring to FIG. 1B , the first memory cell group 160 is connected to each other through the drain terminals of the dummy memory cells located at the edges thereof and the source terminals of the dummy memory cells of the second memory cell group 170 located at the edges thereof.

FIG. 1C is a schematic diagram of programming timing of the memory shown in FIG. 1A . Referring to FIG. 1C , during a programming operation, a memory composed of multiple stack structures is the same as a memory with a single stack structure. In this timing diagram, the programming phase of the memory is entered from the point marked by the dotted line. In this programming stage, the programming voltage Vpgm is applied to the gate of the selected memory cell (Selected Memory Cell, SMC), the turn-on voltage Vpass is applied to the gate of the unselected memory cell (UnSelected Memory Cell, USMC), and the dummy memory cell is applied. The dummy memory cell turn-on voltage Vdummy is applied to the gate of the upper selection tube, and the select tube turn-on voltage Von is applied to the upper selection tube. At the same time, the drain terminal, source terminal, lower selection tube and substrate of the memory are kept at low potential.

In the embodiment of the present invention, the low potentials are all 0V. In other embodiments, the low potential can also be other voltage values.

According to the non-volatile memory shown in Figures 1A-1C, the following problems will arise due to the excessively long channel:

(1) The consistency of the functional layer formed by one-time accumulation is poor;

(2) During the programming process, the memory string where the unselected memory cells are located needs programming inhibition, usually by turning off the upper and lower selection transistors of the unselected string, so that the channel of the unselected string is in a floating state, and the channel will be affected by Vpass. A certain potential is coupled with Vpgm, etc., so as to weaken the unselected string programming electric field and realize programming inhibition. In the actual programming process, the channel potential coupled by Vpgm is higher than the channel potential coupled by Vpass, so the channel coupling potential generated by Vpass will pull down the channel coupling potential generated by Vpgm, and the longer the channel, such The stronger the pull-down effect, the worse the programming inhibition effect and the greater the interference caused by programming.

FIG. 2A is a schematic block diagram of the structure of a non-volatile memory according to an embodiment of the present invention. Referring to FIG. 2A , the nonvolatile memory includes a memory cell array 21 and a controller 22 . Wherein, the memory cell array 21 includes a plurality of memory strings. Each memory string includes a first substring and a second substring connected in series, and the first substring and the second substring respectively include a plurality of memory cells. A plurality of memory cells in the memory cell array 21 can pass word lines (WL), string select lines (String Select Line, SSL), ground select lines (Ground Select Line, GSL), common source line (Common Source Line, CSL) etc. are connected to the driver circuit 23, and may be connected to the read/write circuit 24 through a bit line (BL). The controller 22 can control the operations of the drive circuit 23 and the read/write circuit 24 in response to a control signal transmitted from the outside. For example, when performing a read operation on a memory cell, the controller 22 can control the drive circuit 23 so that the voltage required for the read operation is supplied to the word line of the relevant memory cell; the controller 22 can also control the read/write circuit 24 to allow the read/write circuit 24 to read data stored in a particular memory cell.

2B is a schematic circuit diagram of a memory string in a non-volatile memory according to an embodiment of the present invention. Referring to FIG. 2B , the memory string 200 includes a first substring 210 and a second substring 220 connected in series, and the first substring 210 and the second substring 220 respectively include a plurality of memory cells (MCs).

Referring to FIG. 2B , an intermediate string selector (Intermediate String Select Transistor, ISST) is connected between the first substring 210 and the second substring 220 , and the intermediate string selector does not have a storage unit.

In some embodiments, the controller 22 of the non-volatile memory of the present invention is further configured to: during programming, apply a programming voltage to the selected memory cells SMC of each memory string, and apply the first conduction voltage to the unselected memory cells USMC. A turn-on voltage is applied, and a second turn-on voltage is applied to the intermediate string selection transistor ISST, wherein in at least a part of the programming period, the second turn-on voltage is greater than the first turn-on voltage.

According to these embodiments, the channel potential of the unselected memory cells can be increased, and the disturbance of the programming operation to the unselected memory cells can be reduced.

In these embodiments, referring to FIG. 2B , the memory string of the non-volatile memory of the present invention may further include a first string selection transistor SST1 and a second string selection transistor SST2 . The first string selection tube SST1 is connected to one end of the first substring 210 that is not connected to the intermediate string selection tube ISST (the lower end in the figure); the second string selection tube SST2 is connected to the second substring 220 that is not connected to the intermediate string selection tube. One end of the tube ISST connection (the upper end in the figure). The controller is configured to apply an off voltage to the first string selection transistor SST1 and to apply an on voltage to the second string selection transistor SST2 during programming.

In some embodiments, as shown in FIG. 2B , the nonvolatile memory of the present invention may further include a common source terminal CS connected to the first string selection transistor SST1 , and a drain terminal connected to the second string selection transistor. The controller is configured to apply a ground voltage to the common source and a shutdown voltage to the drain during programming.

In the memory cell array, the first string selection transistors in each storage string are connected to the common source terminal, and for NAND type memory, the common source line CSL is formed; the second string selection transistors in each storage string are connected to the common source terminal. Connected to the drain terminal, and then connected to the bit line of the memory through the drain terminal; the gate of each memory cell is connected to the word line of the memory; multiple memory strings can share the same substrate (Substrate).

For a NAND type memory, the gates of the second string selection transistors in different storage strings are connected to each other to form a string selection transistor SST; the gates of the first string selection transistors in different storage strings are connected to each other to form a ground selection transistor GST . The gates of the first string selection transistor and the second string selection transistor of each memory string are respectively connected to the corresponding string selection word lines.

Referring to FIG. 2B , in some embodiments, the memory string of the non-volatile memory of the present invention includes not only a plurality of memory cells, but also a plurality of dummy memory cells DMC. In the actual memory manufacturing process, the reliability of the memory cells formed at the edge of the memory is low, so these memory cells are used as dummy memory cells in use and are not used for actual read and write operations. It will be appreciated that in some embodiments, the non-volatile memory may not have dummy memory cells.

FIG. 2B is not used to limit the number of substrings connected in series in the storage string in the embodiment of the present invention. In some embodiments, a memory string may be formed by connecting more than two substrings in series. In these embodiments, intermediate string selection tubes without memory cells are connected pairwise between the substrings. Correspondingly, the controller is configured to: during programming, apply the programming voltage to the selected memory cells of each memory string, apply the first turn-on voltage to the unselected memory cells, and apply the second turn-on voltage to all the intermediate string selection transistors , wherein during at least a portion of the programming period, the second turn-on voltage is greater than the first turn-on voltage.

The non-volatile memory described above can be a two-dimensional memory or a three-dimensional memory, such as a 3DNAND memory.

3A and 3B are schematic diagrams of programming timing of a non-volatile memory according to an embodiment of the present invention. Referring to Figures 3A and 3B, the programming phase of the memory is entered from the point marked by the dotted line. Usually, before the dotted line mark, is the pre-conduction stage of the memory. In the pre-conduction stage, a pre-conduction voltage is applied to the drain terminal Drain of the memory and the second string selection transistor SST2. In the programming stage, the programming voltage Vpgm is applied to the selected memory cells SMC of each memory string, the first turn-on voltage Vpass is applied to the unselected memory cells USMC, and the second turn-on voltage Vpgm' is applied to the intermediate string selection transistor ISSG, wherein During at least a portion of the programming period, the second turn-on voltage Vpgm' is greater than the first turn-on voltage Vpass. The voltage applied to the memory cell is applied to its gate, and the voltage applied to the string selector is also applied to its gate.

In the embodiment shown in FIG. 3A , the waveform of the second turn-on voltage Vpgm' applied to the middle string selection transistor is the same as the waveform of the programming voltage Vpgm applied to the selected memory cell. In the pre-conduction stage, the voltage on the selected memory cell is at a low level; after entering the programming stage, the programming voltage Vpgm applied to the selected memory cell is stepped up. As shown in FIG. 3A , the programming voltage Vpgm first rises to the first programming voltage value 311 and lasts for a period of time, then rises to the second programming voltage value 312 and continues for a period of time, and then the programming voltage Vpgm directly drops to the same as the pre-on stage , indicating the end of the programming phase for the selected memory cell. It can be understood that what is shown in FIG. 3A is only an example, and is not used to limit the specific waveform and specific voltage value of the programming voltage Vpgm. In other embodiments, the waveform of the programming voltage Vpgm may be a waveform having a plurality of stepped levels, including a plurality of different programming voltage values.

In the embodiment shown in FIG. 3A, the second turn-on voltage Vpgm' has the same waveform as the programming voltage Vpgm. In the pre-conduction stage, the voltage applied to the intermediate string selection transistor is at a low potential; after entering the programming stage, the second turn-on voltage Vpgm' first rises to the first turn-on voltage value 321 for a period of time, and then rises to the first turn-on voltage Vpgm' The second turn-on voltage is 322 and lasts for a period of time; then the second turn-on voltage Vpgm' directly drops to the same low potential level as the pre-turn-on stage.

Specifically, the voltage value of the second turn-on voltage Vpgm' and the voltage value of the programming voltage Vpgm may be the same or different. In some embodiments, the ratio of the voltage value of the second turn-on voltage Vpgm' to the voltage value of the programming voltage Vpgm is between 0.9˜1.1.

In an embodiment not shown, the second turn-on voltage Vpgm' has a waveform similar to or significantly different from the programming voltage Vpgm. In these embodiments, the ratio of the voltage value of the second turn-on voltage Vpgm' to the voltage value of the programming voltage Vpgm may be less than or equal to 1.1.

In the embodiment shown in FIG. 3A , during at least a part of the programming period, the second turn-on voltage Vpgm' applied to the middle string selection transistor is greater than the first turn-on voltage Vpass applied to the unselected memory cells. As shown in FIG. 3A , the first turn-on voltage value 321 may be smaller than the first turn-on voltage Vpass, and the second turn-on voltage value 322 may be greater than the first turn-on voltage Vpass. In this way, at least in this part of the period of the second on-voltage value 322, the second on-voltage Vpgm' is greater than the first on-voltage Vpass. In an embodiment of the present invention, at least a portion of the period may be at least 1/4 of the period of the programming period.

In other embodiments, both the first turn-on voltage value 321 and the second turn-on voltage value 322 may be greater than the first turn-on voltage Vpass, so that the second turn-on voltage Vpgm' is greater than the first turn-on voltage during the entire programming period Pass voltage Vpass.

In the embodiment shown in FIG. 3B , the waveform of the second turn-on voltage Vpgm' applied to the intermediate string selection transistor ISST is different from the waveform of the programming voltage Vpgm applied to the selected memory cell SMC. Referring to FIG. 3B, the difference from FIG. 3A is that after entering the programming stage, the second turn-on voltage Vpgm' rises directly to a fixed turn-on voltage value 330, and lasts for a period of time until the end of the programming stage, The second turn-on voltage Vpgm' directly drops to the same low potential level as the pre-turn-on stage.

In the embodiment shown in FIG. 3B , the fixed turn-on voltage value 330 is greater than the first turn-on voltage Vpass.

FIG. 4A is a schematic structural diagram of a non-volatile memory according to an embodiment of the present invention. Referring to FIG. 4A , the nonvolatile memory of this embodiment includes stacked layers and a memory cell array. The stacked layers include the stacked first stack 410 and the second stack 420 , and the connection layer 430 located between the first stack 410 and the second stack 420 . The first stack 410 and the second stack 420 respectively include alternately stacked gate layers 441 and dielectric layers 442 .

The memory cell array includes a plurality of memory strings, and each memory string includes a first substring 450 and a second substring 460 . Referring to FIG. 4A , the first substring 450 penetrates the first stack 410 , and the second substring 460 penetrates the second stack 420 . A first channel hole 411 and a second channel hole 421 are respectively formed in the first stack 410 and the second stack 420 penetrating the stack structures thereof. Both the first channel hole 411 and the second channel hole 421 are cylindrical holes. 4A is a front cross-sectional view of a nonvolatile memory according to an embodiment of the present invention, showing a front cross-sectional view of a memory string. As can be understood from the perspective of FIG. 4A , the first substrings 450 are formed on the sidewalls of the first channel holes 411 , have a cylindrical ring structure, and do not fill up the spaces in the first channel holes 411 . The second substrings 460 are formed on the sidewalls of the second channel holes 421 , have a cylindrical annular structure, and do not fill up the spaces in the second channel holes 421 .

Referring to FIG. 4A , the first substring 450 includes a first channel layer 451 , the second substring 460 includes a second channel layer 461 , and a channel passes between the first channel layer 451 and the second channel layer 461 The connection portion 431 is electrically connected. The first channel layer 451 is in the innermost ring of the first substring 450, and is adjacent to the space inside the first channel hole 411; the second channel layer 461 is in the innermost ring of the second substring 460, and is adjacent to the second channel hole 411. The voids inside the channel holes 421 are adjacent to each other.

Referring to FIG. 4A , the stacked layers in the non-volatile memory of this embodiment may be formed by alternately stacking gate layers 441 and dielectric layers 442 , and the extension direction of the stacked layers is defined as the extension direction D1 . The stacking direction is defined as the stacking direction D2, and D1 and D2 are perpendicular to each other. The connection layer 430 is distributed along the extending direction D1 and is parallel to the gate layer and the dielectric layer in the first substring 450 and the second substring 460 . In the stacking direction D2, the connection layer 430 is located between the dielectric layer of the first substring 410 and the dielectric layer of the second substring 420, that is, the connection layer 430 is not connected to the gates in the first substring 410 and the second substring 420. Pole layer contact.

The connection layer 430 is opposite to the channel connection parts 431 of the first channel layer 451 and the second channel layer 461 in the extending direction D1 of the stacked layers, and a dielectric layer is formed between the connection layer 430 and the channel connection parts 431 .

In this embodiment, the connection layer 430 and the channel connection portion 431 constitute an intermediate string selection transistor without memory cells, which is the intermediate string selection transistor ISST shown in FIG. 2B and FIGS. 3A and 3B . Since the first channel layer 451 of the first substring 410 is electrically connected to the second channel layer 461 of the second substring 420 through the channel connecting portion 431 , the intermediate string selector is electrically connected to the first substring 420 . Between string 410 and second substring 420.

In some embodiments, referring to FIG. 4A , the first substring 450 further includes a first charge storage layer 452 , the second substring 460 further includes a second charge storage layer 462 , the first charge storage layer 452 and The second charge storage layer 462 does not extend to the region 432 between the connection layer 430 and the channel connection part 431 . The region 432 is a dielectric layer.

The channel connection portion 431 between the first channel layer 451 and the second channel layer 461 in this embodiment is a solid column.

In some embodiments, the first charge storage layer 452 in the first substring 450 includes a first tunneling layer 4521 , a first charge trapping layer 4522 and a first blocking layer 4523 , and the second charge in the second substring 460 The storage layer 462 includes a second tunneling layer 4621 , a second charge trapping layer 4622 and a second blocking layer 4623 . In these embodiments, the first substring 450 is, from the sidewall of the first channel hole 411 to the center, the first blocking layer 4523 , the first charge trapping layer 4522 , the first tunneling layer 4521 and the first channel layer in order. 451; the second substring 460 is a second blocking layer 4623, a second charge trapping layer 4622, a second tunneling layer 4621 and a second channel layer 461 in order from the sidewall of the second channel hole 421 to the center.

In embodiments of the present invention, exemplary materials for the blocking layer and the tunneling layer are silicon oxide, silicon oxynitride or a mixture of the two, and exemplary materials for the charge trapping layer are silicon nitride or silicon nitride and silicon oxynitride multi-layer structure. The blocking layer, charge trapping layer, tunneling layer may form, for example, a multi-layer structure with silicon oxynitride-silicon nitride-silicon oxide (SiON/SiN/SiO); an exemplary material for the channel layer is polysilicon. It is understood, however, that other materials may be selected for these layers. For example, the material of the barrier layer may include a high-K (dielectric constant) oxide layer; the material of the channel layer may include semiconductor materials such as single crystal silicon, single crystal germanium, SiGe, Si:C, SiGe:C, SiGe:H, etc.

Referring to FIG. 4A , the voids inside the first channel holes 411 and the voids inside the second channel holes 421 of the non-volatile memory according to the embodiment of the present invention are also filled with insulating materials, which are used for insulation and support. effect. The insulating material may be the same material as the second material layer 442 or a different material. The insulating material may be an oxide.

In some embodiments, the non-volatile memory shown in FIG. 4A further includes a controller configured to apply a programming voltage to selected memory cells of each memory string and a turn-on voltage to non-selected memory cells during programming , and a second turn-on voltage is applied to the middle string selection transistor, wherein in at least a part of the programming period, the second turn-on voltage is greater than the turn-on voltage. The voltage value of the second turn-on voltage Vpgm' and the voltage value of the programming voltage Vpgm may be the same or different.

In some embodiments, the ratio of the voltage value of the second turn-on voltage Vpgm' to the voltage value of the programming voltage Vpgm is between 0.9˜1.1.

In other embodiments, the ratio of the voltage value of the second turn-on voltage Vpgm' to the voltage value of the programming voltage Vpgm is less than or equal to 1.1.

For a description of the controller and its operation during programming reference may be made to the foregoing descriptions corresponding to Figures 2A, 2B, 3A and 3B.

It should be noted that the stacked layers, storage strings, first substrings, second substrings, etc. included in the embodiments of the present invention are distributed symmetrically around the central axis of the channel hole. Only a part of the structure is marked, and the description of the partial structure is applicable to the unmarked partial structure distributed symmetrically with it.

FIG. 4A is not used to limit the number of stacks and substrings in the embodiment of the present invention. In some embodiments, the non-volatile memory of the present invention may be formed by stacking more than two multiple stacks. In these embodiments, a substring is formed in each stack, and the connection layers and channel connections are formed between a plurality of adjacent substrings. Correspondingly, the controller is configured to: during programming, apply the programming voltage to the selected memory cells of each memory string, apply the first turn-on voltage to the unselected memory cells, and apply the second turn-on voltage to all the intermediate string selection transistors , wherein during at least a portion of the programming period, the second turn-on voltage is greater than the first turn-on voltage.

FIG. 4B is a schematic structural diagram of a nonvolatile memory according to another embodiment of the present invention. Referring to FIG. 4B , the difference between this embodiment and FIG. 4A is that the channel connection portion 431 between the first channel layer 451 and the second channel layer 461 in this embodiment is a hollow column.

Referring to FIGS. 4A and 4B , regardless of whether the channel connection portion 431 is a solid column or a hollow column, the channel connection portion 431 and the connection layer 430 constitute an intermediate string selection transistor without memory cells. In this way, when programming the non-volatile memory, a higher second turn-on voltage Vpgm' is applied to the middle string selection transistor, which can increase the channel potential of the non-selected memory cells and reduce the channel potential and the Turn on the potential difference between the voltages Vpass, thereby reducing the disturbance of the programming operation to the unselected memory cells.

FIG. 5 is an exemplary flowchart of a method for manufacturing a nonvolatile memory according to an embodiment of the present invention. 5 and 6A-8C, the manufacturing method of this embodiment includes the following steps:

Step 510, forming a first stack.

6A is a schematic diagram of a process of forming a first stack in a method for manufacturing a nonvolatile memory according to an embodiment of the present invention. Referring to FIG. 6A , the first stack 610 formed in step 510 includes alternately stacked first material layers 641 and second material layers 642 .

In some embodiments, the first material layer 641 and the second material layer 642 may be selected from the following materials and include at least one insulating medium, such as silicon nitride, silicon oxide, amorphous carbon, diamond-like amorphous carbon, oxide Germanium, alumina, etc. and combinations thereof. The first material layer 641 and the second material layer 642 have different etch selectivities. For example, it may be a combination of silicon nitride and silicon oxide, a combination of silicon oxide and undoped polysilicon or amorphous silicon, a combination of silicon oxide or silicon nitride and amorphous carbon, and the like. The deposition method of the first material layer 641 and the second material layer 642 of the first stack 610 may include chemical vapor deposition (CVD, PECVD, LPCVD, HDPCVD), atomic layer deposition (ALD), or physical vapor deposition methods such as molecular beam epitaxy (MBE), thermal oxidation, evaporation, sputtering, and other methods. One of the first material layer 641 and the second material layer 642 may serve as a gate sacrificial layer, such as a silicon nitride layer. The stack as the gate sacrificial layer can also be other conductive layers, such as metal tungsten, cobalt, nickel and the like. Another material layer that does not serve as the gate sacrificial layer may be a dielectric material such as silicon oxide, such as aluminum oxide, hafnium oxide, tantalum oxide, and the like.

In the embodiment of the present invention, the first material layer 641 is a dummy gate layer, and the second material layer 642 is a dielectric layer.

Step 520, forming a first substring vertically penetrating the first stack.

6B and 6C are schematic diagrams of a process of forming a first substring in a method for manufacturing a nonvolatile memory according to an embodiment of the present invention. Referring to FIG. 6B , first channel holes 611 are formed by etching in the first stack 610 . Referring to FIG. 6C , a first substring 650 is deposited in the first channel hole 611 . In this embodiment, the first substring 650 includes a first channel layer 651 . The first channel layer 651 may be a conductive material, such as polysilicon.

It can be understood that FIG. 6C is a front cross-sectional view of the non-volatile memory according to an embodiment of the present invention, showing a front cross-sectional view of the first substring. It can be understood from the perspective of FIG. 6C that the first substring 650 should have a ring-shaped structure and not fill the space in the first channel hole 611 . The first channel layer 651 is in the innermost ring of the first substring 650 and is adjacent to the space inside the first channel hole 611 .

In some embodiments, the first substring 650 also includes a first charge storage layer 652 .

In some embodiments, the first charge storage layer 652 in the first substring 650 includes a first tunneling layer 6521 , a first charge trapping layer 6522 and a first blocking layer 6523 . In these embodiments, the first barrier layer 6523, the first charge trapping layer 6522, the first tunneling layer 6521 and the first channel layer 651 are sequentially deposited on the sidewall of the first channel hole 611 toward the center to form The first substring 650.

Referring to FIG. 6C , at the top of the first stack 610 is a second material layer 642 serving as a dielectric layer.

Step 530, forming a connection layer on the first stack.

6D and 6E are schematic diagrams of a process of forming a connection layer in a method for manufacturing a nonvolatile memory according to an embodiment of the present invention. Referring to FIG. 6D , firstly, oxide is filled in the space of the first channel hole 611 , and the oxide material may be the same or different material as that of the second material layer 642 . A connecting layer 630 is then formed on the first stack 610 . Since the top of the first stack 610 is the second material layer 642 , the connection layer 630 is formed on the second material layer 642 on the top. The connection layer 630 can be made of the same or different material as the first material layer 641 . The process of forming the connection layer 630 may be formed by a process similar to the deposition of the first material layer 641 and the second material layer 642 .

Referring to FIG. 6D , in some embodiments, after the connection layer 630 is formed, a second material layer 642 may also be formed on the connection layer 630 .

In the manufacturing method of the embodiment of the present invention, after filling the first channel hole 611 or forming the connection layer 630, and in some other processes, the step of planarizing some surfaces may also be included.

Referring to FIG. 6E , the channel connection part 631 contacting the first channel layer 651 is formed. The channel connecting portion 631 is located above the first channel hole 611 , and its size can cover the maximum diameter of the first channel hole 611 . On the basis of the structure shown in FIG. 6D , the connection layer and the two second material layers 642 located above and below it may be etched and deposited through a mask to form the channel connection portion 631 .

The material of the channel connection part 631 may be the same or different conductive material as that of the first channel layer 651 .

Referring to FIG. 6E , the channel connection portion 631 formed in this step may also be in contact with the connection layer 630 .

In step 540, a second stack is formed on the connection layer.

6F is a schematic diagram of a process of forming a second stack in a method for manufacturing a nonvolatile memory according to an embodiment of the present invention. Referring to FIG. 6F, on the structure shown in FIG. 6E, a second stack 620 is formed. Similar to the first stack 610 , the second stack 620 includes alternately stacked first material layers 641 and second material layers 642 . The description about the first material layer 641 and the second material layer 642 may refer to the description about the first stack 610 .

A method of forming the second stack 620 may be to alternately deposit first material layers 641 and second material layers 642 layer by layer over the first stack 610 .

Referring to FIG. 6F , the bottommost first material layer 641 of the second stack 620 is in contact with the channel connection portion 631 in the first stack 610 and is in contact with the second material layer 642 above the connection layer 630 .

Step 550, forming a second substring vertically penetrating the second stack.

The nonvolatile memory obtained by the method for manufacturing the nonvolatile memory of the present invention is shown in FIGS. 4A and 4B . Corresponding to the two non-volatile memory embodiments shown in FIGS. 4A and 4B , the manufacturing methods of the non-volatile memories in this step are slightly different. Step 550 will be described in two embodiments below.

Corresponding to the embodiment of the non-volatile memory shown in Figure 4A:

7A-7C are schematic diagrams illustrating a process of forming a second substring in a method for manufacturing a nonvolatile memory according to an embodiment of the present invention. Referring to FIG. 7A , a second substring 660 is formed in the second stack 620 throughout the second stack 620 . Similar to the method for forming the first substrings 650 , firstly, the second channel holes 621 need to be formed by etching in the second stack 620 ; then the second substrings 660 may be deposited in the second channel holes 621 . In this embodiment, the second substring 660 includes a second channel layer 661 . The second channel layer 661 may be a conductive material. The second substrings 660 should have a ring-shaped structure and not fill up the spaces in the second channel holes 621 . The second channel layer 661 is in the innermost ring of the second substring 660 and is adjacent to the space inside the second channel hole 621 .

In some embodiments, as shown in FIG. 7A , the second channel layer 661 is in contact with the channel connection 631 . Since the first channel layer 651 is also in contact with the channel connection part 631 , and the first channel layer 651 , the second channel layer 661 and the channel connection part 631 can all be conductive materials, the three can be electrically connected.

In some embodiments, the second substring 660 also includes a second charge storage layer 662 . The first charge storage layer 652 and the second charge storage layer 662 are separated by the channel connection portion 631 .

In some embodiments, the second charge storage layer 662 in the second substring 660 includes a second tunneling layer 6621 , a second charge trapping layer 6622 and a second blocking layer 6623 . In these embodiments, the second barrier layer 6623 , the second charge trapping layer 6622 , the second tunneling layer 6621 and the second channel layer 661 are sequentially deposited on the sidewall of the second channel hole 621 toward the center to form Second substring 660 .

Referring to FIG. 7B , an insulating material is filled in the second channel hole 621 . The insulating material may be the same material as the second material layer 642 or a different material. In the process shown in FIG. 7B , the first material layer 641 serving as the dummy gate layer is also etched away. It should be noted that, in the previous steps, the connection layer 630 may also be the first material layer 641 serving as the dummy gate layer. Therefore, in this process, the first material layer 641 in the stacked structure of the first stack 610 and the second stack 620 and the first material layer 641 in the connection layer 630 are etched away together.

In the process shown in FIG. 7B, an oxidized portion of the channel connection 631 is also included. 7A and 7B, the part of the channel connection part 631 in contact with the connection layer 630 is oxidized, so that the first charge storage layer 652 and the second charge storage layer 662 do not extend to the connection layer 630 and the channel connection part. Area 632 between 631. That is, the first charge storage layer 652 in the first substring 650 and the second charge storage layer 662 in the second substring 660 are not electrically connected.

Further, in some embodiments, the first charge trapping layer 6522 and the first tunneling layer 6521 in the first substring 650 and the second charge trapping layer 6622 and the second tunneling layer in the second substring 660 Neither 6621 extends to the region 632 between the connection layer 630 and the channel connection 631 .

Referring to FIG. 7C , conductive material is deposited on the portions of the first material layer 641 and the connection layer 630 that are etched away in the process of FIG. 7B . The gate layer of the non-volatile memory is formed after the conductive material is deposited on the first material layer 641 indicated in FIG. 7C .

FIG. 7C shows a nonvolatile memory obtained by a method for manufacturing a nonvolatile memory according to an embodiment of the present invention. This nonvolatile memory is the same as the nonvolatile memory shown in FIG. 4A. The channel connecting portion 631 thereof is in the shape of a solid column.

For the embodiment of the non-volatile memory shown in FIG. 4B, it can be fabricated as follows.

8A-8C are schematic diagrams of a process of forming a second substring in a method for manufacturing a nonvolatile memory according to another embodiment of the present invention. The process shown in FIG. 8A is similar to the process shown in FIG. 7A , the difference is that when the second channel hole 621 is formed by etching in the second stack 620 , the channel connection part 631 is also etched, The channel connection portion 631 has a hollow columnar structure. As shown in FIG. 8A , the etching of the channel connection 631 exposes the oxide filled in the first channel hole 611 of the first stack 610 .

The process of depositing the second substrings 660 in the second channel holes 621 is also the same as that in FIG. 7A , and related descriptions can be referred to.

Referring to FIG. 8B , oxide is filled in the second channel hole 621 , and oxide is also filled in the hollow portion of the channel connection portion 631 . The oxide in the first channel hole 611 is integrated with the hollow portion of the channel connection portion 631 and the oxide in the second channel hole 621 . In the process shown in FIG. 8B , the process of etching the first material layer 641 and the connection layer 630 as the dummy gate layer, and the process of oxidizing the part of the channel connection part 631 , are the same as those shown in FIG. 7B , and can Refer to the relevant instructions.

Referring to FIG. 8C , the nonvolatile memory obtained by the manufacturing method of the nonvolatile memory according to the embodiment of the present invention is the same as the nonvolatile memory shown in FIG. 4B . The channel connecting portion 631 in FIG. 8C has a hollow columnar shape.

In other embodiments, the above-described fabrication method may be applicable to the fabrication of a non-volatile memory having more than two stacked stacks.

According to the method of fabricating a non-volatile memory according to an embodiment of the present invention, the first substring 650 in the first stack 610 and the second substring 660 in the second stack 620 are formed, respectively, instead of a one-time pad after stacking The first substring 650 and the second substring 660 are formed by product, which improves the uniformity and consistency of the functional layer and the conductive channel layer.

Although the present invention has been described with reference to the present specific embodiments, those of ordinary skill in the art will recognize that the above embodiments are only used to illustrate the present invention, and can be made without departing from the spirit of the present invention Various equivalent changes or substitutions, therefore, as long as the changes and modifications to the above-mentioned embodiments within the spirit and scope of the present invention will fall within the scope of the claims of the present application.

Claims (12)

1. A non-volatile memory, comprising:

the stacked layer comprises a first stacked layer and a second stacked layer which are stacked and a connecting layer positioned between the first stacked layer and the second stacked layer, and the first stacked layer and the second stacked layer respectively comprise gate layers and dielectric layers which are stacked alternately; and

the storage unit array comprises a plurality of storage strings, each storage string comprises a first substring and a second substring, the first substring vertically penetrates through the first stack, the second substring vertically penetrates through the second stack, the first substring comprises a first channel layer, the second substring comprises a second channel layer, and the first channel layer is electrically connected with the second channel layer;

the connection layer is opposite to the channel connection portions of the first channel layer and the second channel layer in the extension direction of the stacked layer, and a dielectric layer is arranged between the connection layer and the channel connection portions.

2. The non-volatile memory of claim 1, wherein the first sub-string includes a first charge storage layer and the second sub-string includes a second charge storage layer, wherein the first charge storage layer and the second charge storage layer do not extend to a region between the connection layer and the channel connection.

3. The nonvolatile memory according to claim 1, wherein a channel connection portion of the first channel layer and the second channel layer is a hollow pillar shape or a solid pillar shape.

4. The non-volatile memory as claimed in claim 1, wherein the connection layer and the channel connection constitute an intermediate string selection pipe without memory cells, electrically connected between the first sub-string and the second sub-string.

5. The non-volatile memory of claim 4, further comprising a controller configured to: during programming, a programming voltage is applied to selected memory cells of each memory string, a first turn-on voltage is applied to unselected memory cells, and a second turn-on voltage is applied to the intermediate string select transistor, wherein the second turn-on voltage is greater than the first turn-on voltage for at least a portion of the period during the programming.

6. The nonvolatile memory of claim 5, wherein the waveform of the second turn-on voltage is the same as the waveform of the programming voltage, and a ratio of the second turn-on voltage to the programming voltage is between 0.9 and 1.1.

7. The non-volatile memory of claim 5, wherein the second turn-on voltage has a waveform that is the same as the first turn-on voltage, and wherein the second turn-on voltage and the programming voltage are less than or equal to 1.1.

8. A method of manufacturing a non-volatile memory device, comprising the steps of:

forming a first stack comprising first and second material layers stacked alternately;

forming a first sub-string vertically penetrating the first stack, the first sub-string including a first channel layer;

forming a connection layer on the first stack;

forming a second stack on the connection layer, the second stack comprising first material layers and second material layers stacked alternately; and

forming a second substring vertically penetrating through the second stack, the second substring including a second channel layer, the first channel layer being electrically connected to the second channel layer, wherein a channel connection portion of the first channel layer and the second channel layer is opposite to the connection layer in an extending direction of the stacked layers, and a dielectric layer is between the channel connection portion and the connection layer;

the first material layer is a gate layer or a dummy gate layer, and the second material layer is a dielectric layer.

9. The method of claim 8, wherein the first substring further comprises a first charge storage layer, the second substring further comprises a second charge storage layer, wherein the first charge storage layer and the second charge storage layer do not extend to a region between the connection layer and the channel connection.

10. The method of claim 8, further comprising, after forming a connection layer on the first stack, forming a channel connection contacting the first channel layer; and when the second substring is formed, the second channel layer contacts the channel connecting part.

11. The method of claim 10, wherein the channel connection is a hollow cylinder or a solid cylinder.

12. The method of claim 8, wherein the connection layer and the channel connection constitute an intermediate string selection pipe without memory cells, electrically connected between the first sub-string and the second sub-string.

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