CN111402737A - Display panel - Google Patents
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- CN111402737A CN111402737A CN202010224615.8A CN202010224615A CN111402737A CN 111402737 A CN111402737 A CN 111402737A CN 202010224615 A CN202010224615 A CN 202010224615A CN 111402737 A CN111402737 A CN 111402737A
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- 239000002184 metal Substances 0.000 claims abstract description 185
- 239000011810 insulating material Substances 0.000 claims description 5
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- 239000003990 capacitor Substances 0.000 description 10
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- 239000003989 dielectric material Substances 0.000 description 3
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
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Abstract
The invention provides a display panel, which solves the problem of alternate row brightness caused by load difference generated by adopting different-layer wiring for source data lines of a fan-out area of the conventional display panel. The display panel includes: the driving chip comprises a plurality of first pins for outputting first signals and a plurality of second pins for outputting second signals; the first metal leads are respectively and correspondingly electrically connected with the first pins one by one; the plurality of second metal leads are respectively and correspondingly electrically connected with the second pins one by one; and a third conductive layer disposed at one side of the first and second metal leads; wherein a distance from the second metal lead to the third conductive layer is shorter than a distance from the first metal lead to the third conductive layer, a line width w of the second metal lead2Is smaller than the line width w of the first metal lead1. By reducing the line width of the second metal lead, the load difference between source data lines is reduced, and the row spacing brightness risk of the display panel is reduced.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel.
Background
At present, a display panel designed by a narrow frame is easier to realize a comprehensive screen design, can bring better user experience, and is more and more concerned by consumers. The frame narrowing puts higher requirements on the lower frame wiring of the display panel. Because the display panel is easily limited by the distance when the same-layer wiring is adopted, the space is saved by adopting the wiring of different layers compared with the wiring of the same layer. However, when the source data lines (source lines) of the fan-out area of the display panel adopt different-layer wiring, the voltages written into the pixel data lines (data lines) are different, so that the display panel has the phenomenon of alternate-column lighting. With the requirement of higher refreshing frequency and resolution of the display panel, the data writing time is further shortened, the alternate row brightness problem is more serious, and the display effect of the display panel is seriously influenced.
Disclosure of Invention
In view of this, embodiments of the present invention are directed to provide a display panel, which aims to solve the problem that the alternate columns are bright due to the difference between voltages written into the pixel data lines caused by different layer wirings adopted in the source data lines of the fan-out area of the conventional display panel on the premise of ensuring the narrow frame design of the display panel.
An embodiment of the present invention provides a display panel, including: the driving chip comprises a plurality of first pins for outputting first signals and a plurality of second pins for outputting second signals; the first metal leads are respectively and correspondingly electrically connected with the first pins one by one; the plurality of second metal leads are respectively and correspondingly electrically connected with the second pins one by one; a third conductive layer disposed at one side of the first metal lead and the second metal lead; wherein a distance from the second metal lead to the third conductive layer is shorter than a distance from the first metal lead to the third conductive layer, a line width w of the second metal lead2Is smaller than the line width w of the first metal lead1。
In one embodiment, the display panel further comprises a first dielectric layer disposed between the first metal lead and the second metal lead; and the second dielectric layer is arranged between the second metal lead and the third conducting layer.
In one embodiment, the first dielectric layer and the second dielectric layer are made of the same insulating material; the thickness of the first dielectric layer is d1The thickness of the second dielectric layer is d2(ii) a The line width w of the first metal lead1And the line width w of the second metal lead2The following conditions are satisfied: w is a1:w2＝(d1+d2):d2。
In one embodiment, the first dielectric layer and the second dielectric layer are equal in thickness; the first dielectric layer has a dielectric constant of1The dielectric constant of the second dielectric layer is2(ii) a The line width w of the first metal lead1And the line width w of the second metal lead2The following conditions are satisfied: w is a1:w2＝(1+2):1。
In one embodiment, the first dielectric layer: thickness d1A dielectric constant of1(ii) a The second medium layer: thickness d2A dielectric constant of2(ii) a The line width w of the first metal lead1And the line width w of the second metal lead2The following conditions are satisfied: w is a1:w2＝(1*d2+2*d1):(1*d2)。
In one embodiment, the length of the second metal lead is less than the length of the first metal lead.
In one embodiment, the first metal lead is connected to odd-numbered column pixel data lines, and the second metal lead is connected to even-numbered column pixel data lines.
In one embodiment, the first metal leads and the second metal leads are symmetrically arranged along a longitudinal axis direction of the driving chip, a distance between two adjacent first metal leads is equal, and a distance between two adjacent second metal leads is equal.
In one embodiment, the third metal layer includes a power supply signal region connected to a pixel driving power supply.
In one embodiment, the first metal lead under the power signal region is parallel to a projection of the second metal lead on a substrate layer.
According to the display panel provided by the embodiment of the invention, the first metal lead wire, the second metal lead wire and the upper conducting layer form the same capacitance basically by reducing the line width of the second metal lead wire. On the premise of narrow frame design, the load difference between source data lines is reduced, the voltages written into the pixel data lines are equal, the brightness consistency of the display panel is ensured, and the lighting risk of alternate columns is reduced.
Drawings
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the invention.
FIG. 2 is a cross-sectional view of a different-layer layout of source data lines of a display panel according to an embodiment of the invention.
FIG. 3 is a cross-sectional view of a different-layer wiring of a source data line of a display panel according to the prior art.
Fig. 4 is a schematic diagram illustrating a signal variation of a source data line of a display panel in the prior art.
Fig. 5 is a schematic diagram illustrating signal variations of source data lines of a display panel according to an embodiment of the invention.
FIG. 6 is a schematic diagram illustrating a positional relationship between source data lines and a third conductive layer of a display panel according to another embodiment of the present invention.
Fig. 7 is a schematic structural diagram of a display panel according to another embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the invention. FIG. 2 is a cross-sectional view of a different-layer layout of source data lines of a display panel according to an embodiment of the invention. As shown in fig. 1 and 2, the driver chip 1 includes a plurality of first pins 11 outputting a first signal and a plurality of second pins 12 outputting a second signal; multiple purposeThe first metal leads 2 are respectively and correspondingly electrically connected with the first pins 11 one by one; the second metal leads 3 are respectively and correspondingly electrically connected with the second pins 12 one by one; a third conductive layer 4 disposed at one side of the first metal lead 2 and the second metal lead 3; wherein the distance from the second metal lead 3 to the third conductive layer 4 is shorter than the distance from the first metal lead 2 to the third conductive layer 4, and the line width w of the second metal lead 32Is smaller than the line width w of the first metal lead 21。
Specifically, the first metal lead 2 shown in fig. 1 is a source data line source1, the second metal lead 3 is a source data line source2, and the driving chip 1 provides signals to corresponding pixel data lines (data lines) through the first metal lead 2 and the second metal lead 3. It should be understood that the first signal and the second signal are signals output by different pins of the driving chip 1, and the content of the first signal may be the same as or different from that of the second signal, which is not limited in the present invention. However, it should be understood that the metal leads and the driving chip 1 may be thermally and thermally bonded, ultrasonically bonded, or thermosonic bonded or other connection techniques, and the present invention is not limited to the specific connection manner between the first metal leads 2 and the second metal leads 3 and the leads of the driving chip 1. It should be noted that the specific number of the first metal leads 2 and the second metal leads 3 may be determined according to the specific function of the display panel, and the specific number of the first metal leads 2 and the second metal leads 3 is not limited in the embodiment of the present invention. The third conductive layer 4 is disposed on one side of the first metal lead 2 and the second metal lead 3, as shown in fig. 2, which means above the first metal lead 2 and the second metal lead 3. The third conductive layer 4 can be used for wiring layers of other metal leads to reduce the width of a fan-out area of the display panel and realize a narrow frame design.
The inventor of the present application found in the research and development process that one of the main reasons that the conventional display panel is prone to the poor column-to-column bright display is that when the source data line is formed by the different-layer wiring as shown in fig. 3, the delay (delay) of the first signal is different from the delay of the second signal. As shown in FIG. 3, a first metal lead 2' connected to a first signal is provided in the same layer, and a second metal lead 3 connected to a second signal is providedThe first metal lead 2' and the second metal lead 3' are arranged in the same layer, the line widths of the first metal lead 2' and the second metal lead 3' are equal, two layers of dielectric exist between the first metal lead 2' of the first signal and the metal layer above the first metal lead, and only one layer of dielectric exists between the second metal lead 3' of the second signal and the metal layer 4' above the second metal lead, so that the distances between the first metal lead 2' and the second metal lead 3' and the metal layer above the second metal lead are different, and therefore the capacitances formed by the first metal lead and the second metal lead are different. Resulting in a difference in the loading of source data line source1 and source2, i.e., different signal delays. The signal variation of the source line corresponding to the gray level is shown in FIG. 4, i.e. the source data line voltage V at low gray leveldataWhen the brightness is high, the source2 signal is large in delay, so that the source2 cannot fill the target voltage, and the pixel brightness of the corresponding pixel data line data2 is high; in contrast, the voltage of the source2 is higher at the high gray level, which results in the lower brightness of the pixel corresponding to the pixel data line data2, but the bright phenomenon of the display panel at intervals occurs because human eyes are not sensitive to brightness at the high gray level and are sensitive to brightness at the low gray level.
In view of this, the embodiment of the invention reduces the load difference between the source data lines by reducing the line width of the second metal wire 3. Specifically, as shown in fig. 2, a first metal lead 2 connected to a first signal is located at a first metal layer; the second metal lead 3 connecting the second signal is located at the second metal layer. Wherein a dielectric layer is present between the first metal layer and the second metal layer, and a dielectric layer is present between the second metal layer and the third conductive layer 4. Fig. 5 shows a schematic diagram of signal changes of the source data line of the display panel provided in the above embodiment, in which the line width of the second metal lead 3 is reduced, which is equivalent to reducing the area values corresponding to the second metal lead 3 and the third conductive layer 4, and the capacitance formed therebetween is reduced accordingly. Therefore, the capacitance difference generated by the first metal lead 2 and the second metal lead 3 due to different distances from the third conductive layer 4 is compensated, and the capacitance difference formed by the first metal lead 2, the second metal lead 3 and the third conductive layer 4 is reduced. It should be noted that, although the capacitance difference and the resistance difference both affect the load, the influence of the resistance difference on the load is small, and the influence of the resistance change caused by the reduction of the line width of the second metal wire 3 on the load is also small, so it is preferable to reduce the capacitance difference formed by the first metal wire 2, the second metal wire 3, and the third conductive layer 4. In addition, in an embodiment of the present invention, the resistance difference caused by the line width reduction of the second metal wire 3 can be compensated by setting the length of the second metal wire 3 to be smaller than the length of the first metal wire 2, so as to further ensure the load difference between the source data lines. As described above, the above design reduces the load difference between the source data lines, so that the delay of the source data line source1 is substantially equal to the delay of the source2, the voltages written to the source data lines source1 and source2 are equal, and the uniformity of the brightness of the display panel is ensured.
According to the display panel provided by the embodiment of the invention, the line width of the second metal lead 3 is reduced, so that the capacitances formed by the first metal lead 2, the second metal lead 3 and the third conductive layer 4 are basically equal, and on the premise of a narrow frame design, the load difference between source data lines is reduced, and further the row spacing brightness risk of the display panel is reduced.
In an embodiment of the present invention, the display panel further includes a first dielectric layer B disposed between the first metal lead 2 and the second metal lead 3; and a second dielectric layer C arranged between the second metal lead 3 and the third conductive layer 4.
Specifically, as shown in fig. 6, the first metal lead 2 and the third conductive layer 4 form a capacitor C1The second metal lead 3 and the third conductive layer 4 form a capacitor C2. Although two layers of dielectrics B and C are filled between the first metal lead 2 and the third conductive layer 4, and only one layer of dielectric C is filled between the second metal lead 3 and the third conductive layer 4, the line width of the second metal lead 3 is reduced, the area value corresponding to the second metal lead 3 and the third conductive layer 4 is reduced, and the capacitor C can be formed1And a capacitor C2The values are substantially equal. The design can reduce the load difference between the source data lines, so that the voltages written into the source data lines source1 and source2 are equal, the pixel brightness of the corresponding pixel data lines is equal, and the alternate brightness risk of the display panel is reduced.
In an embodiment of the present invention, the first dielectric layer B and the second dielectric layer C are made of the same insulating material; the thickness of the first dielectric layer B isd1The thickness of the second dielectric layer C is d2(ii) a Line width w of first metal lead 21And the line width w of the second metal lead 32The following conditions are satisfied: w is a1:w2＝(d1+d2):d2。
Specifically, the equation for the calculation of the parallel plate capacitor is expressed as C ═ S)/d, where the dielectric constant of the inter-plate dielectric is defined as S, the plate area and the distance between the plates, in the present embodiment, the upper plate is defined as the third conductive layer 4, the lower plate is defined as the first metal lead 2 and the second metal lead 3, and the corresponding plate area S is defined as the product of the length and the width of the metal lead, since the first dielectric layer B and the second dielectric layer C are made of the same insulating material, the dielectric constant of the inter-plate dielectric is equal, and the length L of the first metal lead 2 and the second metal lead 3 under the third conductive layer 4 is equal, so that the capacitance C is equal to the length L of the second metal lead 3 under the third conductive layer 41And a capacitor C2Equal in value, i.e., (. w)1*L)/(d1+d2)＝(*w2*L)/d2Need to satisfy w1:w2＝(d1+d2):d2。
In the display panel provided by the embodiment of the invention, in the product design process, the first dielectric layer B and the second dielectric layer C are set to be made of the same insulating material; the thickness of the first dielectric layer B is d1The thickness of the second dielectric layer C is d2In this case, only the line width w of the first metal lead 2 is required to be set1And the line width w of the second metal lead 32The following conditions are satisfied: w is a1:w2＝(d1+d2):d2The method can accurately ensure that the signal delay on the source data line is basically the same, and can effectively ensure the display effect of the display panel on the basis of narrow frame design and reduction of the row spacing brightness risk.
In an embodiment of the present invention, the thicknesses of the first dielectric layer B and the second dielectric layer C are equal; the first dielectric layer B has a dielectric constant of1The dielectric constant of the second dielectric layer C is2(ii) a Line width w of first metal lead 21And the line width w of the second metal lead 32The following conditions are satisfied: w is a1:w2＝(1+2):1。
Specifically, in the embodiment of the present invention, since the thicknesses of the first dielectric layer B and the second dielectric layer C are equal, and the types of the filling dielectrics are different, the capacitor C should be made1And a capacitor C2The values are equal, i.e., (w)1*L)/(d1/1+d2/2)＝(w2*L)/(d2/2) Need to satisfy w1:w2＝(1+2):1。
In the display panel provided by the embodiment of the invention, in the product design process, the thicknesses of the first dielectric layer B and the second dielectric layer C are set to be equal, and when the first dielectric layer B and the second dielectric layer C are different; measuring the dielectric constant of the first dielectric layer B1Dielectric constant of the second dielectric layer C2Only the line width w of the first metal lead 2 needs to be set1And the line width w of the second metal lead 32The following conditions are satisfied: w is a1:w2＝(1+2):1The method can accurately ensure that the signal delay on the source data line is basically the same, and can effectively ensure the display effect of the display panel on the basis of narrow frame design and reduction of the row spacing brightness risk.
In one embodiment of the present invention, the first dielectric layer B: thickness d1A dielectric constant of1(ii) a Second dielectric layer C: thickness d2A dielectric constant of2(ii) a Line width w of first metal lead 21And the line width w of the second metal lead 32The following conditions are satisfied: w is a1:w2＝(1*d2+2*d1):(1*d2)。
Specifically, in the embodiment of the present invention, the thicknesses of the first dielectric layer B and the second dielectric layer C are not equal, and the types of the filling dielectrics are different, so that the capacitor C needs to be formed1And a capacitor C2The values are equal, i.e., (w)1*L)/(d1/1+d2/2)＝(w2*L)/(d2/2) Need to satisfy w1:w2＝(1*d2+2*d1):(1*d2)。
In the display panel provided by the embodiment of the invention, in the product design process, the thicknesses of the first dielectric layer B and the second dielectric layer C are set to be unequal, and the thickness d of the first dielectric layer B is respectively measured when the types of the filling media are different1Thickness d of the second dielectric layer C2(ii) a Respectively measuring the dielectric constants of the first dielectric layers B1Dielectric constant of the second dielectric layer C2Only the line width w of the first metal lead 2 needs to be set1And the line width w of the second metal lead 32The following conditions are satisfied: w is a1:w2＝(1+2):1The method can accurately ensure that the signal delay on the source data line is basically the same, and can effectively ensure the display effect of the display panel on the basis of narrow frame design and reduction of the row spacing brightness risk.
In an embodiment of the present invention, the length of the first metal lead 2 is smaller than the length of the second metal lead 3. The different lengths of the metal leads can reduce the resistance difference among the different metal leads, thereby ensuring the consistency of the signal transmission process. It should be understood that the position of the pins of the driving chip 1 may be adjusted, and the position of the contact holes or the transparent electrodes connecting the metal leads and the pixel data lines may also be adjusted, and the embodiment of the present invention is not particularly limited to the implementation of the metal leads with different lengths.
According to the display panel provided by the embodiment of the invention, the length of the first metal lead 2 is smaller than that of the second metal lead 3, so that the display effect of the display panel is further ensured on the basis of narrow frame design and reduction of the row spacing brightness risk.
In an embodiment of the invention, the first metal lead 2 is connected to the odd-numbered rows of pixel data lines, and the second metal lead 3 is connected to the even-numbered rows of pixel data lines. Specifically, the display data on the source data line source1 corresponding to the first metal lead 2 is written into the pixel data lines in the odd columns, and the display data on the source data line source2 corresponding to the second metal lead 3 is written into the pixel data lines in the even columns. Because the delay of the first signal is equal to that of the second signal, the voltage signal changes on the source1 are consistent with those on the source2, so that the pixel brightness corresponding to the odd column data1 and the even column data2 are equal, and the uniformity of the odd-even column brightness of the display panel is guaranteed.
In an embodiment of the present invention, the first metal leads 2 and the second metal leads 3 are symmetrically arranged along a longitudinal axis direction of the driving chip 1, a distance between two adjacent first metal leads 2 is equal, and a distance between two adjacent second metal leads 3 is equal. It should be understood that, as long as narrow frame design and convenient wiring are easily achieved, the embodiment of the present invention does not limit the specific value of the distance between two adjacent metal leads and the specific wiring form.
According to the display panel provided by the embodiment of the invention, the first metal leads 2 and the second metal leads 3 are symmetrically arranged along the longitudinal axis direction of the driving chip 1, the distance between two adjacent first metal leads 2 is equal, and the distance between two adjacent second metal leads 3 is equal, so that the consistency of control signal supply at different positions of the display panel can be ensured, and the display effect of the display panel is further ensured.
Fig. 7 is a schematic structural diagram of a display panel according to another embodiment of the invention.
In an embodiment of the present invention, as shown in fig. 7, the third conductive layer 4 includes a power signal region 5, and the power signal region 5 is connected to a pixel driving power source. Specifically, the pixel driving power supplies power to the pixel circuit through the power signal region 5, and the power signal region 5 covers the first metal wire 2 and the second metal wire 3 thereunder. By arranging the power signal area 5, the comprehensive screen design of the display panel can be further realized on the basis of the narrow frame. In addition, the design of the large area of the power signal area 5 is beneficial to reducing the voltage drop of the fan-out area, and the display effect of the display panel can be further guaranteed on the basis of designing a comprehensive screen and reducing the alternate bright risk.
In an embodiment of the invention, the first metal lead 2 below the power signal area 5 is parallel to the projection of the second metal lead 3 on the substrate layer. Specifically, the second metal lead 3 is arranged obliquely above the first metal lead 2, so that the consistency of the supply of control signals at different positions of the display panel can be ensured, and the display effect of the display panel is further ensured.
It will be understood that the foregoing is illustrative of particular embodiments of the invention and that the invention is not limited thereto, as many similar variations are possible. All modifications which would occur to one skilled in the art and which are, therefore, directly derived or suggested from the disclosure herein are deemed to be within the scope of the present invention.
It should be understood that the terms such as first, second, etc. used in the embodiments of the present invention are only used for clearly describing the technical solutions of the embodiments of the present invention, and are not used to limit the protection scope of the present invention.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and the like that are within the spirit and principle of the present invention are included in the present invention.
Claims (10)
1. A display panel, comprising:
the driving chip comprises a plurality of first pins for outputting first signals and a plurality of second pins for outputting second signals;
the first metal leads are electrically connected with the first pins one by one respectively;
the second metal leads are electrically connected with the second pins one by one respectively; and
a third conductive layer disposed at one side of the first metal lead and the second metal lead;
wherein a distance from the second metal lead to the third conductive layer is shorter than a distance from the first metal lead to the third conductive layer, a line width w of the second metal lead2Is smaller than the line width w of the first metal lead1。
2. The display panel according to claim 1, further comprising:
the first dielectric layer is arranged between the first metal lead and the second metal lead;
and the second dielectric layer is arranged between the second metal lead and the third conducting layer.
3. The display panel according to claim 2, wherein the first dielectric layer and the second dielectric layer are the same insulating material; the thickness of the first dielectric layer is d1The thickness of the second dielectric layer is d2(ii) a The line width w of the first metal lead1And the line width w of the second metal lead2The following conditions are satisfied: w is a1:w2＝(d1+d2):d2。
4. The display panel according to claim 2, wherein the first dielectric layer and the second dielectric layer are equal in thickness; the first dielectric layer has a dielectric constant of1The dielectric constant of the second dielectric layer is2(ii) a The line width w of the first metal lead1And the line width w of the second metal lead2The following conditions are satisfied: w is a1:w2＝(1+2):1。
5. The display panel of claim 2, wherein the first dielectric layer: thickness d1A dielectric constant of1(ii) a The second medium layer: thickness d2A dielectric constant of2(ii) a The line width w of the first metal lead1And the line width w of the second metal lead2The following conditions are satisfied: w is a1:w2＝(1*d2+2*d1):(1*d2)。
6. The display panel according to any one of claims 1 to 5, wherein the length of the second metal lead is smaller than the length of the first metal lead.
7. The display panel according to any one of claims 1 to 5, wherein the first metal wiring is connected to odd-numbered column pixel data lines, and the second metal wiring is connected to even-numbered column pixel data lines.
8. The display panel according to any one of claims 1 to 5, wherein the first metal leads and the second metal leads are symmetrically arranged along a longitudinal axis direction of the driving chip, a distance between two adjacent first metal leads is equal, and a distance between two adjacent second metal leads is equal.
9. The display panel according to any one of claims 1 to 5, wherein the third conductive layer includes a power signal region, and the power signal region is connected to a pixel driving power source.
10. The display panel of claim 9, wherein the first metal lead under the power signal region is parallel to a projection of the second metal lead on a substrate layer.
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