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CN111405771A - A kind of manufacturing method of printed circuit conductive line - Google Patents

A kind of manufacturing method of printed circuit conductive line Download PDF

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CN111405771A
CN111405771A CN202010155047.0A CN202010155047A CN111405771A CN 111405771 A CN111405771 A CN 111405771A CN 202010155047 A CN202010155047 A CN 202010155047A CN 111405771 A CN111405771 A CN 111405771A
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copper
circuit
seed layer
printed circuit
tin
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王守绪
胡甲聪
阿的克古
陈欣雨
陈苑明
何为
王翀
周国云
洪延
杨文君
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University of Electronic Science and Technology of China
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process

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  • Manufacturing Of Printed Wiring (AREA)

Abstract

一种印制电路导电线路的制作方法,涉及印制电路板制造技术领域。包括:1)在印制电路绝缘基板表面生长锡质种子层,2)在锡质种子层上覆盖图形化的干膜,3)电镀铜形成铜质导电线路,4)干膜的去除,5)上步处理后得到的基板进行热处理,使铜质导电线路与锡质种子层共熔成一体;6)蚀刻锡质种子层,获得印制电路导电线路。本发明方法中,蚀刻锡层速度快,精准度高,线路完整无侧蚀,利于制作高精度线路板;同时,铜锡两种金属共熔形成均匀的合金层,释放了金属间的应力,防止了锡质种子层与铜质导电线的蚀刻速度不一致而产生的局部缺陷,保证了导电线路与底层绝缘介质的结合力,使得线路图形耐热性好,稳定性高,可靠性强。

Figure 202010155047

A manufacturing method of a printed circuit conductive circuit relates to the technical field of printed circuit board manufacturing. Including: 1) growing a tin seed layer on the surface of the printed circuit insulating substrate, 2) covering a patterned dry film on the tin seed layer, 3) electroplating copper to form a copper conductive circuit, 4) removing the dry film, 5 ) heat treatment of the substrate obtained after the previous step, so that the copper conductive circuit and the tin seed layer are eutectic and integrated; 6) the tin seed layer is etched to obtain a printed circuit conductive circuit. In the method of the invention, the etching speed of the tin layer is fast, the precision is high, and the circuit is complete without side etching, which is conducive to the manufacture of high-precision circuit boards; It prevents the local defects caused by the inconsistent etching speed of the tin seed layer and the copper conductive line, ensures the bonding force between the conductive line and the underlying insulating medium, and makes the circuit pattern with good heat resistance, high stability and high reliability.

Figure 202010155047

Description

一种印制电路导电线路的制作方法A kind of manufacturing method of printed circuit conductive line

技术领域technical field

本发明涉及印制电路板制造技术领域,具体涉及一种印制电路导电线路的制作方法。The invention relates to the technical field of printed circuit board manufacturing, in particular to a manufacturing method of a printed circuit conductive circuit.

背景技术Background technique

印制电路板作为承载电子元器件并连接电路的“桥梁”,广泛应用于通讯电子、消费电子、计算机、汽车电子、工业控制、医疗器械、国防及航空航天等领域,是现代电子信息产业中不可或缺的存在。在近些年的云技术、5G网络建设、大数据、人工智能、共享经济、工业4.0、物联网等加速演变的大环境趋势下,市场对PCB制造技术提出了更高的要求,为适应高密度、高精度、微型化的需要,其制造技术与工艺急需改革和创新,首当其冲的就是关于精细线路图形的制作技术。As a "bridge" that carries electronic components and connects circuits, printed circuit boards are widely used in communication electronics, consumer electronics, computers, automotive electronics, industrial control, medical equipment, national defense and aerospace and other fields. indispensable presence. In recent years, with the accelerated evolution of cloud technology, 5G network construction, big data, artificial intelligence, sharing economy, Industry 4.0, and the Internet of Things, the market has put forward higher requirements for PCB manufacturing technology. The need for density, high precision, and miniaturization, its manufacturing technology and process urgently need reform and innovation, and the first is the production technology of fine circuit patterns.

目前印制电路板行业中99%以上的企业都在使用传统印制电路板线路图形制作技术,该技术的核心是采用抗蚀层覆盖住被保护的线路图形,然后用蚀刻液蚀刻掉铜面上不需要的部分,从而制得所需要的线路图形。铜蚀刻液分为碱性蚀刻液和酸性蚀刻液。使用碱性蚀刻液时,以镀锡层作为抗蚀层,一种典型的流程是:覆铜板前处理→涂覆光致抗蚀剂→曝光→显影→形成抗电镀层→图形电镀锡→褪膜→蚀刻铜→退锡→光学检测,该流程示意图如图2所示;使用酸性蚀刻液时,以抗蚀干膜作为抗蚀层,一种典型的流程为覆铜板前处理→涂覆光致抗蚀剂→曝光→显影→形成抗蚀层→蚀刻铜→褪膜→光学检测,该流程示意图如图3所示。这种传统印制电路板线路图形制作技术的优点是技术成熟,设备完善,产品制造的合格率高,但由于蚀刻时存在侧蚀,该技术会带来一个不可避免的问题,那就是当线路的线宽和线距进一步缩小的时候,线路上宽和下宽的差距会进一步增大,甚至发生严重的蚀刻过量现象,这将会对信号的传输产生极大的不利影响。At present, more than 99% of enterprises in the printed circuit board industry are using traditional printed circuit board circuit pattern making technology. The core of this technology is to use a resist layer to cover the protected circuit pattern, and then use etching solution to etch away the copper surface. Unnecessary parts on the board, so as to obtain the required circuit pattern. Copper etching solution is divided into alkaline etching solution and acid etching solution. When using alkaline etching solution, the tin plating layer is used as the resist layer. A typical process is: pretreatment of copper clad laminate → coating photoresist → exposure → development → formation of anti-plating layer → pattern plating tin → fading Film → etching copper → tin stripping → optical inspection, the schematic diagram of the process is shown in Figure 2; when using acid etching solution, the dry resist film is used as the resist layer, a typical process is CCL pretreatment → coating light Photoresist→exposure→development→formation of resist layer→etching copper→film stripping→optical inspection. The schematic diagram of the process is shown in FIG. 3 . The advantages of this traditional printed circuit board circuit pattern manufacturing technology are that the technology is mature, the equipment is perfect, and the product manufacturing qualification rate is high. However, due to side etching during etching, this technology will bring an inevitable problem, that is, when the circuit When the line width and line spacing are further reduced, the gap between the upper width and the lower width of the line will further increase, and even a serious over-etching phenomenon will occur, which will have a great adverse effect on signal transmission.

在蚀刻过程中,蚀刻时间随铜层厚度的不同而存在差异。铜层厚度较小时,所需蚀刻时长较短。短的蚀刻时长有利于减轻侧蚀,从而提高精细线路的质量。因此有人提出了一种新技术,该技术的主体有别于传统线路图形制作方法的核心,是将“蚀刻掉铜面上不需要的部分得到所需线路图形”转化为“将薄铜层作为种子层,在种子层上生长出所需线路图形”,从而避免了蚀刻大量铜的工序以及蚀刻铜层带来的侧蚀问题。During the etching process, the etching time varies with the thickness of the copper layer. When the copper layer thickness is smaller, the required etching time is shorter. Short etching time is beneficial to reduce side etching, thereby improving the quality of fine lines. Therefore, someone proposed a new technology. The main body of the technology is different from the core of the traditional circuit pattern production method. The seed layer is used to grow the desired circuit pattern on the seed layer, thereby avoiding the process of etching a large amount of copper and the side etching problem caused by etching the copper layer.

在这种以薄铜层作为种子层的制作技术中,又可以根据薄铜层的沉积方式分为:化学镀铜、层压厚铜再减薄、磁控溅射沉积铜等。其中,化学镀铜是在没有外加电流的情况下,利用镀液中的还原剂,并在具有催化活性的基材上将镀液中的金属离子还原为金属原子进而沉积在基材表面,使用的还原剂一般为甲醛,沉积所得铜层虽然厚度一致,能均匀的覆盖在基材表面,但化学镀铜层与基材之间的结合力明显不足,很容易产生线路剥离的严重问题,对于目前普遍使用的环氧树脂基材更是如此。在进行元器件贴装时,线路板一般要经过230℃~260℃的高温,较差的结合力很容易导致线路板在某一次热应力测试之后就出现铜层与介质层分层、产生气泡等缺陷。【电子元件与材料,2014,33(02):6-9+15】中还提到:化学沉铜可能存在包括位错、孪晶、晶粒边界等在内的晶体缺陷;化学镀铜层的铜质量分数、密度、延展率通常均低于电镀铜,因此快速蚀刻后化学铜面与介质层之间易形成底部咬蚀的侧蚀状态,进一步降低线路的接触面积。In this production technology using the thin copper layer as the seed layer, it can be further divided into: electroless copper plating, lamination of thick copper and then thinning, magnetron sputtering deposition of copper, etc. according to the deposition method of the thin copper layer. Among them, electroless copper plating is to use the reducing agent in the plating solution in the absence of an applied current, and on the substrate with catalytic activity, the metal ions in the plating solution are reduced to metal atoms and then deposited on the surface of the substrate. The reducing agent is generally formaldehyde. Although the deposited copper layer has the same thickness and can evenly cover the surface of the substrate, the bonding force between the electroless copper plating layer and the substrate is obviously insufficient, and it is easy to cause serious problems of line peeling. This is especially true of epoxy resin substrates that are commonly used today. When mounting components, the circuit board generally has to go through a high temperature of 230°C to 260°C. Poor bonding force can easily lead to the delamination of the copper layer and the dielectric layer and the generation of air bubbles after a certain thermal stress test of the circuit board. and other defects. [Electronic Components and Materials, 2014, 33(02): 6-9+15] also mentioned that: electroless copper may have crystal defects including dislocations, twins, grain boundaries, etc.; electroless copper plating layer The copper mass fraction, density, and elongation rate of copper are usually lower than those of electroplated copper. Therefore, after rapid etching, a side-etching state of bottom etch is easily formed between the chemical copper surface and the dielectric layer, which further reduces the contact area of the circuit.

层压厚铜再减薄是在传统的层压超薄铜作为种子层的方法上改良而成的新工艺。【印制电路信息,2013(08):9-13】中提出:层压厚铜再减薄工艺要求铜箔厚度要合适,如果铜箔太厚,需要减铜的量较多,由于蚀刻液对铜面上各处的腐蚀速率无法达到完全一致,会造成咬蚀程度不均匀的结果;如果铜箔厚度太薄,则制作覆铜箔层压板的时候难度加大,薄铜箔在层压的时候容易产生划伤和褶皱,而且薄铜箔的生产成本较高。由于信号传输速率和频率的提高要求印制电路板精细线路光滑平整,因此层压厚铜再减薄的工艺无法满足要求。Lamination thick copper thinning is a new process improved on the traditional method of laminating ultra-thin copper as a seed layer. [Printed Circuit Information, 2013(08):9-13] proposed that the thickness of the copper foil should be appropriate for the thinning process of laminating thick copper. If the copper foil is too thick, a large amount of copper needs to be reduced. The corrosion rate of all parts of the copper surface cannot be completely consistent, which will result in uneven bite corrosion; if the thickness of the copper foil is too thin, it will be more difficult to make a copper-clad laminate, and the thin copper foil will be laminated during lamination. It is prone to scratches and wrinkles when it is used, and the production cost of thin copper foil is high. Due to the increase in signal transmission rate and frequency, the fine lines of printed circuit boards are required to be smooth and flat, so the process of laminating thick copper and then thinning it cannot meet the requirements.

磁控溅射沉积薄铜种子层的方法具有设备操作简单,沉积面积可控,铜层与基材的结合力较好的特点,另外由于沉积过程属于物理气相沉积,不需要用到化学试剂,可以极大地减少对环境的污染。但是,磁控溅射设备成本较高,要求条件严苛且生产效率非常低,目前还无法广泛应用于印制电路板的批量生产中。【印制电路信息,2014(01):38-39+58】中指出:不同的溅镀条件对线路剥离强度有较大的影响,只有在适当的溅镀条件时才能达到良好的结合力。The method of depositing a thin copper seed layer by magnetron sputtering has the characteristics of simple equipment operation, controllable deposition area, and good bonding force between the copper layer and the substrate. It can greatly reduce the pollution to the environment. However, magnetron sputtering equipment has high cost, strict requirements and very low production efficiency, so it cannot be widely used in mass production of printed circuit boards at present. [Printed Circuit Information, 2014(01):38-39+58] pointed out that different sputtering conditions have a great influence on the stripping strength of the lines, and good bonding force can only be achieved under appropriate sputtering conditions.

而除了以薄铜层作为种子层,类似地,【印制电路信息,2017,25(z1):213-217】中提到了以化学镀镍层作为种子层的新型导电线路制作方法。这种方法避免了蚀刻大量铜,同时减少了侧蚀带来的信号传输受损的问题。但是这种方法仍然存在一些问题,一是由于镍与环氧树脂板间的结合力强弱与化学镀镍层的厚度有关:当化学镍层的厚度达到8μm后,其间结合力超过35μm铜厚覆铜板铜箔与环氧树脂基材之间的结合力,然而,随着化学镍层厚度的增加,镍蚀刻所需要的时间增加,又由于金属镍在空气中易发生钝化,进一步加大了蚀刻的难度,这对线路可靠性产生了很大的影响;二是镍和铜在较低温度下难以实现金属一体化。金属一体化有利于解决金属层之间的应力集中的问题,有利于减少侧蚀的形成,增加线路可靠性。而较高温的热处理条件又会造成加工工艺成本增加和铜面氧化的线路失效风险。In addition to using a thin copper layer as the seed layer, similarly, [Printed Circuit Information, 2017, 25(z1): 213-217] mentioned a new conductive circuit fabrication method using an electroless nickel layer as the seed layer. This method avoids etching a large amount of copper, while reducing the problem of impaired signal transmission caused by side etching. However, there are still some problems with this method. First, the bonding force between the nickel and the epoxy resin board is related to the thickness of the electroless nickel plating layer: when the thickness of the electroless nickel layer reaches 8 μm, the bonding force exceeds the copper thickness of 35 μm. However, with the increase of the thickness of the chemical nickel layer, the time required for nickel etching increases, and because the metal nickel is prone to passivation in the air, it further increases The difficulty of etching has a great impact on the reliability of the circuit; the second is that it is difficult for nickel and copper to achieve metal integration at lower temperatures. Metal integration is conducive to solving the problem of stress concentration between metal layers, reducing the formation of side corrosion and increasing the reliability of the circuit. The higher temperature heat treatment conditions will increase the cost of the processing process and the risk of circuit failure due to oxidation of the copper surface.

发明内容SUMMARY OF THE INVENTION

本发明的目的在于,针对背景技术存在的缺陷,提出了一种印制电路导电线路的制作方法。本发明通过在绝缘基板上生长一层薄锡作为种子层,再在其上制得所需线路图形,非线路图形区域的锡层在蚀刻的过程中快速蚀刻掉。本发明相较于传统印制电路板线路图形制作工艺,避免了大量蚀刻铜层的工序以及蚀刻铜层带来的侧蚀问题;相较于薄铜作为种子层的线路图形制作工艺,避免了化学镀铜层与基材结合力差导致线路易剥离、热稳定性差的问题,避免了侧蚀的形成和线路接触面积的减小,也避免了线路图形因咬蚀不均粗糙不平而导致无法满足高频高速信号传输要求的问题,还避免了因为制作成本过高,效率过低,无法实现大批量生产的问题;相较于薄镍层作为种子层的线路图形制作工艺,避免了由于化学镀镍层钝化和镍层过厚导致的线路可靠性降低的问题,避免了高温热处理对铜面的氧化和难于实现铜镍金属一体化的问题。The purpose of the present invention is to provide a method for manufacturing a conductive circuit of a printed circuit in view of the defects existing in the background technology. In the invention, a thin layer of tin is grown on an insulating substrate as a seed layer, and then a desired circuit pattern is prepared thereon, and the tin layer in the non-circuit pattern area is quickly etched away during the etching process. Compared with the traditional circuit pattern manufacturing process of the printed circuit board, the present invention avoids a large number of processes of etching the copper layer and the side etching problem caused by etching the copper layer; The poor bonding force between the electroless copper plating layer and the substrate leads to the problems of easy stripping of the circuit and poor thermal stability, which avoids the formation of side etching and the reduction of the contact area of the circuit, and also avoids the failure of the circuit pattern due to uneven bite and roughness. The problem of meeting the requirements of high-frequency and high-speed signal transmission also avoids the problem that mass production cannot be achieved due to high production costs and low efficiency; The passivation of the nickel plating layer and the reduction of the reliability of the circuit caused by the excessive thickness of the nickel layer avoid the oxidation of the copper surface by the high temperature heat treatment and the difficulty in realizing the integration of copper and nickel metals.

为实现上述目的,本发明采用的技术方案如下:For achieving the above object, the technical scheme adopted in the present invention is as follows:

一种印制电路导电线路的制作方法,其特征在于,包括以下步骤:A method for manufacturing a conductive circuit of a printed circuit, comprising the following steps:

步骤1:在印制电路绝缘基板表面生长锡质种子层;Step 1: grow a tin seed layer on the surface of the printed circuit insulating substrate;

步骤2:在步骤1生长的锡质种子层上覆盖图形化的干膜作为抗电镀层;Step 2: Cover the tin seed layer grown in Step 1 with a patterned dry film as a plating resist;

步骤3:在步骤2得到的基板表面未被干膜覆盖的锡质种子层区域上进行电镀铜,形成铜质导电线路;Step 3: electroplating copper on the tin seed layer area of the substrate obtained in step 2 that is not covered by the dry film to form a copper conductive circuit;

步骤4:对步骤3电镀铜后得到的基板进行干膜的去除;Step 4: removing the dry film on the substrate obtained after the copper electroplating in Step 3;

步骤5:将步骤4处理后得到的基板进行热处理,使铜质导电线路与锡质种子层共熔成一体;Step 5: heat-treating the substrate obtained after the treatment in Step 4, so that the copper conductive circuit and the tin seed layer are eutectic and integrated;

步骤6:对步骤5处理后得到的基板表面未被电镀铜层覆盖的锡质种子层区域进行蚀刻处理,获得印制电路导电线路。Step 6: Etch the area of the tin seed layer on the surface of the substrate obtained after the treatment in Step 5, which is not covered by the electroplated copper layer, to obtain a printed circuit conductive circuit.

进一步地,步骤1中所述印制电路绝缘基板选自由环氧树脂、酚醛树脂、聚酯树脂、聚酰亚胺等材质制成的纸基印制板,环氧玻纤布印制板,复合基材印制板,特种基材印制板等多种绝缘基板材料中的一种。Further, the printed circuit insulating substrate described in step 1 is selected from paper-based printed boards made of epoxy resin, phenolic resin, polyester resin, polyimide and other materials, epoxy glass fiber cloth printed boards, It is one of various insulating substrate materials such as composite substrate printed boards, special substrate printed boards, etc.

进一步地,步骤1中生长的锡质种子层的厚度为1~2μm,采用的方法为化学镀技术或直接电镀技术。方法之的一化学镀技术包括还原法化学镀锡、歧化反应化学镀锡和浸镀法化学镀锡,其中,还原法化学镀锡是在无外加电流的情况下,在具有催化活性的基材上将镀液中的金属离子还原为金属原子进而沉积在基材表面。方法之二的直接电镀技术是先在印制电路绝缘基板表面涂覆导电层,之后再进入电镀锡工序,其中,导电层可以为钯系列(以钯或其化合物作为导电物质)、导电性高分子系列(如聚吡咯、聚苯胺)、碳黑系列(碳黑导电膜)等。Further, the thickness of the tin seed layer grown in step 1 is 1-2 μm, and the adopted method is electroless plating technology or direct electroplating technology. One of the electroless plating techniques includes reduction electroless tin plating, disproportionation reaction electroless tin plating and immersion plating electroless tin plating, wherein the reduction electroless tin plating is performed on a substrate with catalytic activity under the condition of no applied current. The metal ions in the plating solution are reduced to metal atoms and deposited on the surface of the substrate. The direct electroplating technology of the second method is to first coat a conductive layer on the surface of the printed circuit insulating substrate, and then enter the process of electroplating tin, wherein the conductive layer can be palladium series (using palladium or its compound as the conductive substance), with high conductivity. Molecular series (such as polypyrrole, polyaniline), carbon black series (carbon black conductive film), etc.

进一步地,步骤2中所述图形化的干膜可以采用照相底版或通过激光直接成像技术完成。其中,照相底版的方法以菲林作为掩模,通过曝光工序将线路图形转移到线路板上,形成一种抗电镀的掩模图形;抗电镀的掩模图形用于图形电镀工艺,即保护性的抗电镀材料在线路板上形成负相图形后,进行图形电镀铜,生长出所需的线路图形部分。而激光直接成像技术则是利用激光直接成像原理将线路图形以激光光束的形式直接投影在涂有光致抗蚀剂的线路板上进而实现图形转移的一种技术,其主要优点在于:无需使用照相底版,简化了生产工序,大大提高了生产效率,且由于比例设定模式灵活,大大提高了机器的对位精度,减小了图形转移的误差。Further, the patterned dry film in step 2 can be completed by using a photographic plate or by a laser direct imaging technology. Among them, the method of photographing the negative plate uses the film as a mask, and the circuit pattern is transferred to the circuit board through the exposure process to form an anti-plating mask pattern; the anti-plating mask pattern is used for the pattern plating process, that is, a protective After the electroplating resist material forms a negative phase pattern on the circuit board, pattern copper plating is performed to grow the desired circuit pattern part. The laser direct imaging technology is a technology that uses the principle of laser direct imaging to directly project the circuit pattern in the form of a laser beam on a circuit board coated with photoresist to realize the pattern transfer. Its main advantages are: no need to use a photographic plate , simplifies the production process, greatly improves the production efficiency, and because the scale setting mode is flexible, the alignment accuracy of the machine is greatly improved, and the error of graphic transfer is reduced.

进一步地,步骤3中所述铜质导电线路的厚度为5~100μm。Further, the thickness of the copper conductive circuit in step 3 is 5-100 μm.

进一步地,步骤3中所述电镀铜包括清洗、粗化、电镀的过程,其中,电镀时采用的电镀液为硫酸盐型、焦磷酸盐型、氟硼酸盐型或氰化物型,硫酸盐型最为常见,添加剂包括光亮剂、整平剂、抑制剂和辅助添加剂氯离子等。Further, the copper electroplating described in step 3 includes the processes of cleaning, roughening and electroplating, wherein the electroplating solution used during electroplating is sulfate type, pyrophosphate type, fluoroborate type or cyanide type, and sulfate type. The most common type of additives include brighteners, levelers, inhibitors and auxiliary additives such as chloride ions.

进一步地,步骤4中对基板进行干膜的去除时,采用3wt%~5wt%的氢氧化钠溶液,温度为50~60℃,去除方式为浸泡或机械喷淋等。Further, when removing the dry film from the substrate in step 4, a sodium hydroxide solution of 3wt%-5wt% is used, the temperature is 50-60°C, and the removal method is soaking or mechanical spraying.

进一步地,步骤5中所述热处理的温度为180℃~200℃,热处理时间为30s。铜锡界面在热处理后会发生锡、铜原子之间的相互结合、渗入、迁移、扩散等一系列动作,冷却固化后会快速形成一层类似″锡合金″的化合物薄层并逐渐增厚,这一铜锡界面合金化合物又被称为IMC(Intermetallic Compound)。Further, the temperature of the heat treatment in step 5 is 180°C to 200°C, and the heat treatment time is 30s. After heat treatment, the copper-tin interface will undergo a series of actions such as mutual bonding, infiltration, migration, and diffusion between tin and copper atoms. After cooling and solidification, a thin layer of compound similar to "tin alloy" will quickly form and gradually thicken This copper-tin interface alloy compound is also called IMC (Intermetallic Compound).

进一步地,步骤6中所述蚀刻处理采用化学方法槽式浸泡或喷淋。Further, the etching treatment in step 6 adopts a chemical method tank-type soaking or spraying.

进一步地,步骤6获得的印制电路导电线路的线宽为8μm~3mm。Further, the line width of the conductive circuit of the printed circuit obtained in step 6 is 8 μm˜3 mm.

本发明提供的一种印制电路导电线路的制作方法,以沉积薄锡种子层并在种子层上生长出所需线路图形为技术核心,非线路图形区域的锡在蚀刻的过程中快速蚀刻。本发明相较于传统印制电路板线路图形制作工艺(主要工艺流程示意图如图2和图3所示),种子层技术是有别于传统减成法制造工艺的一种改良型半加成法工艺,直接生长所需线路图形,避免了大量蚀刻铜层的工序,蚀刻厚度极薄的种子层金属避免了蚀刻不足或蚀刻过量等侧蚀问题;相较于薄铜层作为种子层的线路图形制作工艺,通过热处理实现金属一体化,避免了线路图形热稳定性差、易起泡剥离的问题,避免了侧蚀的形成和线路的接触面积的减小,也避免了铜面粗糙不平,在趋肤效应的作用下出现电阻增加,损耗增加,信号传输失真的现象,从而导致无法满足高频高速信号传输要求的问题,还避免了因为制作成本过高,效率过低,无法实现大批量生产的问题;相较于薄镍层作为种子层的线路图形制作工艺,由于锡种子层厚度极薄,且锡在空气中不易钝化,快速蚀刻所需时间极短,有利于减小铜线路受到的腐蚀,提高线路可靠性;另外,铜锡两种金属共熔形成均匀的IMC层,消除了铜锡之间原有的明显分界线,释放了金属间的应力,防止了锡质种子层与铜质导电线路的蚀刻速度不一致而产生的局部缺陷,保证了导电线路与底层绝缘介质的结合力,减少了侧蚀的形成,增强了线路图形的可靠性,也避免了高温热处理对铜面的氧化和难于实现铜镍金属一体化的问题。The present invention provides a method for manufacturing a conductive circuit of a printed circuit. The technical core is to deposit a thin tin seed layer and grow a desired circuit pattern on the seed layer, and the tin in the non-circuit pattern area is rapidly etched during the etching process. Compared with the traditional circuit pattern manufacturing process of the printed circuit board (the schematic diagrams of the main process flow are shown in Figures 2 and 3), the seed layer technology is an improved semi-additive method which is different from the traditional subtractive method manufacturing process. method, directly growing the required circuit patterns, avoiding a large number of processes of etching the copper layer, etching the extremely thin seed layer metal to avoid side etching problems such as insufficient etching or excessive etching; compared with the thin copper layer as the seed layer of the circuit The pattern manufacturing process realizes metal integration through heat treatment, which avoids the problems of poor thermal stability of the circuit pattern, easy foaming and peeling, avoids the formation of side etching and the reduction of the contact area of the circuit, and also avoids the roughness of the copper surface. Under the action of the skin effect, the resistance increases, the loss increases, and the signal transmission is distorted, which leads to the inability to meet the requirements of high-frequency and high-speed signal transmission. It also avoids the inability to achieve mass production due to high production costs and low efficiency Compared with the circuit pattern manufacturing process in which the thin nickel layer is used as the seed layer, the thickness of the tin seed layer is extremely thin, and the tin is not easily passivated in the air, and the time required for rapid etching is extremely short, which is beneficial to reduce the copper circuit. In addition, the two metals of copper and tin are eutectic to form a uniform IMC layer, which eliminates the original obvious dividing line between copper and tin, releases the stress between metals, and prevents the tin seed layer from interacting with The local defects caused by the inconsistent etching speed of copper conductive lines ensure the bonding force between the conductive lines and the underlying insulating medium, reduce the formation of side etching, enhance the reliability of the circuit pattern, and avoid the high temperature heat treatment on the copper surface. Oxidation and difficulty in achieving copper-nickel metal integration.

综上所述,与现有技术相比,本发明的有益效果为:To sum up, compared with the prior art, the beneficial effects of the present invention are:

本发明提供的一种印制电路导电线路的制作方法,相较于现有相类似的制作技术,克服了其实施过程中出现的种种不足之处。其优势主要表现在:(1)锡层蚀刻速度快,精准度高,线路完整无侧蚀且表面均匀平滑,利于制作高精度线路板且高频高速信号传输稳定;(2)铜锡两种金属共熔形成均匀的合金层,释放了金属间的应力,防止了锡质种子层与铜质导电线的蚀刻速度不一致而产生的局部缺陷,保证了导电线路与底层绝缘介质的结合力,减少了侧蚀的形成,使得线路图形耐热性好,稳定性高,可靠性强;(3)工艺制作条件简单,制作成本降低,有利于实现大规模批量生产。Compared with the existing similar manufacturing technology, the method for manufacturing a conductive circuit of a printed circuit provided by the present invention overcomes various deficiencies in the implementation process. Its advantages are mainly manifested in: (1) the tin layer etching speed is fast, the accuracy is high, the circuit is complete without side etching and the surface is uniform and smooth, which is conducive to the production of high-precision circuit boards and stable high-frequency and high-speed signal transmission; (2) two kinds of copper and tin Metal eutectic forms a uniform alloy layer, releases the stress between metals, prevents local defects caused by inconsistent etching speeds between the tin seed layer and the copper conductive wire, ensures the bonding force between the conductive wire and the underlying insulating medium, reduces the The formation of side etch is eliminated, so that the circuit pattern has good heat resistance, high stability and high reliability; (3) the manufacturing conditions of the process are simple, the manufacturing cost is reduced, and the large-scale mass production is facilitated.

可以发现,该新型印制电路基板导电线路制作方法,无论是较传统工艺还是相类似的种子层生长技术,在各方面都有着明显的优势。根据上述理论分析,本发明印制电路基板导电线路制作方法中所涉及到的化学镀锡、电镀锡、电镀铜、褪膜、蚀刻锡等流程中,对镀液、褪膜液、蚀刻液等的生产厂商、型号等都没有特殊要求,可以是任意厂商生产的合格药水添加剂。It can be found that the new method for manufacturing conductive lines of printed circuit substrates has obvious advantages in all aspects, whether compared with traditional processes or similar seed layer growth technologies. According to the above theoretical analysis, in the processes of chemical tin plating, tin electroplating, copper electroplating, film stripping, tin etching and other processes involved in the method for making conductive lines of printed circuit substrates of the present invention, the plating solution, film stripping solution, etching solution, etc. There are no special requirements for the manufacturer, model, etc., and it can be a qualified potion additive produced by any manufacturer.

附图说明Description of drawings

图1为本发明提供的一种印制电路导电线路的制作方法的工艺流程图;1 is a process flow diagram of a method for manufacturing a printed circuit conductive circuit provided by the present invention;

图2为使用碱性蚀刻液的传统印制电路导电线路的制作方法的工艺流程图;Fig. 2 is the process flow diagram of the manufacturing method of the traditional printed circuit conductive line using alkaline etching solution;

图3为使用酸性蚀刻液的传统印制电路导电线路的制作方法的工艺流程图;3 is a process flow diagram of a method for making a conventional printed circuit conductive circuit using an acidic etching solution;

图4为实施例1的效果示意图和金相切片图;其中,图4-(a)为环氧树脂基板上生长锡种子层的效果示意图,图4-(b)为环氧树脂基板上生长锡种子层的金相切片图,图4-(c)为锡种子层表面电镀铜层的效果示意图,图4-(d)为锡种子层表面电镀铜层的金相切片图,图4-(e)为热处理后生成铜锡合金的效果示意图,图4-(f)为热处理后生成铜锡合金的金相切片图;FIG. 4 is a schematic diagram of the effect and a metallographic section diagram of Example 1; wherein, FIG. 4-(a) is a schematic diagram of the effect of growing a tin seed layer on an epoxy resin substrate, and FIG. 4-(b) is a growth diagram on the epoxy resin substrate. The metallographic section view of the tin seed layer, Figure 4-(c) is a schematic diagram of the effect of the electroplated copper layer on the surface of the tin seed layer, and Figure 4-(d) is the metallographic section view of the electroplated copper layer on the surface of the tin seed layer, Figure 4- (e) is a schematic diagram of the effect of generating a copper-tin alloy after heat treatment, and FIG. 4-(f) is a metallographic section view of the copper-tin alloy generated after heat treatment;

图5为实施例1热处理后的导电线路的截面SEM图和EDS能谱图;5 is a cross-sectional SEM image and an EDS spectrogram of the conductive circuit after heat treatment in Example 1;

图6为实施例1在环氧树脂基板上获得的印制电路导电线路的截面金相切片图。FIG. 6 is a cross-sectional metallographic section view of the conductive circuit of the printed circuit obtained on the epoxy resin substrate in Example 1. FIG.

具体实施方式Detailed ways

下面结合附图和具体实施例对本申请做进一步阐述,以期本领域技术人员能够理解本发明方案及其特点。The present application will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can understand the solutions and features of the present invention.

实施例1Example 1

裁剪20mm*100mm的环氧树脂基板,经等离子体表面处理后,按表1所示镀液配方,采用浸镀法化学镀锡在基板表面生长厚度为2μm的锡质种子层;生长完成后,覆盖图形化的干膜;之后按表2所示镀液配方进行电镀铜,在基板表面未被干膜覆盖的锡质种子层区域上形成铜质导电线路,并在60℃的5wt%的氢氧化钠溶液中将干膜去除;然后在180℃下热处理30s,热处理后取出自然冷却至室温;最后对未被电镀铜层覆盖的锡质种子层区域进行蚀刻处理,获得印制电路导电线路。A 20mm*100mm epoxy resin substrate was cut, and after plasma surface treatment, a tin seed layer with a thickness of 2 μm was grown on the surface of the substrate by electroless tin plating by immersion plating according to the formula of the plating solution shown in Table 1; Cover the patterned dry film; then electroplate copper according to the bath formula shown in Table 2, and form copper conductive lines on the tin seed layer area not covered by the dry film on the surface of the substrate. The dry film was removed in sodium oxide solution; then heat-treated at 180°C for 30s, taken out after heat-treatment and cooled to room temperature naturally; finally, the area of the tin seed layer not covered by the electroplated copper layer was etched to obtain a printed circuit conductive line.

表1生长锡质种子层的镀液配方Table 1 The plating solution formula for growing tin seed layer

镀液组成Bath composition 浓度concentration 硫酸亚锡stannous sulfate 20g/L20g/L 硫脲Thiourea 70g/L70g/L 柠檬酸citric acid 40g/L40g/L 次亚磷酸钠sodium hypophosphite 70g/L70g/L 对苯二酚Quinol 4g/L4g/L 乳化剂(OP-10)Emulsifier (OP-10) 1mL/L1mL/L 硫酸sulfuric acid 2.5mL/L2.5mL/L

表2电镀铜的镀液配方Table 2 The plating solution formula of electroplating copper

镀液组成Bath composition 浓度concentration 五水合硫酸铜Copper sulfate pentahydrate 75g/L75g/L 硫酸sulfuric acid 240g/L240g/L 氯离子Chloride 60mg/L60mg/L 聚二硫二丙烷磺酸钠(SPS)Sodium Polydithiopropane Sulfonate (SPS) 1mg/L1mg/L 环氧乙烷-环氧丙烷嵌段共聚物(EO/PO)Ethylene oxide-propylene oxide block copolymer (EO/PO) 500mg/L500mg/L

在金相显微镜下观察环氧树脂基板上生长锡质种子层、锡质种子层表面电镀铜层、热处理后生成铜锡合金层、最终在环氧树脂基板上获得的印制电路导电线路的切片,结果分别如图4-(b)、图4-(d)、图4-(f)和图6所示。在扫描电子显微镜下观察热处理后导电线路的截面,并对截面元素进行EDS能谱分析,结果如图5所示。从图中可以看出:(1)在环氧树脂基板上生长锡质种子层厚度在2μm左右;(2)锡质种子层表面电镀铜层后,锡和铜金属层厚度在6μm左右;(3)热处理后,铜锡分界线消失,铜层和锡层共熔为一体,形成铜锡合金;(4)最终在环氧树脂基板上获得的印制电路导电线路图形完整,线路侧蚀程度较轻。Observe the growth of tin seed layer on the epoxy resin substrate, the electroplated copper layer on the surface of the tin seed layer, the formation of copper-tin alloy layer after heat treatment, and the slices of the printed circuit conductive circuit obtained on the epoxy resin substrate under a metallographic microscope , the results are shown in Fig. 4-(b), Fig. 4-(d), Fig. 4-(f) and Fig. 6, respectively. The cross-section of the conductive line after heat treatment was observed under a scanning electron microscope, and the elements of the cross-section were analyzed by EDS. The results are shown in Figure 5. It can be seen from the figure: (1) The thickness of the tin seed layer grown on the epoxy resin substrate is about 2 μm; (2) After the copper layer is electroplated on the surface of the tin seed layer, the thickness of the tin and copper metal layers is about 6 μm; ( 3) After the heat treatment, the copper-tin boundary disappears, and the copper layer and the tin layer are eutectic to form a copper-tin alloy; (4) The conductive circuit pattern of the printed circuit finally obtained on the epoxy resin substrate is complete, and the degree of side corrosion of the circuit is complete. lighter.

使用3M 600型宽1/2英寸的压敏胶带紧紧贴在导电线路的表面,排除压敏胶带下的空气。在压贴胶带后1分钟内完成撕胶带的动作,撕胶带时保持与导电线路表面大致呈直角,迅速施加拉力。按同样的步骤和方法完成三次测试,每次测试都使用未被污染的胶带。测试结果表明,导电线路与底层环氧树脂基板之间结合力良好。经剥离强度测试仪测定,得到剥离强度测试结果为0.86N/mm,满足IPC-TM650标准规定的最低剥离强度。Use 3M Type 600 1/2" wide pressure sensitive tape to firmly adhere to the surface of the conductive traces to exclude air from under the pressure sensitive tape. Complete the action of tearing off the tape within 1 minute after pressing the tape. When tearing off the tape, keep it at a roughly right angle to the surface of the conductive circuit, and quickly apply a pulling force. Complete three tests using the same procedure and method, using uncontaminated tape for each test. The test results show that the bonding force between the conductive line and the underlying epoxy resin substrate is good. The peel strength test result is 0.86N/mm as measured by the peel strength tester, which meets the minimum peel strength specified by the IPC-TM650 standard.

实施例2Example 2

本实施例与实施例1相比,区别在于:以15mm*100mm的PI(Polyimide,聚酰亚胺)作为基板,以在1mol/L的KOH溶液中浸泡10分钟为表面处理方式,其余步骤与实施例1相同。Compared with Example 1, the difference between this example is that 15mm*100mm PI (Polyimide, polyimide) is used as the substrate, and the surface treatment method is immersed in 1mol/L KOH solution for 10 minutes. The remaining steps are the same as Example 1 is the same.

实施例3Example 3

本实施例与实施例1相比,区别在于:以15mm*100mm的PET(PolyethyleneTerephthalate,聚对苯二甲酸乙二醇酯)作为基板,以在1mol/L的KOH溶液中浸泡10分钟为表面处理方式,其余步骤与实施例1相同。Compared with Example 1, the difference between this example is that 15mm*100mm PET (PolyethyleneTerephthalate, polyethylene terephthalate) is used as the substrate, and the surface treatment is immersed in 1mol/L KOH solution for 10 minutes. The rest of the steps are the same as in Example 1.

以上所述实例仅表达了本发明的一种实施方式,其描述较为具体和详细,但并不能因此而理解为对本发明专利范围的限制。应当指出的是,对于本领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干变形和改进,这些都属于本发明的保护范围。因此,本发明专利的保护范围应以所附权利要求书为准。The above-mentioned example only expresses an embodiment of the present invention, and its description is relatively specific and detailed, but it should not be construed as a limitation on the patent scope of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can also be made, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the appended claims.

Claims (5)

1.一种印制电路导电线路的制作方法,其特征在于,包括以下步骤:1. a preparation method of a printed circuit conductive circuit, is characterized in that, comprises the following steps: 步骤1:在印制电路绝缘基板表面生长锡质种子层;Step 1: grow a tin seed layer on the surface of the printed circuit insulating substrate; 步骤2:在步骤1生长的锡质种子层上覆盖图形化的干膜作为抗电镀层;Step 2: Cover the tin seed layer grown in Step 1 with a patterned dry film as a plating resist; 步骤3:在步骤2得到的基板表面未被干膜覆盖的锡质种子层区域上进行电镀铜,形成铜质导电线路;Step 3: electroplating copper on the tin seed layer area of the substrate obtained in step 2 that is not covered by the dry film to form a copper conductive circuit; 步骤4:对步骤3电镀铜后得到的基板进行干膜的去除;Step 4: removing the dry film on the substrate obtained after the copper electroplating in Step 3; 步骤5:将步骤4处理后得到的基板进行热处理,使铜质导电线路与锡质种子层共熔成一体;Step 5: heat-treating the substrate obtained after the treatment in Step 4, so that the copper conductive circuit and the tin seed layer are eutectic and integrated; 步骤6:对步骤5处理后得到的基板表面未被电镀铜层覆盖的锡质种子层区域进行蚀刻处理,获得印制电路导电线路。Step 6: Etch the area of the tin seed layer on the surface of the substrate obtained after the treatment in Step 5, which is not covered by the electroplated copper layer, to obtain a printed circuit conductive circuit. 2.根据权利要求1所述的印制电路导电线路的制作方法,其特征在于,步骤1中生长的锡质种子层的厚度为1~2μm。2 . The method for manufacturing a conductive circuit of a printed circuit according to claim 1 , wherein the tin seed layer grown in step 1 has a thickness of 1-2 μm. 3 . 3.根据权利要求1所述的印制电路导电线路的制作方法,其特征在于,步骤2中所述图形化的干膜采用照相底版或通过激光直接成像技术得到。3 . The method for manufacturing a conductive circuit of a printed circuit according to claim 1 , wherein the patterned dry film in step 2 is obtained by using a photographic plate or by using a laser direct imaging technique. 4 . 4.根据权利要求1所述的印制电路导电线路的制作方法,其特征在于,步骤3中所述铜质导电线路的厚度为5~100μm。4 . The method for manufacturing a conductive circuit of a printed circuit according to claim 1 , wherein the thickness of the copper conductive circuit in step 3 is 5-100 μm. 5 . 5.根据权利要求1所述的印制电路导电线路的制作方法,其特征在于,步骤5中所述热处理的温度为180℃~200℃,热处理时间为30s。5 . The method for manufacturing a printed circuit conductive line according to claim 1 , wherein the temperature of the heat treatment in step 5 is 180° C.˜200° C., and the heat treatment time is 30 s. 6 .
CN202010155047.0A 2020-03-09 2020-03-09 A kind of manufacturing method of printed circuit conductive line Pending CN111405771A (en)

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CN112235951A (en) * 2020-10-20 2021-01-15 盐城维信电子有限公司 Method for manufacturing circuit boards with different copper thicknesses
CN112635602A (en) * 2020-12-23 2021-04-09 泰州隆基乐叶光伏科技有限公司 Conductive backboard, manufacturing method thereof and back contact photovoltaic module
CN114554704A (en) * 2022-03-25 2022-05-27 深圳市大族数控科技股份有限公司 How to make a circuit board
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JP2007329325A (en) * 2006-06-08 2007-12-20 Fujikura Ltd Wiring board manufacturing method
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112235951A (en) * 2020-10-20 2021-01-15 盐城维信电子有限公司 Method for manufacturing circuit boards with different copper thicknesses
CN112235951B (en) * 2020-10-20 2021-09-21 盐城维信电子有限公司 Method for manufacturing circuit boards with different copper thicknesses
CN112635602A (en) * 2020-12-23 2021-04-09 泰州隆基乐叶光伏科技有限公司 Conductive backboard, manufacturing method thereof and back contact photovoltaic module
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RU2854162C1 (en) * 2025-04-17 2025-12-29 Акционерное Общество "Научно-Исследовательский Центр Электронной Вычислительной Техники" Method of combined positive manufacturing of printed circuit boards with a conductor pattern thickness of the outer layers of more than 150 mc

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Application publication date: 20200710