CN111404391A - Positive-shock active clamping driving circuit - Google Patents

Abstract

The invention relates to a forward active clamping driving circuit, which comprises a control chip, a forward transformer, a main switching tube, an active clamping capacitor and two synchronous rectifier tubes, wherein a VIN pin of the control chip is connected with a VIN power supply. In addition, the voltages at the two ends of the primary winding of the forward transformer are in regular square wave shapes in each switching period, so that regular square waves are generated at the two ends of the secondary winding, the square wave voltages of the secondary winding can be used for driving the two synchronous rectifier tubes, a special synchronous rectification driving circuit is not required to be designed, the design is simplified, and the cost is reduced.

Description

A Forward Active Clamp Driving Circuit

technical field

The invention relates to the technical field of power management, in particular to an active clamp drive circuit based on a forward converter.

Background technique

Forward converters are widely used due to their simple structure, reliable operation, and electrical isolation of input and output. But the converter has an obvious weakness, that is, when the main switch tube is turned off, a reset circuit must be added to realize the demagnetization of the transformer, so as to prevent the magnetic saturation of the transformer. Conventional demagnetization methods mainly include: third reset winding technology, lossless LCD clamping technology and RCD clamping technology. However, these three technologies each have their own shortcomings, such as the third reset winding technology is complicated to manufacture, and the voltage stress of the main switch tube is large; the current stress and on-state loss of the main switch tube of the LCD clamping technology are large, resulting in low system efficiency; The RCD clamp technique consumes a large part of the energy during the demagnetization process, resulting in low system efficiency.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a forward excitation active clamp drive circuit with novel structure, simple and practical structure. On the traditional forward excitation converter, a clamp branch is added, and the branch is composed of an active clamp capacitor and an active clamp. The source clamp switch tubes are connected in series. The main switch tube and the active clamp switch tube use a specially designed drive module circuit (the realization of the drive module only needs to be amplified step by step). This architecture can well achieve a large system occupancy. ratio, high efficiency, and facilitates the design of forward transformers.

In order to achieve the above purpose, the technical solution adopted in the present invention is a forward active clamp drive circuit, which includes a control chip, a forward transformer, a main switch tube, an active clamp switch tube, an active clamp capacitor, a third The first and second synchronous rectifiers, output inductors, isolation modules, and output capacitors, the VIN pin of the control chip is connected to the VIN power supply, and both ends of the primary winding of the forward transformer are connected to the VIN power supply and the drain of the main switch tube respectively. Both ends of the secondary winding of the transformer are connected to the first synchronous rectifier tube and the second synchronous rectifier tube. Specifically, the positive terminal of the output capacitor is connected to the output terminal of the circuit, and the negative terminal is connected to the ground. The output terminal of the circuit is connected to the COMP pin and CS2 pin of the control chip through the isolation module, and the gate of the main switch tube is connected to the OUTA pin of the control chip. , the source of the main switch tube is connected to the CS1 pin of the control chip, the positive terminal of the active clamp capacitor is connected to the drain of the main switch tube, the negative terminal is connected to the source of the active clamp switch tube, and the active clamp switch tube The gate of the control chip is connected to the OUTB pin of the control chip, the drain of the active clamp switch is grounded, the GND pin of the control chip is grounded, and the first plug-in resistor and the first plug-in capacitor are connected in series between the VIN power supply and the ground to control the The RAMP pin of the chip is connected between the first external resistor and the first external capacitor, and the second external resistor is connected in series between the RT pin of the control chip and the ground.

As an improvement of the present invention, it also includes a current sampling resistor, first and second voltage dividing resistors, an output sampling network, a capacitor pump, a second external capacitor, a third external capacitor, a first and a second diode, and a current The sampling resistor is set on the main switch branch. Specifically, the current sampling resistor is connected in series between the source of the main switch and the ground, and the CS1 pin of the control chip is connected between the source of the main switch and the current sampling resistor. The first and second voltage dividing resistors are voltage dividing resistors of the control chip COMP pin voltage. After the first and second voltage dividing resistors are connected in series, one end is connected to the output end of the isolation module, the other end is grounded, and the COMP pin of the control chip is connected to the output end of the isolation module. Between the output terminal of the isolation module and the first voltage dividing resistor, the CS2 pin of the control chip is connected between the first and second voltage dividing resistors, and the output sampling network is connected between the input terminal of the isolation module and the circuit output terminal , the output sampling network is composed of two resistors in series, the positive terminal of the capacitor pump is connected to the OUTB pin of the control chip, the negative terminal is connected to the gate of the active clamp switch tube, and the second external capacitor is connected in series to the VCC of the control chip. Between the pin and the ground, the third external capacitor is connected in series between the COMP pin of the control chip and the ground, and the first diode is connected in series between the VCC pin of the control chip and the auxiliary winding coupled with the output inductance. The second diode is connected in series between the gate and the drain of the active clamp switch.

As an improvement of the present invention, the control chip is provided with a voltage adjustment module, an internal power supply/bias/enable module, a first and a second drive module, an oscillator, a switch MOS tube, a logic module, and an RS trigger. comparator, the first to fourth comparators, OR gate, two pull-down MOS transistors, the VIN pin is connected to the input end of the voltage regulation module, the output end of the voltage regulation module is connected to the VCC pin and the internal power/bias/enable module , the internal power/bias/enable module provides power, enable and bias for each module inside the control chip, VCC supplies power for the first and second drive modules, and the input terminal of the oscillator is connected to the RT pin, which is determined by the oscillator Control the switching frequency of the chip, the output terminal of the oscillator is connected to the input terminal of the logic module and the S terminal of the RS flip-flop, the gate of the switch MOS tube, the R terminal of the RS flip-flop and the gates of the two pull-down MOS tubes are all connected to the logic The output end of the module, the output end of the RS flip-flop is respectively connected to the input end of the first drive module and the second drive module, the output ends of the first drive module and the second drive module are OUTA pin and OUTB pin respectively, switch MOS tube The source is connected to the RAMP pin, the forward input of the first and second comparators is connected to the RAMP pin, the reverse input of the first comparator is connected to the COMP pin, and the reverse input of the second comparator is connected to 3.5 V reference voltage, the forward input terminals of the third comparator and the fourth comparator are connected to the CS1 pin and CS2 pin respectively, the reverse input terminals of the third comparator and the fourth comparator are both connected to the 0.5V reference voltage, the first The output terminals of the first to fourth comparators are all connected to the input terminal of the OR gate, the output terminal of the OR gate is connected to the input terminal of the logic module, and the forward input terminals of the third comparator and the fourth comparator are respectively connected to two pull-down MOS The source of the tube, and the drains of the two pull-down MOS tubes are grounded.

As an improvement of the present invention, the value range of the VIN power supply is 30~100V, and the value range of the VCC power supply is 8~15V.

As an improvement of the present invention, the main switch tube is selected from NMOS tube, and the active clamp switch tube is selected from PMOS tube.

As an improvement of the present invention, the isolation module is composed of TL431 and an optocoupler.

As an improvement of the present invention, the first comparator is a loop comparator, the second comparator is a volt-second clamp comparator, the third comparator is a main switch branch overcurrent protection comparator, and the fourth comparator For the output voltage undervoltage protection comparator.

As an improvement of the present invention, the input voltage of the RAMP pin of the control chip is a ramp voltage, and the peak value of the RAMP ramp voltage is 3.5V.

As an improvement of the present invention, when the VIN power supply is constant, the maximum on-time (ie duty cycle) of the circuit system is determined by the values of the first external resistor and the first external capacitor, and the system duty cycle can be greater than 0.5 .

As an improvement of the present invention, both the first and second synchronous rectifiers use NMOS transistors.

Compared with the prior art, the overall structure of the circuit of the present invention is ingeniously designed, the structure is novel, simple and practical, and a clamp branch is added to the traditional forward converter, and the branch is composed of an active clamp capacitor and an active clamp switch. The main switch tube and the active clamp switch tube are driven by the drive circuit specially designed inside the control chip, which can well realize the large duty cycle of the system, high efficiency and convenient forward transformer design. In addition, the voltage across the primary winding of the forward transformer has a regular square wave shape in each switching cycle, thereby generating a regular square wave at both ends of the secondary winding. There is no need to specially design a synchronous rectifier drive circuit, which simplifies the design and reduces the cost.

Description of drawings

FIG. 1 is a structural diagram of a forward active clamp driving circuit according to a preferred embodiment of the present invention.

FIG. 2 is a waveform diagram of each main signal of the forward active clamp driving circuit according to the preferred embodiment of the present invention.

Detailed ways

In order to deepen the understanding and understanding of the present invention, the present invention will be further described and introduced below with reference to the accompanying drawings.

The forward active clamp drive circuit of the preferred embodiment shown in FIG. 1 is an active clamp forward converter. On the traditional forward converter, a clamp branch is added, and the branch is connected by The active clamp capacitor and the active clamp switch are connected in series. The main switch and the active clamp switch use a specially designed drive circuit, that is, the main switch and the active clamp switch use their own independent drive modules. Drive (the drive design only needs to be amplified by a conventional multi-stage inverter). Specifically, it includes control chip IC, forward excitation transformer T1, main switch tube N1, active clamp switch tube P1, active clamp capacitor C5, first and second synchronous rectifier tubes, output inductor L, isolation module EA&Isolation, output capacitor Cout, current sampling resistor R3, first and second voltage dividing resistors, output sampling network, capacitor pump C3, second external capacitor C2, third external capacitor C4, first and second diodes.

Among them, the control chip IC is a forward drive chip with active clamping for magnetic reset. The VIN pin of the control chip IC is connected to the VIN power supply, and the two ends of the primary winding of the forward excitation transformer T1 are respectively connected to the VIN power supply and the main switch tube N1. Drain, both ends of the secondary winding of the forward transformer T1 are connected to the first synchronous rectifier N2 and the second synchronous rectifier N3, and both ends of the output inductor L are respectively connected to the secondary winding of the forward transformer T1 and the circuit output terminal VOUT, The output capacitor Cout is connected in series between the output terminal of the circuit and the ground. Specifically, the positive terminal of the output capacitor Cout is connected to the output terminal of the circuit, and the negative terminal is connected to the ground. The output end of the circuit is connected to the COMP pin and CS2 pin of the control chip IC through the isolation module EA&Isolation, the gate of the main switch N1 is connected to the OUTA pin of the control chip IC, and the source of the main switch N1 is connected to the CS1 pin of the control chip IC. foot. An active clamp branch is formed by the active clamp switch tube P1 and the active clamp capacitor C5. The positive terminal of the active clamp capacitor C5 is connected to the drain of the main switch tube N1, and the negative terminal is connected to the active clamp The source of the switch tube P1, the gate of the active clamp switch tube P1 is connected to the OUTB pin of the control chip IC, and the drain of the active clamp switch tube P1 is grounded. The GND pin of the control chip IC is grounded, the first plug-in resistor R1 and the first plug-in capacitor C1 are connected in series between the VIN power supply and the ground, and the RAMP pin of the control chip IC is connected to the first plug-in resistor R1 and the first plug-in capacitor C1. between. A second external resistor R2 is connected in series between the RT pin of the control chip IC and the ground to adjust the frequency of the built-in oscillator of the control chip IC.

The current sampling resistor R3 is arranged on the main switch branch. Specifically, the current sampling resistor R3 is connected in series between the source of the main switch tube N1 and the ground for overcurrent detection of the main switch branch. The CS1 pin of the control chip IC is connected between the source of the main switch tube N1 and the current sampling resistor R3. The first and second voltage dividing resistors R5 are voltage dividing resistors for the voltage of the COMP pin of the control chip. After the voltage dividing resistor R5 is connected in series, one end is connected to the output end of the isolation module EA&Isolation, and the other end is grounded. The COMP pin of the control chip IC is connected between the output end of the isolation module EA&Isolation and the first and second voltage dividing resistors R5R4. The control chip The CS2 pin of the IC is connected between the first and second voltage dividing resistors R5, so the CS2 pin can detect whether the voltage of the COMP pin of the control chip IC is too high, corresponding to the circuit output, which can be connected to the CS2 pin Check whether overload or undervoltage occurs at the output end of the circuit. The output sampling network is connected between the input terminal of the isolation module EA&Isolation and the output terminal of the circuit. The output sampling network is made up of resistors R6 and R7 in series. The positive terminal of the capacitor pump C3 is connected to the OUTB pin of the control chip IC, and the negative terminal is connected to a The gate of the source clamp switch tube P1, and the second external capacitor C2 is connected in series between the VCC pin of the control chip IC and the ground. In view of the fact that the Source end of the active clamp power transistor P1 is grounded, it can only be realized by a capacitor pump, because after the main switch N1 is turned off, the gate voltage of the active clamp switch P1 is reduced to a negative voltage through the capacitor pump C3 , and at this time, the Source voltage of the active clamp switch P1 is zero, so that the active clamp switch P1 can be turned on. The third external capacitor C4 is connected in series between the COMP pin of the control chip IC and the ground to adjust the stability of the circuit system. The first diode D1 is connected in series between the VCC pin of the control chip IC and the auxiliary winding coupled with the output inductance L, and the auxiliary winding coupled by the output inductance L supplies the VCC pin with unidirectional power supply through the first diode D1 . The second diode D2 is connected in series between the gate and the drain of the active clamp switch transistor P1.

Further, the inside of the control chip IC is provided with a voltage regulation module, an internal power supply/bias/enable module (ie LDO/BIAS/UVLO in the figure), a first and a second drive module, an oscillator, a switch MOS tube, logic module, RS flip-flop, first to fourth comparators, OR gate, two pull-down MOS tubes, the voltage regulation module is used to convert the high voltage VIN into the available medium voltage power supply VCC inside the control chip IC, the VIN The value range of the power supply is 30~100V, the VIN pin is connected to the input end of the voltage regulation module, and the output end of the voltage regulation module is connected to the VCC pin and the LDO/BIAS/UVLO module. The LDO/BIAS/UVLO module is used to generate the low-voltage power supply required inside the IC, various voltage and current biases, and the enable signal for the operation of each module, and to provide power, enable and bias for each module inside the control chip IC , and determine the startup voltage and undervoltage of VCC. VCC supplies power for the first and second drive modules, and the value range of the VCC power supply is 8~15V. The input terminal of the oscillator is connected to the RT pin, and the switching frequency of the control chip IC is determined by the oscillator, and the frequency can be adjusted by the second external resistor R2 externally placed on the RT pin. The output terminal of the oscillator is connected to the input terminal of the logic module and the S terminal of the RS flip-flop. The input terminal of the logic module is the clock signal of the oscillator and the inversion signal of each comparator. The function is that any comparator inversion can act on the following ones. RS flip-flop to control the shutdown drive. And every time the comparator is turned over, several control signals will be generated to control the clearing of CS1, CS2, RAMP and other signals. The gate of the switch MOS tube, the R terminal of the RS flip-flop and the gates of the two pull-down MOS tubes are all connected to the output terminal of the logic module, and the output terminal of the RS flip-flop is connected to the input terminals of the first driving module and the second driving module respectively. , the output terminals of the first driving module and the second driving module are OUTA pins and OUTB pins respectively, and the source of the switch MOS tube is connected to the RAMP pin. The first driving module and the second driving module are respectively used to drive the main switch tube N1 and the active clamp switch tube P1, and the OUTA pin and the OUTB pin are outputs in the same phase.

The first to fourth comparators are all used to control the shutdown of the control chip IC, wherein the forward input terminals of the first and second comparators are connected to the RAMP pin, and the reverse input terminal of the first comparator is connected to the COMP pin , the reverse input terminal of the second comparator is connected to the 3.5V reference voltage, the forward input terminals of the third comparator and the fourth comparator are respectively connected to the CS1 pin and the CS2 pin, the third comparator and the fourth comparator The reverse input terminals are connected to the 0.5V reference voltage, the output terminals of the first to fourth comparators are connected to the input terminal of the OR gate, the output terminal of the OR gate is connected to the input terminal of the logic module, and the third comparator and the fourth comparator are connected to the input terminal of the logic module. The positive input terminals of the device are respectively connected to the sources of the two pull-down MOS tubes, and the drains of the two pull-down MOS tubes are grounded.

The first comparator is a loop comparator, and RAMP is the voltage obtained by the VIN power supply charging the first external capacitor C1 through the first external resistor R1, which is a ramp voltage. When the RAMP voltage is higher than the COMP voltage, the control chip is controlled. IC shuts down. The second comparator is a volt-second clamp comparator, which limits the peak value of the RAMP ramp voltage to 3.5V. When the RAMP reaches 3.5V, it will be reset immediately, so the waveform of the RAMP voltage is a triangle wave as shown in the figure. The third comparator is an overcurrent protection comparator for the main switch branch, and the fourth comparator is an output voltage undervoltage protection comparator. Among them CS1 and CS2 will be pulled down NMOS reset after the end of each switch.

Furthermore, the main switch tube N1 is selected from NMOS tube, and the active clamp switch tube P1 is selected from PMOS tube.

Further, the isolation module EA&Isolation is composed of TL431 and optocoupler.

Further, the first synchronous rectifier N2 and the second synchronous rectifier N3 are both NMOS transistors.

Specifically, the capacitor pump C3 and the second diode D2 are used to turn on or off the active clamp switch P1. For example, when the ICOUTB pin of the control chip is output at a high level, the capacitor pump C3 and the second diode pass through the capacitor pump C3 and the second diode. D2 raises the gate terminal (gate terminal) of the active clamp switch P1 to 0.7V. For the active clamp switch P1, the Source voltage is 0V, the Gate voltage is 0.7V, and the active clamp switch P1 is turned off When the ICOUTB pin of the control chip is output at a low level, the gate terminal of the active clamp switch P1 can be reduced to –VCC (usually -8V ~ -15V) through the capacitor pump C3, and the active clamp switch P1 is turned on.

It works as follows:

First, let's look at the topology of the entire circuit:

In the conduction stage of the main switch tube N1, the active clamp switch tube P1 is turned off, the leakage voltage of the main switch tube N1 is almost zero, the voltage of the lower plate of the active clamp capacitor C5 is -V _C5 , the original The side-winding current keeps increasing, and the RAMP ramp voltage keeps increasing. On the secondary side, the winding Ls is positive and negative, and the voltage at both ends is:

Np and Ns are the turns of the primary and secondary windings, respectively. The first synchronous rectifier N2 is turned on, the second synchronous rectifier N3 is turned off, the winding power supply charges the output inductor L, and the winding power supply, the output inductor L, the output load, and the first synchronous rectifier N2 form a loop.

After the main switch N1 is turned off, the active clamp switch P1 is turned on, and the winding Lp current charges the parasitic capacitance of the main switch N1. Before the leakage voltage of the main switch N1 rises to VIN, the Lp current continues to increase. , when the leakage voltage of the main switch tube N1 is higher than VIN, the electromotive force of Lp is reversed, and the current direction is from the power supply VIN through Lp, the active clamp capacitor C5, and the active clamp switch tube P1 to the ground, and the current gradually decreases. The source clamp capacitor C5 has an almost zero lower plate voltage and an upper plate voltage of V _C5 . On the secondary side, the lower part of the winding Ls is positive and the upper part is negative, the first synchronous rectifier N2 is turned off, the second synchronous rectifier N3 is turned on, and the electromotive force of the output inductor L is reversed and discharged to provide energy for the output.

Therefore, for the secondary side, it is actually a BUCK structure, and the output voltage can be expressed as:

D is the duty cycle. According to the volt-second rule, the voltage of the active clamp capacitor C5 can be expressed as:

Resistors R6 and R7 form a sampling network for outputting VOUT. If VOUT is low, the COMP pull-down current of the optocoupler component to the control chip IC will become lower, and the COMP voltage will increase, resulting in an increase in the system duty cycle and transmitting more energy to the output. , the VOUT voltage will rise, thus realizing the constant voltage loop, and vice versa.

Second, from the control chip IC:

After the VIN power supply is powered on, the regulator module is used to generate a medium voltage power supply VCC for the control chip IC, usually 8~15V. This power supply is mainly used for driving. The VCC power supply passes through the LDO/BIAS/UVLO module to generate each reference, bias and enable. , after the enable is generated, other modules can work. The conduction of one switching cycle is controlled by the oscillator (such as the falling edge switch conduction). After the switch is turned on, the RAMP voltage starts to rise with a ramp. When the RAMP voltage rises to the COMP voltage, the first comparator turns over and controls the switch. After the first comparator is turned off, the RAMP voltage will continue to rise. When the RAMP rises to 3.5V, the second comparator is turned over, and the RAMP voltage is reset by logic control. After the switch is turned off, the next falling edge of the oscillator controls the next switch on. During the on-time of the switch, CS1 samples the main switch current, and its voltage value will continue to rise. CS2, as the sampling signal of COMP voltage, is used to sample whether the COMP voltage of the whole system is too high, and if it is too high, the control chip IC switch will be turned off.

As mentioned above, the control chip IC is turned off through the comparison between RAMP and COMP, but when the COMP voltage is higher than 3.5V, the control chip IC can only be turned off by the inversion of the second comparator. The inversion of the second comparator is actually The maximum on-time (Ton_max) is controlled, so Ton_max is actually determined by the external resistor and capacitor of the RAMP pin, which can be obtained from the charging and discharging principle of the capacitor:

VIN*Ton_max=3.5*R1*C1

It can be seen from the formula that when VIN is constant, the maximum on-time (or duty cycle) is determined by the external first external resistor R1 and the first external capacitor C1, so the system duty cycle D can be greater than 0.5, which makes the transformer design A large turns ratio can be achieved. In connection with the voltage formula of the active clamp capacitor C5 mentioned above, the maximum voltage of the active clamp capacitor C5 is easy to control. Therefore, in the selection of the main switch N1, the active clamp switch P1 and the active clamp When the capacitor C5 is used, it can be selected according to the pressure resistance requirements, which is economical and safe.

Figure 2 shows the waveforms of the main signals, which are the COMP waveform, the RAMP waveform, the Drain end waveform of the main switch N1, the current ILp waveform of the primary winding, and the current waveform of the active clamp capacitor C5. The COMP voltage is lower than 3.5V, and the control chip IC is turned off by the comparison of the RAMP and COMP voltages.

From t0 to t1: the control chip IC starts to conduct, and the RAMP voltage starts to ramp up from 0V. Although the main switch N1 is in the on state and the Drain voltage is 0V, at this time, the electromotive force of the primary winding is positive and negative, and the current path is From the parasitic diode of the main switch tube N1 to the primary winding, and then to the VIN power supply, the current is gradually reduced;

t1~t2: After the primary winding current drops to 0, the current path is from the power supply VIN through the primary winding, and then to the main switch tube N1. At this time, the current continues to rise. During this period, the RAMP voltage is also rising until the RAMP voltage exceeds the COMP voltage, the main switch N1 is turned off, and the primary winding current rises to the highest value ILp_max;

t2~t3: The main switch N1 is turned off, and the active clamp switch P1 is turned on. Since the primary winding current cannot change abruptly, the winding current will continue to flow. At this time, the current path is from the VIN power supply through the primary winding to the The source clamp capacitor C5, and then to the active clamp switch tube P1, the current on the winding is the current on the capacitor. For the primary winding, the upper end voltage is VIN and the lower end voltage is VC5, usually VC5 will be greater than VIN, so the winding electromotive force is negative on the top and positive on the bottom, and the current will gradually decrease;

t3~t4: At the time of t3, the primary winding current decreases to 0, the electromotive force of the primary winding is still positive up and down, and the current path is from the active clamp switch P1 to the active clamp capacitor C5, and then through the primary winding. To the VIN power supply, the current shows an increasing trend;

t4~t5: At the time of t5, the main switch N1 is turned on, and the active clamp switch P1 is turned off. Since the current cannot be abruptly changed in the primary winding, a new current path is generated, and the current flows from the parasitic diode off of the main switch to the primary winding. , and then to the VIN supply; thus repeating a new switching cycle.

From the waveform in Figure 2, the voltage at the Drain terminal of the main switch tube N1 shows a regular square wave shape, that is, the voltage across the primary winding has a regular square wave shape in each cycle, so the voltage at both ends of the secondary winding has a regular square wave shape. A regular square wave is generated. For the first synchronous rectifier N2 and the second synchronous rectifier N3, the square wave voltage of the secondary winding can be used for driving, and there is no need to specially design a synchronous rectification driving circuit, which simplifies the design and reduces the cost.

The technical means disclosed in the solution of the present invention are not limited to the technical means disclosed in the above embodiments, but also include technical solutions composed of any combination of the above technical features. It should be pointed out that for those skilled in the art, without departing from the principle of the present invention, several improvements and modifications can be made, and these improvements and modifications are also regarded as the protection scope of the present invention.

Claims (10)

1. A forward active clamp drive circuit, characterized by: the positive voltage regulator comprises a control chip, a forward transformer, a main switching tube, an active clamping capacitor, a first synchronous rectifier tube, a second synchronous rectifier tube, an output inductor, an isolation module, an output capacitor and a VIN pin of the control chip, wherein two ends of a primary winding of the forward transformer are respectively connected with the VIN power supply and a drain electrode of the main switching tube, two ends of a secondary winding of the forward transformer are respectively connected with a first synchronous rectifier tube and a second synchronous rectifier tube, two ends of the output inductor are respectively connected with the secondary winding of the forward transformer and a circuit output end VOUT, the output capacitor is connected between the circuit output end and the ground in series, the circuit output end is connected with a COMP pin and a CS2 pin of the control chip through the isolation module, a grid electrode of the main switching tube is connected with an OUTA pin of the control chip, a source electrode of the main switching tube is connected with a CS1 pin of the control chip, an anode of the active clamping capacitor is connected with the drain electrode, the grid electrode of the active clamping switch tube is connected with an OUTB pin of the control chip, the drain electrode of the active clamping switch tube is grounded, a GND pin of the control chip is grounded, a first external resistor and a first external capacitor are connected between a VIN power supply and the ground in series, a RAMP pin of the control chip is connected between the first external resistor and the first external capacitor, and a second external resistor is connected between an RT pin of the control chip and the ground in series.

2. The forward active clamp driving circuit according to claim 1, further comprising a current sampling resistor, first and second voltage dividing resistors, an output sampling network, a capacitor pump, a second external capacitor, a third external capacitor, first and second diodes, wherein the current sampling resistor is disposed in the main switch branch, specifically, the current sampling resistor is connected in series between the source of the main switch tube and ground, the CS1 pin of the control chip is connected between the source of the main switch tube and the current sampling resistor, the first and second voltage dividing resistors are voltage dividing resistors of the COMP pin voltage of the control chip, one end of the first and second voltage dividing resistors is connected to the output end of the isolation module, the other end is grounded, the COMP pin of the control chip is connected between the output end of the isolation module and the first voltage dividing resistor, the CS2 pin of the control chip is connected between the first and second voltage dividing resistors, the output sampling network is connected between the input end of the isolation module and the output end of the circuit, the anode of the capacitor pump is connected with the OUTB pin of the control chip, the cathode of the capacitor pump is connected with the grid electrode of the active clamping switch tube, the second externally-hung capacitor is connected between the VCC pin of the control chip and the ground in series, the third externally-hung capacitor is connected between the COMP pin of the control chip and the ground in series, the first diode is connected between the VCC pin of the control chip and the auxiliary winding coupled with the output inductor in series, and the second diode is connected between the grid electrode and the drain electrode of the active clamping switch tube in series.

3. A positive active clamp driving circuit as claimed in claim 2, wherein the control chip is internally provided with a voltage regulation module, an internal power/bias/enable module, a first and a second driving modules, an oscillator, a switching MOS transistor, a logic module, an RS trigger, a first to a fourth comparators, an OR gate, and two pull-down MOS transistors, wherein VIN pin is connected with the input end of the voltage regulation module, the output end of the voltage regulation module is connected with a VCC pin and the internal power/bias/enable module, the internal power/bias/enable module supplies power, enables and biases to the modules in the control chip, VCC supplies power to the first and the second driving modules, the input end of the oscillator is connected with an RT pin, the oscillator determines the switching frequency of the control chip, the output end of the oscillator is connected with the input end of the logic module and the S end of the RS trigger, the gate of the switch MOS tube, the R end of the RS trigger and the gates of the two pull-down MOS tubes are all connected with the output end of the logic module, the output end of the RS trigger is respectively connected with the input ends of the first drive module and the second drive module, the output ends of the first drive module and the second drive module are respectively connected with an OUTA pin and an OUTB pin, the source electrode of the switch MOS tube is connected with a RAMP pin, the forward input ends of the first comparator and the second comparator are connected with the RAMP pin, the reverse input end of the first comparator is connected with a COMP pin, the reverse input end of the second comparator is connected with a 3.5V reference voltage, the forward input ends of the third comparator and the fourth comparator are respectively connected with a CS1 pin and a CS2 pin, the reverse input ends of the third comparator and the fourth comparator are respectively connected with a 0.5V reference voltage, the output ends of the first comparator and the fourth comparator are respectively connected with the input end of an OR gate, the output end of the OR gate is connected with the input end of the logic module, the forward input ends of the third comparator and the, the drains of the two pull-down MOS tubes are grounded.

4. A forward active clamp driver circuit as claimed in any one of claims 1 to 3 wherein said VIN supply is of a value in the range 30 to 100V and said VCC supply is of a value in the range 8 to 15V.

5. The positive active clamp driver circuit of claim 4, wherein the input voltage to the RAMP pin of the control chip is a RAMP voltage, and the peak value of the RAMP RAMP voltage is 3.5V.

6. A forward active clamp drive circuit as claimed in claim 5 wherein said main switching transistor is NMOS transistor and said active clamp switching transistor is PMOS transistor.

7. A forward active clamp driver circuit as claimed in claim 6 wherein said isolation module is comprised of T L431 and optocouplers.

8. The forward active clamp driver circuit of claim 7 wherein said first and second synchronous rectifiers are NMOS transistors.

9. The positive active clamp driver circuit of claim 8, wherein the duty cycle of the circuitry is determined by the values of the first externally hanging resistor and the first externally hanging capacitor when the VIN power supply is constant, and the system duty cycle can be greater than 0.5.

10. The forward active clamp driver circuit of claim 9 in which the first comparator is a loop comparator, the second comparator is a volt-second clamp comparator, the third comparator is a main switch branch over-current protection comparator, and the fourth comparator is an output voltage under-voltage protection comparator.

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