CN111355367A - Power supply controller with frequency jittering effect and related control method - Google Patents

Abstract

The invention provides a power supply controller with a frequency jittering effect and a related control method, which are suitable for a power supply converter. The power controller comprises a PWM signal generator and a jitter frequency generator. The PWM signal generator controls a power switch to generate a plurality of continuous switching cycles. In each switching period, the PWM signal generator controls a peak value to regulate the output power. The peak value may represent an inductor current flowing through the inductor element. The jitter frequency generator is connected to the PWM signal generator for changing the peak value. The dither generator causes a peak variation between every two consecutive peaks. The peak variation has a sign and an intensity. The dither generator causes the symbol to be switched on and off cycle by cycle.

Description

Power supply controller with frequency jittering effect and related control method

technical field

The present invention generally relates to the switching frequency of switching power supplies, and more particularly, to related devices and techniques for dithering the switching frequency.

Background technique

In switching power supplies, quasi-resonance (QR) mode operation used in flyback power converters is a popular power supply operation method in the power supply industry. The QR operation mode can perform valley switching, so that the power switch is turned on at the signal valley of its drain-source voltage, reducing switching losses and improving conversion efficiency.

FIG. 1 shows a flyback power converter 100 operating in a QR mode. The bridge rectifier 102 rectifies the alternating current V _AC provided by the mains network into an input power V _IN on the input power line IN and an input ground power on the ground power line GND. The input ground supply is treated as 0 voltage on the primary side. The transformer TF is an inductive element, and includes a main winding PRI, a secondary winding SEC, and an auxiliary winding AUX that are inductively coupled to each other. As shown in Figure 1, the transformer TF provides DC isolation between the primary side and the secondary side. The main winding PRI and the auxiliary winding AUX are located on the primary side, and are connected to the ground power line GND and the input power line IN by DC connection. The secondary side winding SEC is located on the secondary side and can provide the energy required by the output power line OUT and the output ground power line OGND.

As shown in FIG. 1 , the main winding PRI, the power switch MN, and the current detection resistor RCS are connected in series between the input power line IN and the ground power line GND. The resistor RD is connected between the current detection terminal CS and the current detection resistor RCS. The capacitor CD is connected between the current detection terminal CS and the grounding power line GND.

The power supply controller 104 provides the PWM signal S _DRV to control the power switch MN, thus causing a change in the voltage across the main winding PRI, and also causing an alternating voltage V _{SEC on the secondary winding SEC} . After the AC voltage V _SEC is rectified, an output power V _OUT is generated on the output power line OUT on the secondary side, and the output ground power is located on the output ground power line OGND. The output power supply V _OUT powers the load 106 . The output ground supply is treated as 0 voltage on the secondary side. The state of the output power V _OUT can be transmitted to the power controller 104 on the primary side through a photo-coupler (not shown) or the auxiliary winding AUX, which controls the PWM signal S _DRV accordingly to regulate the output power supply V _OUT .

The power supply controller 104 can detect the cross voltage V _AUX on the auxiliary winding AUX through the feedback terminal FB and the resistors R1 and R2 , so as to know the appearance of a signal valley, realize the QR operation mode, and perform valley switching.

Figure 2 shows some of the signal waveforms in Figure 1 . The PWM signal S _DRV turns on the power switch MN at the turn-on time T _ON . The current-sense voltage, V _CS , across the current-sense resistor RCS, rises as the primary winding PRI is charged. During the turn-on time T _ON , the cross-voltage V _AUX reflects the input power V _IN to an approximately fixed negative voltage. After the turn-on time T _ON , the power switch MN is turned off, and the cross-voltage V _AUX will oscillate after a period of demagnetization time T _DEM to generate signal valleys VA1 , VA2 , VA3 and so on. The power controller 104 can design the next turn-on time T _ON only when the first signal trough occurs after the blanking time T _BLNK . The shadowing time T _BLNK may vary with the load 106 .

In order to prevent electromagnetic interference (EMI), the switching frequency of the flyback power converter needs to be dispersed in the frequency spectrum, and try not to fix one or several frequencies together. One method is to make the switching frequency jitter a little when the load is fixed, and change it in a small range. This technique is called frequency jittering.

A frequency jittering method adopted by the power controller 104 is to jitter the masking time T _BLNK , so that the masking time T _BLNK changes slightly with the progress of the switching cycle, as shown in FIG. 2 . However, as shown in Fig. 2, a slight change in the blocking time T _BLNK causes the next turn-on time T _ON to start approximately at the signal trough VA2 or VA3, so there are actually only two switching periods T _CYC1 and T _CYC2 . This means that the switching frequency of the flyback power converter 100 is only located in the vicinity of two fixed frequencies in the frequency spectrum, and the effect of preventing EMI is not ideal.

SUMMARY OF THE INVENTION

An embodiment of the present invention provides a power controller suitable for a power converter, which has an inductive element and provides an output power. The power controller includes a PWM signal generator and a frequency jitter generator. The PWM signal generator controls a power switch to generate several consecutive switching cycles. In each switching cycle, the PWM signal generator controls a peak value for regulating the output power. The peak value may represent an inductive current flowing through the inductive element. The frequency jitter generator is connected to the PWM signal generator for changing the peak value. The frequency jitter generator makes a peak change between every two consecutive peaks. The peak variation has a sign and an intensity. The frequency jitter generator causes the symbol to be switched one switching cycle after another switching cycle.

An embodiment of the present invention provides a control method suitable for a power converter that provides an output power. The control method includes: controlling a power switch according to a compensation voltage and a current detection voltage to generate Several continuous switching cycles are used to regulate the output power supply, wherein, in each switching cycle, the current detection voltage has a peak value; a dither current is provided to change the peak value, and there is a peak value between every two continuous peak values change, the peak change has a sign and an intensity; and, change the dither current so that the sign switches switch cycle by switch cycle.

Description of drawings

Figure 1 shows a flyback power converter operating in QR mode.

Figure 2 shows some of the signal waveforms in Figure 1 .

FIG. 3 is a power controller implemented in accordance with the present invention.

FIG. 4A shows the signal waveforms of the PWM signal S _DRV , the dither current I _JTR and the current detection voltage V _CS .

FIG. 4B enlargedly shows the signal waveforms of the four continuous switching periods TCYC1 , TCYC2 , TCYC3 , and TCYC4 in FIG. 4A .

FIG. 5 shows the frequency jitter generator 204 by way of example.

FIG. 6 shows some signal waveforms in the frequency jitter generator 204 .

FIG. 7 shows a power supply controller 300 implemented in accordance with the present invention.

FIG. 8 shows the frequency jitter generator 204a.

FIG. 9 shows some signal waveforms in the frequency jittering generator 204a of FIG. 8 .

FIG. 10 shows the frequency jitter generator 204b.

FIG. 11 shows some signal waveforms in the frequency jitter generator 204b of FIG. 10 .

【Symbol Description】

100 Flyback Power Converter

102 Bridge Rectifier

104 Power Controller

106 loads

200 Power Controller

202 PWM signal generator

204, 204a, 204b frequency jitter generator

206 Valley Detector

208 Output detector

210 Transconductor

212 Shading Time Generator

214 logic gates

216 SR flip-flop

218 Attenuator

220 Comparator

222 drives

262 Triangle Wave Generator

264 Voltage Current Converter

266, 266b multiplexer

268 Divide by two circuit

268a Divide by Four Circuits

270 Range Controller

300 Power Controller

304 Frequency jitter generator

306 Basic frequency jittering signal generator

308 carrier frequency generator

310 Multiplier

312 Adder

AUX auxiliary winding

CCOM compensation capacitor

CD capacitor

CS current detection terminal

CT capacitance

DRV driver

f _CYC-JIT jitter frequency

_fMOD carrier frequency

_fSW switching frequency

FB feedback terminal

GND ground power line

ID discharge current source

I _JTR Jitter Current

IN input power cord

I _PRI inductor current

I _SINK sink current

I _SOURCE current source

IS charge current source

MN power switch

OGND output ground power line

OUT output power cord

PRI main winding

R1, R2 resistance

RCS current sense resistor

RD resistance

S _1/2 divide by two clock

S _1/4 divided by four clocks

S _BLNK masking signal

S _DRV PWM signal

SEC secondary side winding

S _GATE gate signal

S _JR Jitter Signal

SJ _JIT basic frequency jittering signal

SJ _MOD carrier signal

T _{BLNK Shading} Time

T _CYC1 , T _CYC2 switching cycle

T _CYC-JIT jitter period

TCYC1, TCYC2, TCYC3, TCYC4

switching cycle

T _DEM demagnetization time

TF transformer

T _ON ON time

V _AC alternating current

V _AUX Overvoltage

VA1, VA2, VA3 signal valley

V _COM , V _COMP-R compensation voltage

V _CS current sense voltage

V _PK-D2 , V _PK-D3 , V _PK-D4 peak changes

V _CS-PEAK , V _CS-PEAK1 , V _CS-PEAK2 , V _CS-PEAK3

peak

V _IN input power

V _OUT output power

V _REF target reference voltage

_VSAM sampling voltage

V _SEC AC Voltage

V _TOP upper limit voltage

V _TRI triangle wave signal

Detailed ways

In the present specification, there are some identical symbols, which represent elements having the same or similar structure, function and principle, which can be inferred by those skilled in the art based on the teaching of the present specification. For the sake of brevity of the description, elements with the same symbols will not be repeated.

FIG. 3 is a power controller 200 implemented in accordance with the present invention, which replaces the power controller 104 of FIG. 1 in a power converter of one embodiment. The power controller 200 includes a PWM signal generator 202 and a frequency jitter generator 204 .

The PWM signal generator 202 controls the power switch MN through the driving terminal DRV to generate several continuous switching cycles. According to the compensation voltage V _COM and the current detection voltage V _CS , the PWM signal generator 202 controls the peak value V _CS-PEAK of the current detection voltage V _CS in each switching cycle through the attenuator 218 and the comparator 220 , thereby Regulates the voltage or current of the output power V _OUT .

The PWM signal generator 202 includes a valley detector 206, an output detector 208, a transconductor 210, a shadow time generator 212, a logic gate 214, an SR flip-flop 216, a driver 222, an attenuator 218 and comparator 220.

The valley detector 206 detects the cross-voltage V _AUX on the auxiliary winding AUX through the feedback terminal FB, and generates a corresponding pulse to the logic gate 214 when a signal valley appears about the cross-voltage V _AUX . For example, when the cross voltage V _AUX drops below 0V, it indicates that a signal valley is about to appear, so after a delay, the valley detector 206 provides a pulse to the logic gate 214 .

The output detector 208 detects the voltage of the output power supply V _OUT on the secondary side through the feedback terminal FB and the auxiliary winding AUX. For example, during the demagnetization time _TDEM , the cross voltage V _AUX roughly reflects the voltage of the output power V _OUT , which can be detected by the output detector 208 to generate the sampling voltage V _SAM accordingly. The transconductor 210 compares the sampling voltage V _SAM with the target reference voltage V _REF to charge and discharge the compensation capacitor CCOM to generate the compensation voltage V _COM .

According to the compensation voltage V _COM , the shadowing time generator 212 generates a shadowing signal S _BLNK , which controls the logic gate 214 to determine the shadowing time T _BLNK . The logic gate 214 blocks any pulses from the valley detector 206 until the blanking time T _BLNK has expired. Only after the blanking time T _{BLNK is} over, the pulse generated by the logic gate 214 can set the SR flip-flop 216 so that the gate signal S _GATE is logically 1 . At this time, the driver 222 generates the PWM signal S _DRV with the same logic value according to the gate signal S _GATE , turns on the power switch MN, and also starts an on time T _ON in a new switching cycle. The shadowing time generator 212 makes each switching period not less than the shadowing time T _BLNK .

The on-time T _ON may begin when a signal trough found by the trough detector 206 occurs. Therefore, the power controller 200 can be a QR controller, which performs valley switching.

During a turn-on time T _ON , the current sense voltage V _CS increases linearly, which also causes the voltage of the non-inverting input terminal of the comparator 220 to increase. The attenuator 218 provides the compensation voltage V _COMP-R according to the compensation voltage V _COM , which is located at the inverting input terminal of the comparator 220 . When the voltage at the non-inverting input terminal of the comparator 220 is greater than the voltage at the inverting input terminal, the comparator 220 resets the SR flip-flop 216 so that the gate signal S _GATE is logically 0 and passes the PWM signal S having the same logical value _DRV , turns off the power switch MN, ends the on-time T _ON , and starts the off-time T _OFF .

As soon as the off time T _OFF is entered, no current flows through the power switch MN, so the current detection voltage V _CS drops rapidly to 0V, so a peak value V _CS-PEAK is generated, which represents the maximum value of the current detection voltage V _CS in the current switching cycle. , which is also approximately the maximum value of the inductor current flowing through the primary winding PRI. Therefore, the PWM signal generator 202 controls the peak value V _CS-PEAK of the current detection voltage V _CS in each switching cycle according to the compensation voltage V _COM .

It can be found from FIG. 3 and FIG. 1 that the PWM signal generator 202 provides a negative feedback control, and the goal is to make the sampling voltage V _SAM approximately equal to the target reference voltage V _REF , thereby regulating the voltage of the output power supply V _OUT to make it equal to A value corresponding to the target reference voltage V _REF .

The level of the compensation voltage V _COM approximately represents the size of the load 106 . Generally speaking, the larger the load 106 is, the higher the compensation voltage V _COM is, the shorter the blocking time T _BLNK is, and the higher the peak value V _CS-PEAK of the current detection voltage V _CS is.

The frequency jitter generator 204 varies the peak value V _CS-PEAK such that there is a peak change between every two consecutive peak values V _CS-PEAK . The peak variation has a sign and a magnitude. The sign shows whether the peak change is positive or negative. Intensity is the absolute value of the peak change. The frequency jitter generator 204 switches one switching cycle by one switching cycle (switching-cycle by switching-cycle) so that the symbols are switched. The peak value change is positive in one switching cycle, negative in the next switching cycle, and positive in the next switching cycle, alternately changing.

The frequency jitter generator 204 provides the jitter current I _JTR , and through the current detection terminal CS, the peak value V _CS-PEAK can be changed. When the jitter current I _JTR is a source current, the jitter current I _JTR flows out of the current detection terminal CS and passes through the resistor RD, so that the voltage of the non-inverting input terminal of the comparator 220 is higher than the current detection voltage V _CS . Therefore, sourcing the current reduces the peak V _CS-PEAK compared to when the jitter current I _JTR is 0. On the contrary, when the jitter current I _JTR is a sink current, the peak value V _CS-PEAK will rise.

FIG. 4A shows the signal waveforms of the PWM signal S _DRV , the dither current I _JTR and the current detection voltage V _CS . The PWM signal S _DRV switches the power switch MN, resulting in several consecutive switching cycles. The jitter current I _JTR alternately switches to a source current greater than 0A and a sink current less than 0A with the switching cycle. If the jitter current I _JTR is a source current in one switching cycle, then the jitter current I _JTR in the next switching cycle will be a sink current, and vice versa. As shown in FIG. 4A , the jitter current I _JTR changes periodically with a jitter period T _CYC-JIT .

FIG. 4B enlargedly shows the signal waveforms of the four continuous switching periods TCYC1 , TCYC2 , TCYC3 , and TCYC4 in FIG. 4A .

In the switching period TCYC1, the jitter current I _JTR is less than 0A, which is a sink current. At this time, the jitter current I _JTR flows from the resistor RD through the current detection terminal CS of the power controller 200 and flows to the ground power line GND. The switching period TCYC1 produces the peak V _CS-PEAK1 .

In the switching period TCYC2, the jitter current I _JTR is greater than 0A, which is a pulling current. At this time, the jitter current I _JTR flows through the current detection terminal CS of the power controller 200 , passes through the resistor RD and the current detection resistor RCS, and flows to the grounding power line GND. The switching period TCYC1 produces the peak V _CS-PEAK2 .

As shown in FIG. 4B , because the switching periods TCYC1 and TCYC2 use source current and sink current, respectively, the difference between the peak value V _CS-PEAK2 and the peak value V _CS-PEAK1 is the peak change V _PK-D2 , which is a negative value. Therefore, the sign of the peak change V _{PK -D2} is negative, and the intensity of the peak change V _PK-D2 is the absolute value of the peak change V PK-D2.

By analogy, the peak change V _PK-D3 , the peak change V _PK-D4 , etc. can be obtained, as shown in FIG. 4B . The sign of the peak change V _PK-D3 is positive, while the sign of the peak change V _PK-D4 is negative. The sign of the peak change, with the switching cycle, constantly switching between positive and negative. As can be appreciated from FIG. 4B, the frequency jitter generator 204 provides the jitter current I _JTR such that the sign of the peak change, switching cycle after switching cycle, is switched.

FIG. 5 shows an example of the frequency jitter generator 204 , which includes a triangular wave generator 262 , a voltage-to-current converter 264 , a divide-by-two circuit 268 , and a multiplexer 266 . FIG. 6 shows some signal waveforms in the frequency jitter generator 204 .

The triangular wave generator 262 has a charging current source IS, a discharging current source ID, a capacitor CT and a range controller 270 to generate a triangular wave signal V _TRI , which has a jitter period T _CYC-JIT and a jitter frequency of f _CYC-JIT (=1 /T _CYC-JIT ). The triangular wave generator 262 periodically changes the intensity of the jitter current I _JTR with the jitter period T _CYC-JIT . As shown in FIG. 6 , when the triangular wave signal V _TRI rises above the upper limit voltage V _TOP , the range controller 270 stops the charging current source IS from charging the capacitor CT, and makes the discharging current source ID start to discharge the capacitor CT. When the triangular wave signal V _TRI drops and exceeds the lower limit voltage V _BTM , the range controller 270 stops the discharge current source ID to discharge the capacitor CT, so that the charging current source IS starts to charge the capacitor CT.

The voltage to current converter 264 includes several current mirrors. According to the triangular wave signal V _TRI , the voltage-to-current converter 264 generates a source current I _SOURCE and a sink current I _SINK .

The divide-by-two circuit 268 uses the gate signal S _GATE- provided by the PWM signal generator 202 as a switching clock to generate a divide-by-two clock S _1/2 . The frequency of the divide-by-two clock S _1/2 is half the frequency of the gate signal S _GATE .

The multiplexer 266 alternately selects the source current I _SOURCE and the sink current I _SINK as the jitter current I _JTR according to the divide-by-two clock S _1/2 to change the peak value V _CS-PEAK . Thus, in one switching cycle, the multiplexer 266 selects the source current I _SOURCE , and the dither current I _JTR is positive; in the next switching cycle, the multiplexer 266 selects the sink current I _SINK , and the dither current I _JTR is negative. It can be seen from FIG. 6 that the sign of the jitter current I _JTR is switched one switching cycle after another switching cycle.

The sign of the jitter current I _JTR switches with the switching period, which can make the effect of frequency jitter more obvious. The negative feedback control provided by the PWM signal generator 202, when the load 106 is fixed and there is no jitter current I _JTR , should keep the peak value V _CS-PEAK at about a constant value, assuming V _EXP , in order to regulate the output power _VOUT . If the jitter current I _JTR changes the peak value V _CS-PEAK in one switching cycle, so that it leaves the fixed value V _EXP , then in the next switching cycle, if the jitter current I _JTR does not change, the negative feedback control should make The peak value V _CS-PEAK approaches the constant value V _EXP , reducing the effect of frequency jitter. In the embodiment of the present invention, in the next switching period, the sign switching of the jitter current I _JTR can ensure that the peak value V _CS-PEAK of the next switching period is further away from the fixed value V _EXP , so that the effect of frequency jitter is more obvious.

In FIG. 3 , the jitter current I _JTR affects the peak value V _CS-PEAK through the current detection terminal CS or the non-inverting input terminal of the comparator 220 , but the invention is not limited thereto. In another embodiment of the present invention, the frequency jitter generator 204 provides the jitter current I _JTR to the inverting input of the comparator 220 , which flows through the attenuator 218 to affect the peak value V _CS-PEAK .

Although a flyback power converter operating in the QR mode is used as an example to illustrate the present invention, the present invention is not limited thereto. For example, the present invention can also be applied to a buck converter, a boost converter, or a buck-boost converter.

FIG. 7 shows the power controller 300 according to the present invention, wherein some elements or symbols are the same or similar to those in FIG. 3 , which can be known from the previous description of FIG. 3 , and will not be repeated for the sake of brevity. The power controller 300 includes a PWM signal generator 202 and a frequency jitter generator 304 . The power controller 300 can also reduce the effect of EMI.

The PWM signal generator 202 generates the PWM signal S _DRV according to the compensation voltage V _COM and the current detection voltage V _CS , which can control the power switch MN in FIG. 1 , so that the power switch MN has a switching frequency f _SW , which is the period of the switching period T _SW . reciprocal. As previously described, the compensation voltage V _COM is controlled by the transconductor 210 , which receives the sampled voltage V _SAMP from the output detector 208 . The sampled voltage V _SAMP approximately reflects the voltage of the output power supply V _OUT . Therefore, the compensation voltage V _COM is controlled by the output power V _OUT . When the power switch MN is turned on, the current sense voltage V _CS may represent the inductor current I _{PRI flowing through the main winding PRI} .

The frequency jittering generator 304 is used to provide the jittering signal S _JR , which is used to adjust the current detection voltage V _CS through the adder 312 . As described in FIG. 7, summer 312 causes the non-inverting terminal of comparator 220 to receive V _CS +KxS _JR , where K is a fixed constant. The dithering signal S _JR can slightly change the switching frequency f _SW , which can reduce the EMI of the entire power supply.

The frequency jittering generator 304 includes a basic frequency jittering signal generator 306 , a carrier frequency generator 308 and a multiplier 310 . The basic frequency jittering signal generator 306 generates a basic frequency jittering signal SJ _JIT having a jitter frequency f _CYC-JIT . Carrier frequency generator 308 generates carrier signal SJ _MOD having carrier frequency f _MOD . As shown in FIG. 7 , the multiplier 310 multiplies the carrier signal SJ _MOD by the basic frequency jittering signal SJ _JIT to generate the jittering signal S _JR . Among the jitter frequency f _CYC-JIT , the carrier frequency f _MOD , and the switching frequency f _SW , the jitter frequency f _CYC-JIT is the lowest, and the switching frequency f _SW is the highest.

The frequency jittering generator 304 in FIG. 7 may be implemented with the frequency jittering generator 204 in FIG. 5 as an example. The basic frequency jittering signal generator 306 may be the triangular wave generator 262, and the basic frequency jittering signal SJ _JIT may be the triangular wave signal V _TRI . The carrier frequency generator 308 may be the divide-by-two circuit 268, and the carrier signal SJ _MOD may be the divide-by-two clock S _1/2 . Multiplier 310 may be a combination of voltage-to-current converter 264 and multiplexer 266 . The jitter signal S _JR may be the jitter current I _JTR .

See Figure 6. When the divide-by-two clock S _1/2 is logically 1, the jitter current I _JTR (=I _TRI ) is approximately proportional to the triangular wave signal V _TRI . When the divide-by-two clock S _1/2 is logically 0, the jitter current I _JTR (=−I _TRI ) is approximately negatively proportional to the triangular wave signal V _TRI . The frequency of the divide-by-two clock S _1/2 is approximately half of the switching frequency f _SW (equal to the signal frequency of the gate signal S _GATE ). The switching frequency _fSW is greater than the frequency of the divide-by-two clock S _1/2 , and the frequency of the divide-by-two clock S _1/2 is greater than the jitter frequency f _CYC-JIT (the inverse of the jitter period T _CYC-JIT ).

The adder 312 in FIG. 7 may be the resistor RD in FIG. 3 , which is connected between the comparator 220 and the current detection resistor RCS.

The frequency jitter generator 304 in FIG. 7 is only an example, and is not intended to limit the present invention. For example, in another embodiment, the adder 312 in FIG. 7 is moved to the inverting input terminal between the comparator 220 and the attenuator 218, and the adder 312 adjusts the compensation voltage V _COMP- with the jitter signal S _{JR R} , equal to the adjusted compensation voltage V _COM . This can also have the effect of reducing EMI.

FIG. 8 shows a frequency jitter generator 204a, which may be an embodiment of the frequency jitter generator 304 in FIG. 7 . Some elements or symbols in FIG. 8 are the same or similar to those in FIG. 5 , which can be known from the previous description of FIG. 5 , and will not be repeated for the sake of brevity.

FIG. 8 replaces the divide-by-two circuit 268 in FIG. 5 with a divide-by-four circuit 268a. A divide-by-four circuit 268a provides a divide-by-four clock S _1/4 for controlling the multiplexer 266 .

FIG. 9 shows some signal waveforms in the frequency jittering generator 204a of FIG. 8 . When the divided clock S _1/4 is logically 1, the jitter current I _JTR (=I _TRI ) is approximately proportional to the triangular wave signal V _TRI . When the divided clock S _1/4 is logically 0, the jitter current I _JTR (=−I _TRI ) is approximately negatively proportional to the triangular wave signal V _TRI . The frequency of the divide-by-four clock S _1/4 is approximately one quarter of the switching frequency f _SW (equal to the signal frequency of the gate signal S _GATE ). The switching frequency _fSW is greater than the frequency of the divide-by-four clock S _1/4 , and the frequency of the divide-by-four clock S _1/4 is greater than the jitter frequency f _CYC-JIT (the inverse of the jitter period T _CYC-JIT ).

FIG. 10 shows the frequency jitter generator 204b, which may be an embodiment of the frequency jitter generator 304 in FIG. 7 . Some elements or symbols in FIG. 10 are the same or similar to those in FIG. 8 , which can be known from the previous description of FIG. 8 , and will not be repeated for the sake of brevity.

Figure 10 replaces the multiplexer 266 of Figure 8 with a multiplexer 266b. The multiplexer 266b has only one switch, which determines whether the source current I _SOURCE passes through and becomes the jitter current I _JTR .

FIG. 11 shows some signal waveforms in the frequency jitter generator 204b of FIG. 10 . When the divide-by-four clock S _1/4 is a logical 1, the jitter current I _JTR is approximately proportional to V _TRI . When the divide-by-four clock S _1/4 is logically 0, the jitter current I _JTR is approximately 0.

In another example not shown, when the divide-by-four clock S _1/4 is a logical 1, the jitter current I _JTR is about 0. When the divide-by-four clock S _1/4 is a logical 0, the jitter current I _JTR is approximately negatively proportional to V _TRI .

The carrier frequency generator 308 is not limited to be implemented only by the divide-by-two circuit 268 or the divide-by-four circuit 268a. For example, the carrier frequency generator 308 can be any frequency divider to generate the carrier frequency f _MOD according to the switching frequency f _SW , and the switching frequency f _SW is an integer multiple of the carrier frequency f _MOD . In another embodiment, the switching frequency f _SW is also greater than the carrier frequency f _MOD , but the switching frequency f _SW is a non-integer multiple of the carrier frequency f _MOD .

The above are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (16)

1. A power controller for a power converter having an inductive element for providing an output power, the power controller comprising:

a PWM signal generator for controlling the power switch to generate a plurality of continuous switching cycles, wherein, in each switching cycle, the PWM signal generator controls a peak value for regulating the output power supply, and the peak value represents the inductive current flowing through the inductive element;

a jitter frequency generator connected to the PWM signal generator for changing the peak value so that there is a peak variation between every two consecutive peak values, wherein the peak variation has a sign (sign) and a magnitude (magnitude), and the jitter frequency generator causes the sign, a switching period and then a switching period to be switched.

2. The power supply controller as claimed in claim 1, wherein the dither generator comprises a triangular wave generator to cause the intensity to vary periodically.

3. The power controller as claimed in claim 1, wherein the dither generator comprises a divide-by-two circuit for generating a divide-by-two clock according to the switching clock provided by the PWM signal generator.

4. The power supply controller of claim 3, wherein the dither generator comprises:

a triangular wave generator for generating a triangular wave signal;

a voltage-current converter for generating a source current and a sink current according to the triangular wave signal; and

a multiplexer (multiplexer) for alternately applying the pull-in current and the sink current to change the peak value according to the divided-by-two clock.

5. The power controller of claim 1, wherein the power converter comprises a current sense resistor coupled between the inductive element and a ground power line for generating a current sense voltage, the PWM signal generator controls the power switch according to the current sense voltage and a compensation voltage, and the jitter frequency generator provides a jitter current for varying the peak value.

6. The power controller of claim 1 further comprising a mask time generator for providing a mask time based on the compensation voltage, wherein the power controller causes each switching cycle to be no less than the mask time.

7. The power supply controller as claimed in claim 1, wherein the power supply controller is a quasi-resonant controller, and the power converter is enabled to perform valley switching.

8. A control method for a power converter providing an output power, the control method comprising:

controlling a power switch according to the compensation voltage and a current detection voltage to generate a plurality of continuous switching cycles for regulating and controlling the output power supply, wherein the current detection voltage has a peak value in each switching cycle;

providing a dithering current to change the peak value and make the peak value change between every two continuous peak values, wherein the peak value change has a sign and an intensity; and

the dither current is varied such that the sign switches from one switching period to the next.

9. The control method according to claim 8, comprising:

alternately switching the dither current into source current and sink current one switching cycle after another.

10. The control method according to claim 8, comprising:

providing a triangular wave signal; and

the jitter current is periodically changed according to the triangular wave signal.

11. A power controller for a power converter having an inductive element for providing an output power, the power controller comprising:

a PWM signal generator for controlling a power switch according to a compensation voltage and a current detection voltage, so that the power switch has a switching frequency, wherein the compensation voltage is controlled by the output power supply, and the current detection voltage can represent an inductive current flowing through the inductive element;

a jitter frequency generator for providing a jitter signal for adjusting one of the compensation voltage and the current detection voltage, comprising:

a basic dither signal generator for generating a basic dither signal having a dither frequency;

a carrier frequency generator for generating a carrier signal having a carrier frequency; and

a multiplier for multiplying the base dither signal and the carrier signal to generate the dither signal;

the switching frequency is greater than the carrier frequency, and the carrier frequency is greater than the jitter frequency.

12. The power supply controller as recited in claim 11 wherein the base dither signal is a triangular wave.

13. The power supply controller as claimed in claim 11, wherein the switching frequency is an integer multiple of the carrier frequency.

14. The power supply controller as recited in claim 11 wherein the dither signal is approximately proportional to the base dither signal when the carrier signal is at a first logical value and approximately proportional to the base dither signal when the carrier signal is at a second logical value.

15. The power controller as recited in claim 11 wherein the dither signal is approximately proportional to the base dither signal when the carrier signal is at a first logical value and 0 when the carrier signal is at a second logical value.

16. The power controller of claim 11, further comprising an adder for adjusting the current detection voltage with the dither signal.

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