CN111324166B

CN111324166B - Power regulator and power regulation method

Info

Publication number: CN111324166B
Application number: CN201811532731.5A
Authority: CN
Inventors: 余文华; 杨文安
Original assignee: Giga Byte Technology Co Ltd
Current assignee: Technical Steel Technology Co ltd
Priority date: 2018-12-14
Filing date: 2018-12-14
Publication date: 2021-09-03
Anticipated expiration: 2038-12-14
Also published as: CN111324166A

Abstract

The invention discloses a power regulator, which is suitable for adjusting the operating frequency of a central processing unit. The power regulator includes a power resistor, a voltage amplifier and an analog-digital converter. The power resistor is coupled to the load to generate the first voltage. The voltage amplifier is coupled to the power resistor to output the second voltage. The analog-to-digital converter is coupled to the voltage amplifier and converts the second voltage into a control signal. The analog-to-digital converter transmits a control signal to the central processing unit, and the control signal can be switched between the first level and the second level.

Description

Power regulator and power regulation method

Technical Field

The present invention relates to a power regulator, and more particularly, to a power regulator for a cpu.

Background

Based on the requirement of safety standard of electronic products, the total power consumed by the host system cannot be greater than the rated power of the transformer attached to the host system. As the demand of consumers for expanding external devices is increasing, the number of USB connection ports designed for many host systems must be increased, and correspondingly, the transformer of the host system must be designed to have a higher power rating so as to meet the safety regulations of electronic products. For example, an electronic product originally rated at 65W will have a total power of 67W due to the increased number of USB connection ports. Therefore, the 65W transformer matched with the product needs to be changed into a 95W transformer. When the host system must be equipped with a transformer with high rated power, the manufacturing cost is increased and the competitiveness is reduced. In addition, the transformer with high rated power is relatively large and is not suitable for the application of micro computer, tablet computer and thin notebook computer.

In view of the above, there is a need for an improved power regulator that addresses at least the above-mentioned shortcomings.

Disclosure of Invention

According to the power regulator and the power regulation method provided by the embodiment of the invention, the working frequency of the central processing unit of the host system can be regulated, so that the host system does not need to be matched with a transformer with high rated power, not only accords with the safety specification, but also is suitable for the application of a microcomputer, a tablet computer and a thin notebook computer.

According to an embodiment of the present invention, a power regulator for adjusting an operating frequency of a cpu is provided, and the power regulator includes a power resistor, a voltage amplifier, and an analog-to-digital converter. The power resistor is used for coupling a load and generating a first voltage. The voltage amplifier is coupled to the power resistor and outputs a second voltage. The analog-to-digital converter is coupled to the voltage amplifier and converts the second voltage into a control signal. The analog-digital converter transmits a control signal to the central processing unit, and the control signal is switched between a first level and a second level.

According to an embodiment of the present invention, a power adjusting method is provided, which is adapted to adjust an operating frequency of a cpu and is performed by a power adjuster, the power adjuster includes a power resistor, a voltage amplifier, and an analog-to-digital converter, and the power adjusting method includes: providing a voltage source; the power resistor is coupled with the load to generate a first voltage; the voltage amplifier receives the first voltage to output a second voltage; the analog-digital converter selectively converts the second voltage into a first level or a second level; and adjusting or maintaining the operating frequency of the central processing unit according to the first level or the second level.

In the power regulator and the power regulating method according to an embodiment of the present invention, after the power regulator is activated by receiving the voltage source, the power resistor may be selectively coupled to any node in the host system, and the power consumption may be monitored by a voltage level of the control command output by the power regulator. The power resistor can be coupled to a USB connection port or a source end of an external transformer entering a mainboard, so that the power resistor is very convenient and flexible to use. Because the power regulator is coupled with the load through the power resistor, when the power regulator malfunctions, a user can conclude that the malfunction is caused by the damage of the power resistor, the replacement of the power resistor is very easy, and the debugging time can be greatly reduced. No matter how large the total power consumption of the load detected by the power regulator is, the power regulator can control the operating frequency of the cpu by the control command, so that the total power consumption of the host system does not exceed the rated power of the transformer. Therefore, the host system does not need to be matched with a transformer with high rated power, so that the manufacturing cost can be reduced, and the host system is very suitable for application of a microcomputer, a tablet computer and a thin notebook computer. Furthermore, the adc has a hysteresis voltage design to avoid the oscillation condition.

The foregoing description of the present disclosure and the following detailed description are presented to illustrate and explain the principles and spirit of the invention and to provide further explanation of the invention as claimed.

Drawings

Fig. 1 is a functional block diagram of a power regulator according to a first embodiment of the invention.

Fig. 2 is a circuit architecture diagram of the power regulator of fig. 1.

Fig. 3 is a circuit architecture diagram of a power regulator according to a second embodiment of the invention.

Fig. 4 is a circuit architecture diagram of a power regulator according to a third embodiment of the invention.

Fig. 5 is a flowchart illustrating a power adjustment method according to an embodiment of the invention.

100 power regulator

10 voltage amplifier

11 first operational amplifier

111 non-inverting input terminal

112 inverting input terminal

113 output terminal

R1 first resistor

First end of T11

Second end of T12

R2 second resistor

First end of T21

Second end of T22

R3 third resistor

First end of T31

Second end of T32

R4 fourth resistor

First end of T41

Second end of T42

20 analog-to-digital converter

21 second operational amplifier

211 non-inverting input terminal

212 inverting input terminal

213 output terminal

R5 fifth resistor

First end of T51

Second end of T52

R6 sixth resistor

First end of T61

Second end of T62

R7 seventh resistor

First end of T71

Second end of T72

30 buffer circuit

31 input terminal

32 output terminal

VCC voltage source

En enable signal

RP power resistor

C capacitor

First voltage of V1

Second voltage of V2

200 central processing unit

GPO _ N pin

300 load

Detailed Description

The detailed features and advantages of the present invention are described in detail in the following embodiments, which are sufficient for anyone skilled in the art to understand the technical content of the present invention and to implement the present invention, and the related objects and advantages of the present invention can be easily understood by anyone skilled in the art according to the disclosure, claims and drawings of the present specification. The following examples further illustrate aspects of the present invention in detail, but are not intended to limit the scope of the present invention in any way.

Fig. 1 is a functional block diagram of a power regulator according to a first embodiment of the invention, and fig. 2 is a circuit architecture diagram of the power regulator of fig. 1. As shown in fig. 1 and 2, the power regulator 100 may be applied to a host system with an external transformer, such as a microcomputer, a tablet computer, or a thin notebook computer. The power regulator 100 may be disposed on a motherboard of the host system and electrically connected to the cpu 200 on the motherboard, so as to adjust the operating frequency of the cpu 200.

In the present embodiment, the BIOS chip on the motherboard is preset to provide a voltage source VCC of 5 volts to the power regulator 100 to start the power regulator 100. The power regulator 100 may include a power resistor RP, a capacitor C, a voltage amplifier 10, an analog-to-digital converter 20, and a buffer circuit 30. One end of the power resistor RP is coupled to the voltage source VCC, and the other end is connected in series with the load 300, and the capacitor C is connected in parallel with the power resistor RP. The input terminal of the voltage amplifier 10 is coupled to the power resistor RP and the capacitor C, and the output terminal of the voltage amplifier 10 is coupled to the input terminal of the analog-to-digital converter 20. The output terminal of the analog-to-digital converter 20 is coupled to the input terminal of the buffer circuit 30, and the output terminal of the buffer circuit 30 is coupled to the central processing unit 200.

In this embodiment, the load 300 may be a USB port of the host system, and the total power consumption generated by the load 300 is larger when the number of external devices coupled to the USB port of the host system is larger. As the total consumed power of the load 300 is larger, the current flowing through the power resistor RP and the first voltage V1 generated from the power resistor RP are also larger. In other embodiments, the load 300 may also be the source of the external transformer entering the motherboard. For safety, the user can select the power resistor RP with an appropriate resistance value and wattage to determine the magnitude of the current passing through the power resistor RP, for example, the wattage of the power resistor RP can be selected to be at least 1 watt and the resistance value can be at least 1m ohm.

When the external device (e.g., the detected power supply) has poor quality and causes the load 300 to generate noise, the capacitor C connected in parallel to the power resistor RP may have a function of filtering the noise. The power regulator 100 may also omit the capacitor C when the quality of the external device is good. On the other hand, the closer the capacitor C is to the voltage amplifier 10, the better the noise filtering effect is.

Since the first voltage V1 generated at the power resistor RP is usually small, the first voltage V1 must be amplified by the voltage amplifier 10 in order to fit the range that the analog-digital converter 40 can resolve. The voltage amplifier 10 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a first operational amplifier 11. The first terminal T11 of the first resistor R1 and the first terminal T21 of the second resistor R2 are coupled to the positive electrode and the negative electrode of the capacitor C, respectively, and the first terminal T31 of the third resistor R3 is coupled to the second terminal T12 of the first resistor R1 and the non-inverting input 111 of the first operational amplifier 11, respectively. The second terminal T32 of the third resistor R3 is grounded. The first terminal T41 of the fourth resistor R4 is coupled to the second terminal T22 of the second resistor R2 and the inverting input terminal 112 of the first operational amplifier 11, respectively, and the second terminal T42 of the fourth resistor R4 is coupled to the output terminal 113 of the first operational amplifier 11. The non-inverting input 111 and the inverting input 112 of the first operational amplifier 11 receive the first voltage V1, and the first operational amplifier 11 performs voltage amplification and outputs a second voltage V2 from the output 113. The resistance values of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 determine the voltage gain (R2/R1) of the voltage amplifier 30, wherein the voltage gain is preferably set when the voltage gain is greater than 200. In the present embodiment, the first resistor R1 and the second resistor R2 have the same resistance value, which may be 4.99K ohms, for example. The third resistor R3 and the fourth resistor R4 have the same resistance value, and may be 1M ohm, for example.

In one embodiment, the adc 20 may include a hysteresis circuit and the second operational amplifier 21, wherein the hysteresis circuit includes a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7. The first terminal T51 of the fifth resistor R5 is coupled to the voltage source VCC, and the second terminal T52 of the fifth resistor R5 is coupled to the first terminal T61 of the sixth resistor R6, the first terminal T71 of the seventh resistor R7, and the non-inverting input terminal 211 of the second operational amplifier 21, respectively. The second terminal T62 of the sixth resistor R6 is connected to ground. The output terminal 113 of the first operational amplifier 11 is coupled to the inverting input terminal 212 of the second operational amplifier 21. The second terminal T72 of the seventh resistor R7 is coupled to the output terminal 213 of the second operational amplifier 21. The adc 20 converts the second voltage V2 in analog format output by the voltage amplifier 10 into a control signal in digital format, and outputs the control signal via the output terminal 213 of the second operational amplifier 21, and the control signal is switchable between a first level and a second level according to the magnitude of the second voltage V2, wherein the first level is smaller than the second level.

The hysteresis circuit of the adc 20 is preset with a hysteresis upper limit threshold voltage VH and a hysteresis lower limit threshold voltage VL, and the calculation formula of the hysteresis upper limit threshold voltage VH and the hysteresis lower limit threshold voltage VL is as follows:

R7/R5 is VL/(VH-VL) (formula 1)

R6/R5 is VL/(VCC-VH) (formula 2)

Since the hysteresis upper threshold voltage VH, the hysteresis lower threshold voltage VL, the voltage source VCC, and the fifth resistor R5 are preset values, the resistance values of the sixth resistor R6 and the seventh resistor R7 can be derived according to the formulas 1 and 2. When the second voltage V2 output by the voltage amplifier 10 is less than the hysteresis lower limit threshold voltage VL, the adc 20 outputs a first control signal. When the second voltage V2 output by the voltage amplifier 10 is greater than the hysteresis upper limit threshold voltage VH, the adc 20 outputs a second control signal, and the level of the first control signal is lower than that of the second control signal. For example, the voltage value of the first control signal is zero, and the voltage value of the second control signal is VCC.

The input terminal 31 of the buffer circuit 30 is coupled to the output terminal 213 of the second operational amplifier 21, and the output terminal 32 of the buffer circuit 30 is coupled to the pin GPO _ N of the cpu 200. The buffer circuit 30 can be used to isolate the cpu 200 from the adc 20 and prevent the voltage level output to the cpu 200 from being too high. In addition, the buffer circuit 30 can also prevent other voltage sources of the cpu 200 from feeding back to the hysteresis circuit, which may affect the calculation of the hysteresis upper limit threshold voltage VH and the hysteresis lower limit threshold voltage VL.

When the adc 40 outputs the first control signal, the buffer circuit 30 may output the first control signal to the GPO _ N pin of the cpu 200, where the first control signal indicates that the total power consumption of the load 300 has reached or exceeded the preset rated power value, and at this time, the power regulator 100 commands the operating frequency of the cpu 200 to be decreased from the first operating frequency (e.g., 2.7GHZ) to the second operating frequency (e.g., 1.3GHZ), so as to decrease the operating frequency of the cpu 200 to achieve the purpose of decreasing the total power consumption of the cpu 200. However, when the GPO _ N pin goes back high, the power down action is stopped. On the contrary, when the adc 20 outputs the second control signal, the buffer circuit 30 outputs the second control signal to the pin GPO _ N of the cpu 200, and the second control signal indicates that the total power consumption of the load 300 does not reach the predetermined rated power value, and at this time, the power regulator 100 commands the operating frequency of the cpu 200 to be maintained at the first operating frequency. In other embodiments, the operating frequency of the cpu 200 may be decreased by an amount proportional to the power difference between the total power consumption of the load 300 and the rated power value.

Fig. 3 is a circuit architecture diagram of a power regulator according to a second embodiment of the invention. The difference between the embodiment of fig. 3 and the embodiment of fig. 1 is that the power regulator 100 omits the design of the buffer circuit 30, and therefore the output terminal 213 of the second operational amplifier 21 of the adc 20 is directly coupled to the GPO _ N pin of the cpu 200, thereby reducing the area of the motherboard occupied by the power regulator 100 and achieving the effect of saving the cost.

Fig. 4 is a circuit architecture diagram of a power regulator according to a third embodiment of the invention. The embodiment of fig. 4 is different from the embodiment of fig. 1 in that the positive voltage source of the power regulator 100 is not provided by the BIOS chip, and the power regulator 100 further includes a start-up circuit 40, and the start-up circuit 40 is configured to receive the enable signal En from outside the host system. When the start-up circuit 40 receives the enable signal En, it provides the voltage source VCC to the power resistor RP, the voltage amplifier 10 and the adc 20. Therefore, a user can provide voltage sources with different voltage values from the outside of the host system to the power regulator according to requirements, and the power regulator is flexible and convenient to use.

Fig. 5 is a flowchart illustrating a power adjustment method according to a first embodiment of the invention, which is suitable for adjusting the operating frequency of the cpu 200 and is executed by the power adjuster 100. In step S501, a voltage source is provided to start the power regulator 100. In step S502, the load 300 is coupled through the power resistor RP to form a first voltage V1 between two terminals of the power resistor RP. In step S503, the first voltage V1 is received by the voltage amplifier 10 to output a second voltage V2. In step S504, the adc 20 determines whether the second voltage V2 is less than the hysteresis lower limit threshold voltage VL, and if the second voltage V2 is less than the hysteresis lower limit threshold voltage VL, step S505 is executed; if the second voltage V2 is not less than the hysteresis lower limit threshold voltage VL, step S506 is executed. In step S505, the second voltage V2 in analog format is converted into the first control signal in digital format by the analog-to-digital converter 20 and the first control signal is output to the buffer circuit 30, and then step S507 is executed. In step S506, the adc 20 determines whether the second voltage V2 is greater than the hysteresis upper limit threshold voltage VH, and if the second voltage V2 is greater than the hysteresis upper limit threshold voltage VH, step S508 is executed. If the second voltage V2 is not greater than the hysteresis upper limit threshold voltage VH, that is, the second voltage V2 is between the hysteresis upper limit threshold voltage VH and the hysteresis lower limit threshold voltage VL, step S509 is executed. In step S507, the first control signal is transmitted to the cpu 200 through the buffer circuit 30 to reduce the operating frequency of the cpu 200. In step S508, the analog-to-digital converter 20 converts the second voltage V2 in analog format into the second control signal in digital format and outputs the second control signal to the buffer circuit 30, followed by step S510. In step S509, the state of the control signal output by the adc 20 last time is maintained, and the state of the control signal output by the adc is maintained at a high level if the state of the control signal output by the adc is at a high level, and the state of the control signal output by the adc is maintained at a low level if the state of the control signal output by the adc is at a low level. In step S510, a second control signal is transmitted to the cpu 200 through the buffer circuit 30 to maintain the operating frequency of the cpu 200. In other embodiments, the order of step S504 and step S506 may be interchanged.

In the power regulator and the power regulating method according to an embodiment of the present invention, after the power regulator is activated by receiving the voltage source, the power resistor may be selectively coupled to any node in the host system, and the power consumption may be monitored by a voltage level of the control signal output by the power regulator. The power resistor can be coupled to a USB connection port or a source end of an external transformer entering a mainboard, so that the power resistor is very convenient and flexible to use. Because the power regulator is coupled with the load through the power resistor, when the power regulator malfunctions, a user can conclude that the malfunction is caused by the damage of the power resistor, the replacement of the power resistor is very easy, and the error time can be greatly reduced. No matter how large the total power consumption of the load detected by the power regulator is, the power regulator can control the operating frequency of the cpu through the control signal, so that the total power consumption of the host system does not exceed the rated power of the transformer. Therefore, the host system does not need to be matched with a transformer with high rated power, so that the manufacturing cost can be reduced, and the host system is very suitable for application of a microcomputer, a tablet computer and a thin notebook computer. Furthermore, the adc has a hysteresis voltage design to avoid the oscillation condition.

Although the present invention has been described with reference to the above embodiments, it is not intended to limit the invention. All changes and modifications that come within the spirit and scope of the invention are desired to be protected by the following claims. For the protection defined by the present invention, reference should be made to the appended claims.

Claims

1. A power regulator adapted to adjust an operating frequency of a cpu, the power regulator comprising:

a power resistor coupled to a load to generate a first voltage;

a voltage amplifier coupled to the power resistor for outputting a second voltage; and

an analog-to-digital converter, coupled to the voltage amplifier, for converting the second voltage into a control signal and transmitting the control signal to the central processing unit, the control signal being switched between a first level and a second level according to the magnitude of the second voltage;

when the control signal is at the first level, the CPU reduces the working frequency according to the control signal, and when the control signal is at the second level, the CPU maintains the working frequency according to the control signal.

2. The power regulator of claim 1, wherein the power resistor has two terminals respectively coupled to a non-inverting input terminal and an inverting input terminal of the voltage amplifier.

3. The power regulator of claim 2, further comprising a capacitor connected in parallel with the power resistor, wherein two ends of the capacitor are coupled to the non-inverting input terminal and the inverting input terminal, respectively.

4. The power regulator of claim 1, wherein the first level is less than the second level.

5. The power regulator of claim 1, further comprising a buffer circuit coupled between the adc and the cpu.

6. The power regulator of claim 1, further comprising a start-up circuit, the start-up circuit receiving an enable signal and providing a voltage source to the power resistor, the voltage amplifier, and the analog-to-digital converter.

7. The power regulator of claim 1, wherein the adc has a hysteresis circuit, and the hysteresis circuit has a hysteresis upper threshold voltage and a hysteresis lower threshold voltage, and the control signal has the second level when the second voltage is greater than the hysteresis upper threshold voltage, and the control signal has the first level when the second voltage is less than the hysteresis lower threshold voltage, and the first level is less than the second level.

8. A power adjustment method is suitable for adjusting the operating frequency of a central processing unit and is executed by a power adjuster, the power adjuster comprises a power resistor, a voltage amplifier and an analog-digital converter, the power adjustment method comprises the following steps:

providing a voltage source;

the power resistor is coupled with a load to generate a first voltage;

the voltage amplifier receives the first voltage to output a second voltage;

the analog-digital converter selectively converts the second voltage to a first level or a second level; and

and adjusting the working frequency of the central processing unit according to the first level, and maintaining the working frequency of the central processing unit according to the second level.

9. The method as claimed in claim 8, wherein the adc determines whether the second voltage is less than a hysteresis lower threshold voltage, and if the second voltage is less than the hysteresis lower threshold voltage, the adc outputs a first control signal to the cpu to reduce the operating frequency of the cpu, the first control signal having the first level.

10. The method as claimed in claim 8, wherein the adc determines whether the second voltage is greater than a hysteresis upper threshold voltage, and if the second voltage is greater than the hysteresis upper threshold voltage, the adc outputs a second control signal to the cpu to maintain the operating frequency of the cpu, the second control signal having the second level.