CN111312303A - Compensation method and device for bit line leakage current of static random access memory - Google Patents
Compensation method and device for bit line leakage current of static random access memory Download PDFInfo
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Abstract
本发明提供一种静态随机存储器位线漏电流的补偿方法，包括：采集相邻两条位线的放电电流；控制所述相邻两条位线中放电电流较大的位线电压降低，和/或，控制所述相邻两条位线中放电电流较小的位线电压升高。本发明提供的静态随机存储器位线漏电流的补偿方法，达到SA可探测电压时需要更少的时间，降低读工作时间，提高电路工作速度。在相同的读时钟窗口，SA可探测到更大的电压差。
This invention provides a method for compensating bit line leakage current in a static random access memory (SRAM), comprising: acquiring the discharge current of two adjacent bit lines; controlling the voltage of the bit line with the larger discharge current to decrease, and/or controlling the voltage of the bit line with the smaller discharge current to increase. The method for compensating bit line leakage current in a SRAM provided by this invention requires less time to achieve a detectable voltage for the static random access memory (SA), reducing read operation time and increasing circuit operating speed. Within the same read clock window, the SA can detect a larger voltage difference.
Description
技术领域technical field
本发明涉及静态随机存储器位线漏电流的补偿技术领域，尤其涉及一种静态随机存储器位线漏电流的补偿方法及装置。The present invention relates to the technical field of compensation for bit line leakage current of SRAM, and in particular, to a method and device for compensating SRAM bit line leakage current.
背景技术Background technique
静态随机存储器(SRAM)作为一种典型的存储结构已经普遍应用于逻辑大规模集成电路(LSI)。这是因为SRAM具有运行速度快、静态功耗低的优点，同时SRAM可采用同逻辑电路一样的制造工艺。SRAM作为逻辑LSI的重要组成部分将直接影响整个电路的性能和良率。随着电路规模越来越大，工艺节点越来越先进，将会给电路带来副作用，其中最大的一个问题是随着工艺节点的降低，位线漏电增加，漏电增加将会影响SRAM的运行，尤其是在读状态时位线的放电可导致读失效。As a typical storage structure, static random access memory (SRAM) has been widely used in logic large-scale integrated circuits (LSI). This is because SRAM has the advantages of fast running speed and low static power consumption, and at the same time, SRAM can use the same manufacturing process as logic circuits. As an important part of logic LSI, SRAM will directly affect the performance and yield of the entire circuit. As the scale of the circuit becomes larger and the process node becomes more advanced, it will bring side effects to the circuit. One of the biggest problems is that with the decrease of the process node, the leakage of the bit line increases, which will affect the operation of the SRAM. , especially in the read state, the discharge of the bit line can cause a read failure.
在现有技术中，对位线漏电流的补偿方法主要有两种：一种是在SRAM单元中增加补偿管抵消SRAM单元与位线之间的漏电流；另一种是在读状态前用电容对位线漏电流进行采样，在读过程时再补偿给位线。然而在SRAM单元中增加补偿管将增加SRAM单元的面积，采用电容补偿则增加位线的负载电容，同时需要电流采样时序，影响读出速率。In the prior art, there are mainly two ways to compensate the leakage current of the bit line: one is to add a compensation tube in the SRAM cell to offset the leakage current between the SRAM cell and the bit line; the other is to use a capacitor before reading the state The leakage current of the bit line is sampled, and then compensated to the bit line during the read process. However, adding a compensation tube in the SRAM cell will increase the area of the SRAM cell, and adopting capacitance compensation will increase the load capacitance of the bit line, and at the same time, the current sampling timing will be required, which will affect the readout rate.
发明内容SUMMARY OF THE INVENTION
本发明提供的静态随机存储器位线漏电流的补偿方法及装置，能够提高SRAM电路性能及良率。The method and device for compensating the leakage current of the bit line of the static random access memory provided by the present invention can improve the performance and yield of the SRAM circuit.
第一方面，本发明提供一种静态随机存储器位线漏电流的补偿方法，包括：In a first aspect, the present invention provides a compensation method for bit line leakage current of a static random access memory, including:
采集相邻两条位线的放电电流；Collect the discharge currents of two adjacent bit lines;
控制所述相邻两条位线中放电电流较大的位线电压降低，和/或，控制所述相邻两条位线中放电电流较小的位线电压升高。Controlling the voltage of the bit line with a larger discharge current in the two adjacent bit lines to decrease, and/or controlling the voltage of the bit line with a smaller discharge current in the two adjacent bit lines to increase.
可选地，所述采集相邻两条位线的放电电流包括：Optionally, the collecting the discharge currents of two adjacent bit lines includes:
采用电压采样电路镜像两条位线上的电压值，并计算所述电压值随时间的变化速率。The voltage values on the two bit lines are mirrored using a voltage sampling circuit, and the rate of change of the voltage values over time is calculated.
可选地，所述控制所述相邻两条位线中放电电流较大的位线电压降低包括：Optionally, the controlling the reduction of the voltage of the bit line with a larger discharge current in the two adjacent bit lines includes:
所述电压采样电路将采集电压值随时间的变化速率发送至信号控制电路，所述信号控制电路依据所述电压值随时间的变化速率向电压反馈电路发送降低电压的信号，所述电压反馈电路依据所述降低电压的信号控制所述放电电流较大的位线电压降低。The voltage sampling circuit sends the rate of change of the collected voltage value over time to the signal control circuit, and the signal control circuit sends a signal to reduce the voltage to the voltage feedback circuit according to the rate of change of the voltage value over time, and the voltage feedback circuit The voltage of the bit line with the larger discharge current is controlled to be lowered according to the signal for lowering the voltage.
可选地，所述控制所述相邻两条位线中放电电流较小的位线电压升高包括：Optionally, the controlling the increase of the voltage of the bit line with a smaller discharge current in the two adjacent bit lines includes:
所述电压采样电路将采集电压值随时间的变化速率发送至信号控制电路，所述信号控制电路依据所述电压值随时间的变化速率向电压反馈电路发送升高电压的信号，所述电压反馈电路依据所述升高电压的信号控制所述放电电流较小的位线电压升高。The voltage sampling circuit sends the rate of change of the collected voltage value over time to the signal control circuit, and the signal control circuit sends a signal of increasing the voltage to the voltage feedback circuit according to the rate of change of the voltage value over time, and the voltage feedback The circuit controls the voltage of the bit line with a smaller discharge current to increase according to the signal of the increased voltage.
可选地，所述采集相邻两条位线的放电电流之前还包括：Optionally, before collecting the discharge currents of two adjacent bit lines, the method further includes:
将所述相邻两条位线预充至高电位；Precharging the adjacent two bit lines to a high potential;
选择相应的字线并控制所述字线的电位达到高电位。The corresponding word line is selected and the potential of the word line is controlled to a high potential.
本发明提供的静态随机存储器位线漏电流的补偿方法，采用基于电压反馈的漏电流补偿电路方案，对放电较快的位线，降低其电压，进一步提高放电速率，对放电较慢的位线，提高其电压，进一步降低放电效率，从而增加两条位线电压差随时间的变化率。本发明提供的静态随机存储器位线漏电流的补偿方法，达到SA可探测电压时需要更少的时间，降低读工作时间，提高电路工作速度。在相同的读时钟窗口，SA可探测到更大的电压差。The method for compensating the leakage current of the bit line of the static random access memory provided by the present invention adopts the leakage current compensation circuit scheme based on voltage feedback. , increasing its voltage, further reducing the discharge efficiency, thereby increasing the rate of change of the voltage difference between the two bit lines over time. The method for compensating the leakage current of the bit line of the static random access memory provided by the present invention requires less time to reach the SA detectable voltage, reduces the reading working time, and improves the circuit working speed. In the same read clock window, SA can detect a larger voltage difference.
第二方面，本发明提供一种静态随机存储器位线漏电流的补偿装置，包括：至少一个补偿模块；所述补偿模块包括：In a second aspect, the present invention provides a device for compensating for bit line leakage current of a static random access memory, including: at least one compensation module; the compensation module includes:
电压采样电路，采集相邻两条位线的放电电流；The voltage sampling circuit collects the discharge current of two adjacent bit lines;
信号控制电路，用于接收所述电压采样电路采集的信息并发出控制信号；a signal control circuit for receiving the information collected by the voltage sampling circuit and sending out a control signal;
电压反馈电路，用于控制相邻两条位线中放电电流较大的位线电压降低，和/或，控制所述相邻两条位线中放电电流较小的位线电压升高。The voltage feedback circuit is used to control the voltage of the bit line with a larger discharge current in two adjacent bit lines to decrease, and/or control the voltage of the bit line with a smaller discharge current in the two adjacent bit lines to increase.
可选地，所述电压采样电路，与相邻两条位线电连接；Optionally, the voltage sampling circuit is electrically connected to two adjacent bit lines;
所述信号控制电路，与所述电压采样电路通信连接；the signal control circuit is connected in communication with the voltage sampling circuit;
所述电压反馈电路，与所述信号控制电路通信连接，所述电压反馈电路与所述相邻两条位线的其中一条电连接。The voltage feedback circuit is connected in communication with the signal control circuit, and the voltage feedback circuit is electrically connected to one of the two adjacent bit lines.
可选地，包括两个补偿模块，其中一个补偿模块的电压反馈电路与所述相邻两条位线中的其中一条电连接，另一个补偿模块的电压反馈电路与所述相邻两条位线中的另一条电连接。Optionally, two compensation modules are included, wherein the voltage feedback circuit of one compensation module is electrically connected to one of the two adjacent bit lines, and the voltage feedback circuit of the other compensation module is electrically connected to the adjacent two bit lines. Another electrical connection in the wire.
可选地，所述电压采样电路，用于对相邻两条位线的电压进行采样并计算电压随时间变化的速率，以得到所述相邻两条位线的放电电流。Optionally, the voltage sampling circuit is configured to sample the voltages of two adjacent bit lines and calculate the rate of voltage change with time, so as to obtain the discharge currents of the two adjacent bit lines.
可选地，所述补偿模块检测所述字线的电位，当所述字线的电位为高电位时启动，当所述字线的电位为低电位时关闭。Optionally, the compensation module detects the potential of the word line, starts when the potential of the word line is at a high potential, and turns off when the potential of the word line is at a low potential.
本发明提供的静态随机存储器位线漏电流的补偿装置，采用基于电压反馈的漏电流补偿电路方案，对放电较快的位线，降低其电压，进一步提高放电速率，对放电较慢的位线，提高其电压，进一步降低放电效率，从而增加两条位线电压差随时间的变化率。本发明提供的静态随机存储器位线漏电流的补偿方法，达到SA可探测电压时需要更少的时间，降低读工作时间，提高电路工作速度。在相同的读时钟窗口，SA可探测到更大的电压差。The device for compensating the leakage current of the bit line of the static random access memory provided by the present invention adopts the leakage current compensation circuit scheme based on voltage feedback to reduce the voltage of the bit line that discharges faster, and further improve the discharge rate, and to the bit line that discharges slowly. , increasing its voltage, further reducing the discharge efficiency, thereby increasing the rate of change of the voltage difference between the two bit lines over time. The method for compensating the leakage current of the bit line of the static random access memory provided by the present invention requires less time to reach the SA detectable voltage, reduces the reading working time, and improves the circuit working speed. In the same read clock window, SA can detect a larger voltage difference.
附图说明Description of drawings
图1为本发明一实施例静态随机存储器位线漏电流的补偿装置的示意图；1 is a schematic diagram of a device for compensating for bit line leakage current of an SRAM according to an embodiment of the present invention;
图2为本发明一实施例静态随机存储器位线漏电流示意图。FIG. 2 is a schematic diagram of the leakage current of the SRAM bit line according to an embodiment of the present invention.
具体实施方式Detailed ways
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。In order to make the purposes, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments It is only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.
实施例1Example 1
如图2所示，在读取C1单元时，位线预充电到高电位，位线将与SRAM单元内部“0”节点之间形成漏电流，漏电流将影响位线上的放电电流。随着电路规模越来越大，位线上连接的SRAM单元越来越多，产生漏电流的单元也会越多，当总的漏电流足够大以至于位线BL上的放电电流接近甚至大于BL_n上的放电电流时，将造成读失效。假设SRAM电路每条位线连接有N个SRAM单元，其中在BL上有n个单元将产生漏电流，则在BL_n上有N-n个单元产生漏电流。每个单元产生的漏电流为Ilkg，开启电流为Ion。在读取SRAM单元C1过程中，位线BL上总的放电电流为nIlkg，位线BL_n上总的放电电流为Ion+(N-n)Ilkg，比较放大器(SA，SenseAmplifier)探测两条位线的电压差从而得到单元C1的存储数据。(N-n)Ilkg可以增大BL_n与BL的压差，因此对读过程是有用的。而现有技术在读过程时对这部分漏电流进行补偿将会降低电路的性能，得不偿失。As shown in Figure 2, when the C1 cell is read, the bit line is precharged to a high potential, and a leakage current will be formed between the bit line and the "0" node inside the SRAM cell, and the leakage current will affect the discharge current on the bit line. As the circuit scale increases, more and more SRAM cells are connected to the bit line, and more cells generate leakage current. When the total leakage current is large enough that the discharge current on the bit line BL is close to or even greater than Discharge current on BL_n will cause read failure. Assuming that each bit line of the SRAM circuit is connected with N SRAM cells, there are n cells on BL that will generate leakage current, and Nn cells on BL_n will generate leakage current. The leakage current generated by each cell is I lkg , and the turn-on current is I on . In the process of reading the SRAM cell C1 , the total discharge current on the bit line BL is nI lkg , the total discharge current on the bit line BL_n is I on +(Nn)I lkg , the comparator amplifier (SA, SenseAmplifier) detects two The voltage difference of the bit line thus obtains the stored data of the cell C1. (Nn)11kg can increase the pressure difference between BL_n and BL, so it is useful for the reading process. However, in the prior art, compensating for this part of the leakage current during the reading process will reduce the performance of the circuit, which is not worth the loss.
本发明实施例提供一种静态随机存储器位线漏电流的补偿方法，包括：An embodiment of the present invention provides a compensation method for bit line leakage current of a static random access memory, including:
采集相邻两条位线的放电电流；Collect the discharge currents of two adjacent bit lines;
控制所述相邻两条位线中放电电流较大的位线电压降低，和/或，控制所述相邻两条位线中放电电流较小的位线电压升高。Controlling the voltage of the bit line with a larger discharge current in the two adjacent bit lines to decrease, and/or controlling the voltage of the bit line with a smaller discharge current in the two adjacent bit lines to increase.
对于本实施例来说，可以采用的方式有三种，第一种为控制所述相邻两条位线中放电电流较大的位线电压降低，可选地，所述电压采样电路将采集电压值随时间的变化速率发送至信号控制电路，所述信号控制电路依据所述电压值随时间的变化速率向电压反馈电路发送降低电压的信号，所述电压反馈电路依据所述降低电压的信号控制所述放电电流较大的位线电压降低。从而使放电效率高的位线进一步提高放电效率。第二种为控制所述相邻两条位线中放电电流较小的位线电压升高，可选地，所述电压采样电路将采集电压值随时间的变化速率发送至信号控制电路，所述信号控制电路依据所述电压值随时间的变化速率向电压反馈电路发送升高电压的信号，所述电压反馈电路依据所述升高电压的信号控制所述放电电流较小的位线电压升高。从而使放电效率低的位线进一步降低放电效率。第三种为控制所述相邻两条位线中放电电流较大的位线电压降低，并同时控制所述相邻两条位线中放电电流较小的位线电压升高，从而使放电效率高的位线进一步提高放电效率，而放电效率低的位线进一步降低放电效率。对于上述的三种方式，第三种为最优选的方式，相较于前两种，达到SA可探测电压时需要更少的时间，降低读工作时间，提高电路工作速度。在相同的读时钟窗口，SA可探测到更大的电压差。For this embodiment, there are three possible ways. The first one is to control the voltage of the bit line with the larger discharge current in the two adjacent bit lines to decrease. Optionally, the voltage sampling circuit will collect the voltage The rate of change of the value over time is sent to a signal control circuit, and the signal control circuit sends a signal to reduce the voltage to a voltage feedback circuit according to the rate of change of the voltage value over time, and the voltage feedback circuit controls according to the signal to reduce the voltage The bit line voltage at which the discharge current is larger decreases. Thereby, the bit line with high discharge efficiency can further improve the discharge efficiency. The second is to control the voltage of the bit line with a smaller discharge current in the two adjacent bit lines to increase. Optionally, the voltage sampling circuit sends the change rate of the collected voltage value over time to the signal control circuit, so The signal control circuit sends a signal of increasing the voltage to the voltage feedback circuit according to the rate of change of the voltage value over time, and the voltage feedback circuit controls the voltage of the bit line with a smaller discharge current to increase according to the signal of the increased voltage. high. As a result, the bit line with low discharge efficiency further reduces the discharge efficiency. The third method is to control the voltage of the bit line with the larger discharge current in the two adjacent bit lines to decrease, and simultaneously control the voltage of the bit line with the smaller discharge current in the two adjacent bit lines to increase, so that the discharge High efficiency bit lines further increase discharge efficiency, while low discharge efficiency bit lines further reduce discharge efficiency. For the above three methods, the third method is the most preferred method. Compared with the first two methods, it takes less time to reach the SA detectable voltage, which reduces the reading time and improves the circuit operating speed. In the same read clock window, SA can detect a larger voltage difference.
可选地，所述采集相邻两条位线的放电电流包括：Optionally, the collecting the discharge currents of two adjacent bit lines includes:
采用电压采样电路镜像两条位线上的电压值，并计算所述电压值随时间的变化速率。The voltage values on the two bit lines are mirrored using a voltage sampling circuit, and the rate of change of the voltage values over time is calculated.
可选地，所述采集相邻两条位线的放电电流之前还包括：Optionally, before collecting the discharge currents of two adjacent bit lines, the method further includes:
将所述相邻两条位线预充至高电位；Precharging the adjacent two bit lines to a high potential;
选择相应的字线并控制所述字线的电位达到高电位。The corresponding word line is selected and the potential of the word line is controlled to a high potential.
具体地，如图1所示，在位线预充电状态时，信号控制电路控制电压反馈电路不工作，位线保持在预充电状态。在读状态时，电压采样电路镜像两条位线上的电压值，从而得到两条位线上电压随时间变化的情况，既位线放电电流的大小。再通过信号控制电路将得到的电压信号传递给电压反馈电路，电压反馈电路根据得到的不同信号反馈相应的电压值，从而达到补偿位线漏电流的目的。Specifically, as shown in FIG. 1 , in the precharge state of the bit line, the signal control circuit controls the voltage feedback circuit to not work, and the bit line is kept in the precharge state. In the read state, the voltage sampling circuit mirrors the voltage values on the two bit lines, so as to obtain the variation of the voltages on the two bit lines with time, that is, the magnitude of the discharge current of the bit lines. Then, the obtained voltage signal is transmitted to the voltage feedback circuit through the signal control circuit, and the voltage feedback circuit feeds back the corresponding voltage value according to the obtained different signals, so as to achieve the purpose of compensating the leakage current of the bit line.
假设位线BL比BL_n的放电电流大，则BL的电压随时间变化率更大，电压采样电路采样到两条位线的情况后传导到电压反馈电路，电压反馈电路探测到BL的放电速率更快时将反馈一电压信号使BL的电压更低，从而增加BL电压随时间变化的速率。相应的，电压反馈电路探测到BL_n的放电速率更慢时将反馈一电压信号使BL的电压更高，从而降低BL电压随时间变化的速率。最终增加两条位线电压差随时间变化率，提高SRAM电路读的性能。Assuming that the discharge current of the bit line BL is larger than that of BL_n, the voltage of BL has a larger rate of change with time. The voltage sampling circuit samples the two bit lines and conducts it to the voltage feedback circuit. The voltage feedback circuit detects that the discharge rate of BL is higher. The fast time will feed back a voltage signal to make the voltage of BL lower, thereby increasing the rate of change of BL voltage with time. Correspondingly, when the voltage feedback circuit detects that the discharge rate of BL_n is slower, it will feed back a voltage signal to make the voltage of BL higher, thereby reducing the rate of change of the BL voltage with time. Finally, the rate of change of the voltage difference between the two bit lines over time is increased, and the read performance of the SRAM circuit is improved.
本实施例提供的静态随机存储器位线漏电流的补偿方法，采用基于电压反馈的漏电流补偿电路方案，对放电较快的位线，降低其电压，进一步提高放电速率，对放电较慢的位线，提高其电压，进一步降低放电效率，从而增加两条位线电压差随时间的变化率。本实施例提供的静态随机存储器位线漏电流的补偿方法，达到SA可探测电压时需要更少的时间，降低读工作时间，提高电路工作速度。在相同的读时钟窗口，SA可探测到更大的电压差。The method for compensating the leakage current of the SRAM bit line provided by this embodiment adopts the leakage current compensation circuit scheme based on voltage feedback, and reduces the voltage of the bit line that discharges faster, further increases the discharge rate, and reduces the voltage of the bit line that discharges slowly. line, increasing its voltage, further reducing the discharge efficiency, thereby increasing the rate of change of the voltage difference between the two bit lines over time. The method for compensating the bit line leakage current of the static random access memory provided in this embodiment requires less time to reach the SA detectable voltage, reduces the read working time, and improves the circuit working speed. In the same read clock window, SA can detect a larger voltage difference.
实施例2Example 2
本实施例提供一种静态随机存储器位线漏电流的补偿装置，包括：至少一个补偿模块；所述补偿模块包括：This embodiment provides a compensation device for bit line leakage current of a static random access memory, including: at least one compensation module; the compensation module includes:
电压采样电路，采集相邻两条位线的放电电流；可选地，所述电压采样电路，用于对相邻两条位线的电压进行采样并计算电压随时间变化的速率，以得到所述相邻两条位线的放电电流。The voltage sampling circuit is used to collect the discharge currents of two adjacent bit lines; optionally, the voltage sampling circuit is used to sample the voltages of the adjacent two bit lines and calculate the rate of voltage change with time, so as to obtain the The discharge current of the two adjacent bit lines.
信号控制电路，用于接收所述电压采样电路采集的信息并发出控制信号；a signal control circuit for receiving the information collected by the voltage sampling circuit and sending out a control signal;
电压反馈电路，用于控制相邻两条位线中放电电流较大的位线电压降低，和/或，控制所述相邻两条位线中放电电流较小的位线电压升高。The voltage feedback circuit is used to control the voltage of the bit line with a larger discharge current in two adjacent bit lines to decrease, and/or control the voltage of the bit line with a smaller discharge current in the two adjacent bit lines to increase.
对于本实施例来说，有三种可选的形式，第一种为包括一个补偿模块，其中一个补偿模块的电压反馈电路与所述相邻两条位线中的其中一条电连接，该补偿模块的电压反馈电路用于在与其连接的位线放电电流较大时控制该位线电压降低，以进一步增大该位线的放电效率；第二种为包括一个补偿模块，其中一个补偿模块的电压反馈电路与所述相邻两条位线中的其中一条电连接，该补偿模块的电压反馈电路用于在与其连接的位线放电电流较小时控制该位线的电压升高，以进一步降低该位线的放电效率；第三种为包括两个补偿模块，其中一个补偿模块的电压反馈电路与所述相邻两条位线中的其中一条电连接，另一个补偿模块的电压反馈电路与所述相邻两条位线中的另一条电连接。For this embodiment, there are three optional forms. The first one is to include a compensation module, wherein the voltage feedback circuit of one compensation module is electrically connected to one of the two adjacent bit lines, and the compensation module is electrically connected to one of the two adjacent bit lines. The voltage feedback circuit is used to control the voltage of the bit line to decrease when the discharge current of the bit line connected to it is large, so as to further increase the discharge efficiency of the bit line; the second is to include a compensation module, wherein the voltage of one compensation module is The feedback circuit is electrically connected to one of the two adjacent bit lines, and the voltage feedback circuit of the compensation module is used to control the voltage of the bit line to increase when the discharge current of the bit line connected to it is small, so as to further reduce the voltage of the bit line. The discharge efficiency of the bit line; the third type is to include two compensation modules, wherein the voltage feedback circuit of one compensation module is electrically connected to one of the two adjacent bit lines, and the voltage feedback circuit of the other compensation module is connected to all the adjacent bit lines. The other one of the two adjacent bit lines is electrically connected.
可选地，所述电压采样电路，与相邻两条位线电连接；Optionally, the voltage sampling circuit is electrically connected to two adjacent bit lines;
所述信号控制电路，与所述电压采样电路通信连接；the signal control circuit is connected in communication with the voltage sampling circuit;
所述电压反馈电路，与所述信号控制电路通信连接，所述电压反馈电路与所述相邻两条位线的其中一条电连接。The voltage feedback circuit is connected in communication with the signal control circuit, and the voltage feedback circuit is electrically connected to one of the two adjacent bit lines.
可选地，所述补偿模块检测所述字线的电位，当所述字线的电位为高电位时启动，当所述字线的电位为低电位时关闭。Optionally, the compensation module detects the potential of the word line, starts when the potential of the word line is at a high potential, and turns off when the potential of the word line is at a low potential.
具体地，如图1所示，在位线预充电状态时，信号控制电路控制电压反馈电路不工作，位线保持在预充电状态。在读状态时，电压采样电路镜像两条位线上的电压值，从而得到两条位线上电压随时间变化的情况，既位线放电电流的大小。再通过信号控制电路将得到的电压信号传递给电压反馈电路，电压反馈电路根据得到的不同信号反馈相应的电压值，从而达到补偿位线漏电流的目的。Specifically, as shown in FIG. 1 , in the precharge state of the bit line, the signal control circuit controls the voltage feedback circuit to not work, and the bit line is kept in the precharge state. In the read state, the voltage sampling circuit mirrors the voltage values on the two bit lines, so as to obtain the variation of the voltages on the two bit lines with time, that is, the magnitude of the discharge current of the bit lines. Then, the obtained voltage signal is transmitted to the voltage feedback circuit through the signal control circuit, and the voltage feedback circuit feeds back the corresponding voltage value according to the obtained different signals, so as to achieve the purpose of compensating the leakage current of the bit line.
假设位线BL比BL_n的放电电流大，则BL的电压随时间变化率更大，电压采样电路采样到两条位线的情况后传导到电压反馈电路，电压反馈电路探测到BL的放电速率更快时将反馈一电压信号使BL的电压更低，从而增加BL电压随时间变化的速率。相应的，电压反馈电路探测到BL_n的放电速率更慢时将反馈一电压信号使BL的电压更高，从而降低BL电压随时间变化的速率。最终增加两条位线电压差随时间变化率，提高SRAM电路读的性能。Assuming that the discharge current of the bit line BL is larger than that of BL_n, the voltage of BL has a larger rate of change with time. The voltage sampling circuit samples the two bit lines and conducts it to the voltage feedback circuit. The voltage feedback circuit detects that the discharge rate of BL is higher. The fast time will feed back a voltage signal to make the voltage of BL lower, thereby increasing the rate of change of BL voltage with time. Correspondingly, when the voltage feedback circuit detects that the discharge rate of BL_n is slower, it will feed back a voltage signal to make the voltage of BL higher, thereby reducing the rate of change of the BL voltage with time. Finally, the rate of change of the voltage difference between the two bit lines over time is increased, and the read performance of the SRAM circuit is improved.
本实施例提供的静态随机存储器位线漏电流的补偿装置，采用基于电压反馈的漏电流补偿电路方案，对放电较快的位线，降低其电压，进一步提高放电速率，对放电较慢的位线，提高其电压，进一步降低放电效率，从而增加两条位线电压差随时间的变化率。本实施例提供的静态随机存储器位线漏电流的补偿方法，达到SA可探测电压时需要更少的时间，降低读工作时间，提高电路工作速度。在相同的读时钟窗口，SA可探测到更大的电压差。The device for compensating the leakage current of the bit line of the static random access memory provided in this embodiment adopts the leakage current compensation circuit scheme based on voltage feedback to reduce the voltage of the bit line that discharges faster, and further improve the discharge rate, and the bit line that discharges slowly. line, increasing its voltage, further reducing the discharge efficiency, thereby increasing the rate of change of the voltage difference between the two bit lines over time. The method for compensating the bit line leakage current of the static random access memory provided in this embodiment requires less time to reach the SA detectable voltage, reduces the read working time, and improves the circuit working speed. In the same read clock window, SA can detect a larger voltage difference.
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求的保护范围为准。The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical scope disclosed by the present invention can easily think of changes or substitutions. All should be included within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
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