CN111289874A - Robustness testing method, system and device for power semiconductor chip - Google Patents

Abstract

The invention relates to the field of chip testing, and specifically discloses a robustness testing method for a power semiconductor chip. During the aging process, the temperature gradient distribution (instead of the temperature distribution) on the surface of the chip to be tested is obtained, which is used for chip abnormality detection and physical screening. The source and judgment basis of data processing in the process, after obtaining the temperature gradient information of the current chip, use anomaly detection and physical fitness screening algorithms to perform robust automated testing. The invention can find out the defects of chip thermoelectric robustness earlier, find out deeper robustness problems (such as abnormal heat concentration and uneven heat dissipation) in time, and obtain basic data quantitatively rather than qualitatively (such as temperature gradient and heat dissipation). change with time); compared with the detection period of several days or even tens of days for each batch of the traditional aging method, the present invention can complete the robustness test of the chip with the data collected within tens of minutes to several hours, saving energy More time, effectively improve production efficiency.

Description

Robustness testing method, system and device for power semiconductor chip

technical field

The invention relates to the field of chip testing, in particular to a robustness testing method, system and device of a power semiconductor chip.

Background technique

For power devices such as LDMOS\VDMOS\IGBT, the robustness (ie robustness) of semiconductor chips is a very important indicator. The robustness of power devices is often related to the temperature distribution of the device. The device has high power, and the internal or external temperature of the component in the working state will change with the accumulation of heat, and the temperature change will in turn affect the working state of the component, that is, the phenomenon of thermoelectric coupling. For the IGBT, the accumulation of heat increases the internal temperature of the IGBT, and the current also increases with the increase of the internal temperature, and the increase of the current in turn further increases the power and increases the internal temperature. device burnout. In order to ensure the reliable operation of electronic components, it is necessary to ensure that the electronic components have sufficient robustness during the production process.

At present, the robustness of semiconductor chips is mainly carried out through the aging test, that is, the semiconductor chip to be tested is placed in the aging test device, and the IV detection module is used to detect whether the semiconductor chip to be tested has normal electrical performance. The test semiconductor chip will be attached with a CV detection module to ensure the reliability of the test semiconductor chip. However, for power devices such as LDMOS\VDMOS\IGBT, it is the temperature accumulation caused by high power that affects the reliability of the semiconductor chip to be tested. It takes a long enough time to judge the reliability of the semiconductor chip to be tested by detecting the electrical properties. The aging time can reflect the unreliability of the semiconductor chip under test through abnormal electrical performance.

SUMMARY OF THE INVENTION

The present invention provides a robustness testing method for a power semiconductor chip in order to solve the problem of long testing period in the prior art by detecting the electrical properties of the semiconductor chip to be tested in the aging process to determine the robustness of the semiconductor chip to be tested. , can shorten the test time.

The technical scheme adopted in the present invention:

A robustness testing method for a power semiconductor chip, comprising:

S11: Obtain an infrared image of the semiconductor chip to be tested;

S12: Acquire infrared information of Y points in the infrared image space region;

S13: Calculate the temperature information of the Y points respectively;

S14: Calculate the temperature gradients of the Y points respectively;

S15: Divide the overall spatial area of the infrared image into i small areas;

S16: Obtain the maximum temperature gradient in each of the small regions, and configure the maximum temperature gradient in each of the small regions as the temperature gradient of each of the small regions;

S17: Count the temperature gradients of each of the small regions, and draw a first histogram, where the horizontal axis of the first histogram is the temperature gradient, and the vertical axis of the first histogram is the temperature gradient For the number of corresponding small areas, sort the first histogram according to the number from large to small to form a second histogram;

S18: Use Rayleigh distribution to fit the second histogram to obtain σ, and the Rayleigh distribution formula is:

Wherein, x is the sampling value of the temperature gradient at a certain point, and σ is the root mean square of the temperature gradient. When σ is greater than the first set value, the semiconductor chip to be tested is determined to be abnormal.

The robustness testing method of the power semiconductor chip further includes a constitution screening algorithm, and the constitution screening algorithm includes:

S21: Obtain n infrared images in the aging period;

S22: Perform steps S12 to S18 on the n infrared images to obtain n Rayleigh distributions and their parameters σ ₁ , σ ₂ ... σ _n , for the parameters σ ₁ , σ ₂ ... σ _n Perform statistics and draw a third histogram;

S23: Fitting the third histogram with Gaussian distribution N(μ, θ ² ) to obtain θ, where μ is the expectation of the root mean square of the temperature gradient, and θ is the standard of the root mean square of the temperature gradient Difference;

S24: Compare the θ value with the second set value, and classify the quality of the semiconductor chip to be tested.

Further, the formula for calculating the temperature information of each point in the spatial region is:

T(x,y)=αK(x,y)+β,

Among them, K(x,y) is the infrared information of the point (x,y) in the infrared image, α is the first constant coefficient, which is used to amplify the infrared information, and β is the second constant coefficient, which is used to amplify the infrared information. The temperature information is converted into a positive value, and T(x,y) is the temperature information of the linearly mapped infrared image.

Further, the calculation formula of the temperature gradient at each point in the space region is:

为偏微分算子，T为温度信息，

为矢量，

的绝对值

为所述温度梯度。i and j are unit vectors in the x and y directions,

is the partial differential operator, T is the temperature information,

is a vector,

the absolute value of

is the temperature gradient.

Further, the robustness testing method of the power semiconductor chip also includes:

S01: set the variation range and variation process of excitation signal and described excitation signal;

S02: setting the ambient temperature and the variation range and variation process of the ambient temperature;

S03: Set the aging time, collect and store the infrared image of the semiconductor chip to be tested during the aging period;

S04: analyze the electrical performance test results of the semiconductor chip to be tested;

S041: If the electrical properties of the semiconductor chip to be tested are normal, continue to perform steps S11 to S14;

S042: If the electrical properties of the semiconductor chip to be tested are abnormal, end the test.

The present invention provides a robustness testing system for a power semiconductor chip in order to solve the problem of long test period in the prior art by detecting the electrical properties of the semiconductor chip to be tested in the aging process to determine the robustness of the semiconductor chip to be tested. , can shorten the test time.

A robustness testing system for a power semiconductor chip, comprising:

an image acquisition module, which is used to acquire an infrared image of the semiconductor chip to be tested;

an information acquisition module, which is used to acquire infrared information of Y points in the infrared image space region;

a temperature information calculation module, which is used to calculate the temperature information of the Y points respectively;

a temperature gradient calculation module, the temperature gradient calculation module is used to calculate the temperature gradients of the Y points respectively;

a space area division module, the space area division module is used to divide the overall space area of the infrared image into i small areas;

A small area temperature gradient acquisition module, the small area temperature gradient acquisition module is used to acquire the maximum temperature gradient in each of the small areas, and configure the maximum temperature gradient in each of the small areas as the temperature gradient of each of the small areas ;

A statistical module, the statistical module is used to perform statistics on the temperature gradient of each of the small regions, and draw a first histogram, where the horizontal axis of the first histogram is the temperature gradient, and the The vertical axis is the number of small regions corresponding to the temperature gradient, and the first histograms are sorted from large to small to form a second histogram;

an analysis module, the analysis module uses the Rayleigh distribution to fit the second histogram to obtain the root mean square value of the temperature gradient, and when the root mean square value of the temperature gradient is greater than the first threshold, it is determined that the The semiconductor chip is abnormal.

The present invention provides a robustness testing device for a power semiconductor chip in order to solve the problem of long test period in the prior art by detecting the electrical properties of the semiconductor chip to be tested during the aging process to determine the robustness of the semiconductor chip to be tested. , can shorten the test time.

A robustness testing device for a power semiconductor chip, comprising:

a signal generating module, which generates various excitation signals to impact the semiconductor chip to be tested;

a temperature control module, which controls and adjusts the ambient temperature of the semiconductor chip to be tested;

an electrical performance detection module, used to detect the electrical performance of the semiconductor chip to be tested;

An infrared imaging module, including a camera, for obtaining an infrared image of the excited semiconductor chip to be tested;

and a controller, which is used for processing the infrared image and judging whether the semiconductor chip to be tested is normal.

Compared with the prior art, the beneficial effects of the present invention:

When the power semiconductor chip is working, a large amount of heat is dissipated, resulting in high chip temperature and more obvious temperature change. The present invention can reflect the internal defect of the power semiconductor chip by detecting the surface temperature change of the power semiconductor chip and processing the data. , abnormal state and good or bad physical condition, the time for detecting temperature change of the present invention is much shorter than that of long-term electrical aging test, so the problem of long test time in the prior art is solved and the test efficiency is improved.

Description of drawings

FIG. 1 is a flowchart 1 of a method for testing robustness of a power semiconductor chip according to an embodiment of the present invention;

2 is a second flowchart of a method for testing robustness of a power semiconductor chip according to an embodiment of the present invention;

3 is a third flowchart of a method for testing robustness of a power semiconductor chip according to an embodiment of the present invention;

4 is a schematic diagram of an infrared image provided by an embodiment of the present invention;

5 is a schematic diagram of a first histogram provided by an embodiment of the present invention;

6 is a schematic diagram of a second histogram provided by an embodiment of the present invention;

7 is a schematic diagram of a third histogram provided by an embodiment of the present invention;

FIG. 8 is a schematic diagram of a robustness testing apparatus for a power semiconductor chip according to an embodiment of the present invention.

In the figure, 311 is the first isotherm, 312 is the second isotherm, 313 is the third isotherm, 314 is the fourth isotherm, Dt1 is the first temperature gradient, Dt2 is the second temperature gradient, and Dt3 is the third temperature gradient.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

An embodiment of the present invention provides a robustness testing method for a power semiconductor chip. The semiconductor chip to be tested is placed in a robustness testing device, and the robustness testing device can be used to perform an aging test on the semiconductor chip to be tested. The robustness testing device includes a signal generation module, a temperature control module and an infrared imaging module. The signal generation module provides an excitation signal for the semiconductor chip to be tested, and the temperature control module makes the semiconductor chip to be tested work at a set temperature. The infrared imaging module includes a camera , take pictures of the semiconductor chip to be tested by a camera during the aging period, and use the principle of thermal imaging to obtain an infrared image corresponding to the semiconductor chip to be tested. Specifically, as shown in Figure 1, the method includes:

S11: Obtain an infrared image of the semiconductor chip to be tested;

In this embodiment, an infrared image is obtained through an infrared imaging module, which detects the infrared energy (heat) of the semiconductor chip to be tested through non-contact, converts it into an electrical signal, and then generates an infrared image and the infrared image of each pixel of the infrared image. information.

S12: Obtain the infrared information of Y points in the infrared image space area;

In this implementation, the more the number of infrared information acquired, the better, and the more data the more accurate the subsequent statistical analysis, so the number of acquired infrared information is not limited.

S13: Calculate the temperature information of Y points respectively;

In this embodiment, the temperature information corresponding to each point in the infrared image is obtained by linearly mapping the infrared information of each point in the infrared image spatial area to the temperature information. Linearly amplify, and then correct the linearly amplified infrared information to obtain a positive number from 0 to 100, and configure the calculated positive number as temperature information. In this embodiment, by amplifying the infrared information, the temperature information of two adjacent points is obtained. The difference is more obvious;

Specifically, the formula for calculating the temperature information of each point in the space area is:

T(x,y)=αK(x,y)+β,

Among them, K(x,y) is the infrared information of the point (x,y) in the infrared image, α is the first constant coefficient, which is used to amplify the infrared information, and β is the second constant coefficient, which is used to convert the temperature information. is a positive value, and T(x,y) is the temperature information of the linearly mapped infrared image.

Specifically, this embodiment is described by taking an LDMOS semiconductor chip for P-band radar as an example. After the steps S11 to S13 are processed, the infrared image formed in this embodiment is shown in FIG. 4 . The LDMOS semiconductor chip for P-band radar is composed of 512 It consists of several LDMOS units 314 (only six are shown here as an example), each LDMOS unit 314 will generate heat, and the accumulation and dissipation of heat will cause temperature changes. In this embodiment, the first isotherm 311 and the second isotherm are used. Line 312, third isotherm 313 and fourth isotherm 314 represent the temperature distribution of the spatial region.

S14: Calculate the temperature gradient of Y points respectively;

The temperature gradient of each point is calculated in the infrared image plane processed from steps S11 to S13, and the temperature gradient calculation formula is:

为偏微分算子，T为温度信息，

为矢量，

的绝对值

为温度梯度。i and j are unit vectors in the x and y directions,

is the partial differential operator, T is the temperature information,

is a vector,

the absolute value of

is the temperature gradient.

Taking the LDMOS semiconductor chip for P-band radar as an example, after the infrared image is calculated by the temperature gradient, the temperature gradient distribution diagram is formed as shown in Figure 3. In this figure, Dt1 represents the first temperature gradient, Dt2 represents the second temperature gradient, and Dt3 represents the The third temperature gradient.

S15: Divide the overall spatial area of the infrared image into i small areas;

S16: Obtain the maximum temperature gradient in each small area, and configure the maximum temperature gradient in each small area as the temperature gradient of each small area;

S17: Count the temperature gradient of each small area, and draw a first histogram, as shown in Figure 5, the horizontal axis of the first histogram is the temperature gradient, and the vertical axis of the first histogram is the temperature gradient corresponding to the The number of small areas, sort the first histogram from large to small to form a second histogram, as shown in Figure 6;

S18: Use the Rayleigh distribution to fit the second histogram to obtain σ. The Rayleigh distribution formula is:

Among them, x is the sampling value of the temperature gradient at a certain point, and σ is the root mean square of the temperature gradient. When σ is greater than the first set value, the semiconductor chip to be tested is determined to be abnormal.

Specifically, the larger the σ value obtained by the Rayleigh distribution in this embodiment, the greater the temperature change rate of the semiconductor chip to be tested is, and the temperature distribution of the semiconductor chip to be tested is uneven.

Further, as shown in FIG. 2 , the robustness testing method of the power semiconductor chip further includes a constitution screening algorithm, and the constitution screening algorithm includes:

S21: Obtain n infrared images in the aging period;

S22: Perform steps S12 to S18 on n infrared images, respectively, to obtain n Rayleigh distributions and their parameters σ ₁ , σ ₂ ... σ _n , and perform statistics on the parameters σ ₁ , σ ₂ ... σ _n , Draw a third histogram, as shown in Figure 7;

S23: Use Gaussian distribution N(μ, θ ² ) to fit the third histogram to obtain θ, where μ is the expectation of the root mean square of the temperature gradient, and θ is the standard deviation of the root mean square of the temperature gradient;

S24: Compare the θ value with the second set value to classify the quality of the semiconductor chip to be tested.

Specifically, in this embodiment, all infrared images during the entire aging process of the semiconductor chip to be tested are processed and analyzed, and then the θ value is obtained by using Gaussian distribution. Subsequently, the quality of the semiconductor chip to be tested is classified.

It should be noted that, in this embodiment, the robustness of the semiconductor chip is judged by performing statistical analysis on the temperature gradient distribution, rather than using the temperature distribution for statistical analysis, for the following reasons:

1. Among different semiconductor chips to be tested, the temperature distribution of the semiconductor chips to be tested varies greatly, and the abnormal temperature of the semiconductor chips to be tested can easily be masked by this difference in temperature distribution as noise;

2. The temperature does not change significantly with time, it is difficult to observe obvious changes in a short period of time, and the abnormal temperature in time is difficult to find;

3. In the process of using temperature for data statistics, due to the large difference in temperature distribution of different semiconductor chips, when using distributions such as normal distribution for statistics, the data spread is large, the fitting error is large, and the parameter values fluctuate greatly;

Therefore, in this embodiment, statistical analysis is performed through the temperature gradient distribution, and more attention is paid to the distribution of temperature changes, thereby avoiding the interference of noise caused by the differences in the temperature distribution between the semiconductor chips, and effectively reflecting the details of temperature changes of the semiconductor chips. The temperature gradient distribution changes more obviously with time, and obvious changes can be observed in a short period of time, so that semiconductor chip abnormalities can be detected in a short period of time; Statistical methods have more obvious regularities in distribution fitting, greatly reduced fitting errors, and achieved higher accuracy in final anomaly detection or physique screening.

Compared with the currently commonly used IV/CV detection method, this embodiment can find out the defects in the robustness of the device earlier by obtaining the basic data (such as temperature gradient and change with time) quantitatively but not qualitatively, so as to find out the defects in time. Robustness issues at a deeper level (such as uneven heat dissipation); compared with the detection cycle of several days or even tens of days per batch of traditional aging methods, this embodiment can be completed by collecting data from tens of minutes to several hours In the robust abnormal detection and physical screening of the chip, this embodiment saves more time and effectively improves the production efficiency.

Further, as shown in FIG. 3 , the robustness testing method of the power semiconductor chip also includes:

S01: set the excitation signal and the variation range and variation process of the excitation signal;

S02: Set the ambient temperature and the change range and change process of the ambient temperature;

S03: Set the aging time, collect and store the infrared image of the semiconductor chip to be tested during the aging period;

S04: analyze the electrical performance test results of the semiconductor chip to be tested;

S041: If the electrical properties of the semiconductor chip to be tested are normal, continue to perform steps S11 to S14;

S042: If the electrical properties of the semiconductor chip to be tested are abnormal, the test is ended.

This embodiment also provides a robustness testing system for a power semiconductor chip, including:

an image acquisition module, the image acquisition module is used to acquire an infrared image of the semiconductor chip to be tested;

an information acquisition module, the information acquisition module is used to acquire infrared information of each point Y in the infrared image space area;

temperature information calculation module, the temperature information calculation module is used to distribute and calculate the temperature information of Y points;

temperature gradient calculation module, the temperature gradient calculation module is used to calculate the temperature gradient of Y points respectively;

A space area division module, the space area division module is used to divide the overall space area of the infrared image into i small areas;

Small area temperature gradient acquisition module, the small area temperature gradient acquisition module is used to acquire the maximum temperature gradient in each small area, and configure the maximum temperature gradient in each small area as the temperature gradient of each small area;

Statistical module, the statistical module is used to count the temperature gradient of each small area, and draw a first histogram. The horizontal axis of the first histogram is the temperature gradient, and the vertical axis of the first histogram is the temperature gradient corresponding to the temperature gradient. The number of regions, sort the first histogram from large to small to form the second histogram;

The analysis module uses the Rayleigh distribution to fit the second histogram to obtain the root mean square value of the temperature gradient. When the root mean square value of the temperature gradient is greater than the first threshold, it is determined that the semiconductor chip to be tested is abnormal.

As shown in FIG. 8 , this embodiment also provides a robustness testing device for a power semiconductor chip, including:

Signal generation module, the signal generation module generates various excitation signals to impact the semiconductor chip to be tested;

The temperature control module controls and adjusts the ambient temperature of the semiconductor chip to be tested;

An electrical performance detection module, including an IV detection circuit and/or a CV detection circuit, used to detect the electrical performance of the semiconductor chip to be tested;

An infrared imaging module, including a camera, for obtaining an infrared image of the excited semiconductor chip to be tested;

The controller is used to judge whether the semiconductor chip to be tested is normal.

Further, in this embodiment, the controller can adjust the excitation signal, adjust the temperature, control the aging time, and control the electrical detection module to test the electrical performance of the semiconductor chip, and analyze the test results.

Specifically, the signal generating module provided in this embodiment can also manually adjust the excitation signal. In this embodiment, the excitation signal includes but is not limited to pulse signal and AC signal. According to the actual situation, the excitation signal form and signal parameters can be flexibly selected.

Specifically, the signal generating module provided in this embodiment further includes a bias circuit. When testing the LDMOS chip for P-band radar, first use the bias circuit to set the LDMOS chip for P-band radar to a static operating point, and then use the output excitation signal to output the excitation signal. Shock chip.

In conclusion, the robustness testing method for a power semiconductor chip provided in this embodiment can shorten the aging time, thereby improving the testing efficiency.

Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, and substitutions can be made in these embodiments without departing from the principle and spirit of the invention and modifications, the scope of the present invention is defined by the appended claims and their equivalents.

Claims (7)

1. a robustness testing method of a power semiconductor chip, is characterized in that, comprises: S11: Obtain an infrared image of the semiconductor chip to be tested; S12: Acquire infrared information of Y points in the infrared image space region; S13: Calculate the temperature information of the Y points respectively; S14: Calculate the temperature gradients of the Y points respectively; S15: Divide the overall spatial area of the infrared image into i small areas; S16: Obtain the maximum temperature gradient in each of the small regions, and configure the maximum temperature gradient in each of the small regions as the temperature gradient of each of the small regions; S17: Count the temperature gradients of each of the small regions, and draw a first histogram, where the horizontal axis of the first histogram is the temperature gradient, and the vertical axis of the first histogram is the temperature gradient For the number of corresponding small areas, sort the first histogram according to the number from large to small to form a second histogram; S18: Use Rayleigh distribution to fit the second histogram to obtain σ, and the Rayleigh Rayleigh distribution formula is:

Wherein, x is the sampling value of the temperature gradient at a certain point, and σ is the root mean square of the temperature gradient. When σ is greater than the first set value, the semiconductor chip to be tested is determined to be abnormal. 2. The robustness testing method of a power semiconductor chip according to claim 1, wherein the robustness testing method of the power semiconductor chip further comprises a constitution screening algorithm, and the constitution screening algorithm comprises: S21: Obtain n infrared images in the aging period; S22: Perform steps S12 to S18 on the n infrared images to obtain n Rayleigh distributions and their parameters σ ₁ , σ ₂ ... σ _n , for the parameters σ ₁ , σ ₂ ... σ _n Perform statistics and draw a third histogram; S23: Fitting the third histogram with Gaussian distribution N(μ, θ ² ) to obtain θ, where μ is the expectation of the root mean square of the temperature gradient, and θ is the standard of the root mean square of the temperature gradient Difference; S24: Compare the θ value with the second set value, and classify the quality of the semiconductor chip to be tested. 3. The robustness testing method of a power semiconductor chip according to claim 1, wherein the formula for calculating the temperature information of each point in the space region is: T(x,y)=αK(x,y)+β, Among them, K(x,y) is the infrared information of the point (x,y) in the infrared image, α is the first constant coefficient, which is used to amplify the infrared information, and β is the second constant coefficient, which is used to amplify the infrared information. The temperature information is converted into a positive value, and T(x,y) is the temperature information of the linearly mapped infrared image. 4. The robustness testing method of a power semiconductor chip according to claim 1, wherein the calculation formula of the temperature gradient at each point in the space region is:

i and j are unit vectors in the x and y directions,

is the partial differential operator, T is the temperature information,

is a vector,

the absolute value of

is the temperature gradient. 5. The robustness testing method of a power semiconductor chip according to claim 1, wherein the robustness testing method of the power semiconductor chip further comprises: S01: set the variation range and variation process of excitation signal and described excitation signal; S02: setting the ambient temperature and the variation range and variation process of the ambient temperature; S03: Set the aging time, collect and store the infrared image of the semiconductor chip to be tested during the aging period; S04: analyze the electrical performance test results of the semiconductor chip to be tested; S041: If the electrical properties of the semiconductor chip to be tested are normal, continue to perform steps S11 to S14; S042: If the electrical properties of the semiconductor chip to be tested are abnormal, end the test. 6. A robustness testing system for a power semiconductor chip, comprising: an image acquisition module, which is used to acquire an infrared image of the semiconductor chip to be tested; an information acquisition module, which is used to acquire infrared information of Y points in the infrared image space region; a temperature information calculation module, which is used to calculate the temperature information of the Y points respectively; a temperature gradient calculation module, the temperature gradient calculation module is used to calculate the temperature gradients of the Y points respectively; a space area division module, the space area division module is used to divide the overall space area of the infrared image into i small areas; A small area temperature gradient acquisition module, the small area temperature gradient acquisition module is used to acquire the maximum temperature gradient in each of the small areas, and configure the maximum temperature gradient in each of the small areas as the temperature gradient of each of the small areas ; A statistical module, the statistical module is used to perform statistics on the temperature gradient of each of the small regions, and draw a first histogram, where the horizontal axis of the first histogram is the temperature gradient, and the The vertical axis is the number of small regions corresponding to the temperature gradient, and the first histograms are sorted from large to small to form a second histogram; an analysis module, the analysis module uses the Rayleigh distribution to fit the second histogram to obtain the root mean square value of the temperature gradient, and when the root mean square value of the temperature gradient is greater than the first threshold, it is determined that the The semiconductor chip is abnormal. 7. A robustness testing device for a power semiconductor chip, characterized in that, comprising: a signal generating module, which generates various excitation signals to impact the semiconductor chip to be tested; a temperature control module, which controls and adjusts the ambient temperature of the semiconductor chip to be tested; an electrical performance detection module, used to detect the electrical performance of the semiconductor chip to be tested; An infrared imaging module, including a camera, for obtaining an infrared image of the excited semiconductor chip to be tested; and a controller, which is used for processing the infrared image and judging whether the semiconductor chip to be tested is normal.

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