CN111275197A - Computing method, apparatus, computer equipment and storage medium - Google Patents

Abstract

The present disclosure relates to an arithmetic method, an apparatus, a computer device and a storage medium. The combined processing device includes: a machine learning computing device, a general interconnection interface and other processing devices; the machine learning computing device interacts with other processing devices to jointly complete the computing operation specified by the user, wherein the combined processing device further includes: a storage device, The storage device is respectively connected with the machine learning computing device and other processing devices, and is used for saving the data of the machine learning computing device and other processing devices. The computing method, device, computer equipment and storage medium provided by the embodiments of the present disclosure have a wide range of applications, and have high processing efficiency and high processing speed for computing.

Description

Computing method, apparatus, computer equipment and storage medium

technical field

The present disclosure relates to the field of computer technology, and in particular, to a scalar type conversion instruction operation method, apparatus, computer device and storage medium.

Background technique

With the continuous development of science and technology, the use of machine learning, especially neural network algorithms, is becoming more and more extensive. It has been well used in image recognition, speech recognition, natural language processing and other fields. However, due to the increasing complexity of neural network algorithms, the types and quantities of data operations involved continue to increase. In the related art, the scalar type conversion operation on scalar data is inefficient and slow.

SUMMARY OF THE INVENTION

In view of this, the present disclosure proposes an operation method, apparatus, computer device and storage medium to improve the efficiency and speed of scalar type conversion operation on scalar data.

According to a first aspect of the present disclosure, there is provided an apparatus for processing a scalar type conversion instruction, the apparatus comprising:

The control module is used to parse the acquired scalar type conversion instruction, obtain the operation code and operation field of the scalar type conversion instruction, and obtain the pending operation required to execute the scalar type conversion instruction according to the operation code and the operation field scalar and target address, and determine the target data type and the initial data type of the scalar to be operated;

The operation module is configured to perform a scalar type conversion operation on the to-be-operated scalar of the initial data type according to the target data type, obtain an operation result, and store the operation result in the target address. the data type is the target data type,

The operation code is used to indicate that the operation performed by the scalar type conversion instruction on the data is a scalar type conversion operation, and the operation field includes the scalar address to be operated and the target address.

According to a second aspect of the present disclosure, there is provided a machine learning computing device, the device comprising:

One or more scalar type conversion instruction processing devices described in the first aspect above are used to obtain the scalar to be calculated and control information from other processing devices, and execute the specified machine learning operation, and transmit the execution result through the I/O interface. to other processing devices;

When the machine learning computing device includes a plurality of the scalar type conversion instruction processing devices, the plurality of the scalar type conversion instruction processing devices can be connected through a specific structure and data can be transmitted;

Wherein, a plurality of the scalar type conversion instruction processing devices are interconnected and transmit data through the fast peripheral device interconnection bus PCIE bus to support larger-scale machine learning operations; a plurality of the scalar type conversion instruction processing devices share the same The control system may have its own control system; a plurality of the scalar type conversion instruction processing devices share memory or have their own memory; the interconnection mode of the plurality of scalar type conversion instruction processing devices is any interconnection topology.

According to a third aspect of the present disclosure, there is provided a combined processing device, the device comprising:

The machine learning computing device, universal interconnection interface, and other processing devices described in the second aspect above;

The machine learning computing device interacts with the other processing devices to jointly complete the computing operation specified by the user.

According to a fourth aspect of the present disclosure, there is provided a machine learning chip, where the machine learning chip includes the machine learning computing device described in the second aspect or the combined processing device described in the third aspect.

According to a fifth aspect of the present disclosure, a machine learning chip packaging structure is provided, and the machine learning chip packaging structure includes the machine learning chip described in the fourth aspect.

According to a sixth aspect of the present disclosure, there is provided a board card including the machine learning chip packaging structure described in the fifth aspect.

According to a seventh aspect of the present disclosure, an electronic device is provided, and the electronic device includes the machine learning chip described in the fourth aspect or the board card described in the sixth aspect.

According to an eighth aspect of the present disclosure, a method for processing a scalar type conversion instruction is provided. The method is applied to an apparatus for processing a scalar type conversion instruction, and the method includes:

Analyzing the acquired scalar type conversion instruction to obtain the operation code and operation field of the scalar type conversion instruction, and obtaining the scalar to be operated and the target address required for executing the scalar type conversion instruction according to the operation code and the operation field, and determining the target data type and the initial data type of the to-be-operated scalar;

Perform a scalar type conversion operation on the to-be-operated scalar of the initial data type according to the target data type, obtain an operation result, and store the operation result in the target address, where the data type of the operation result is the target data type,

The operation code is used to indicate that the operation performed by the scalar type conversion instruction on the data is a scalar type conversion operation, and the operation field includes the scalar address to be operated and the target address.

According to a ninth aspect of the present disclosure, there is provided a non-volatile computer-readable storage medium having computer program instructions stored thereon, the computer program instructions implementing the above-described scalar type conversion instruction processing method when executed by a processor.

In some embodiments, the electronic device includes a data processing device, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a mobile phone, a driving recorder, a navigator, a sensor, a camera, a server, a cloud server, a camera, Cameras, projectors, watches, headphones, mobile storage, wearables, vehicles, home appliances, and/or medical equipment.

In some embodiments, the vehicles include airplanes, ships and/or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods; the medical Equipment includes MRI machines, ultrasound machines and/or electrocardiographs.

In the scalar type conversion instruction processing method, apparatus, computer equipment and storage medium provided by the embodiments of the present disclosure, the apparatus includes a control module and an operation module. The control module is used to parse the acquired scalar type conversion instruction, obtain the operation code and operation field of the scalar type conversion instruction, and obtain the scalar to be operated and the target address required to execute the scalar type conversion instruction according to the operation code and operation field, As well as determining the target data type and the initial data type of the scalar to be operated on. The operation module is used to perform scalar type conversion operation on the scalar to be operated on the initial data type according to the target data type, obtain the operation result, and store the operation result in the target address. The scalar type conversion instruction processing method, device, computer equipment and storage medium provided by the embodiments of the present disclosure have a wide range of applications, high processing efficiency and fast processing speed for scalar type conversion instructions, and high processing efficiency and processing speed for scalar type conversion. high speed.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the accompanying drawings.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure, and together with the description, serve to explain the principles of the disclosure.

FIG. 1 shows a block diagram of a scalar type conversion instruction processing apparatus according to an embodiment of the present disclosure.

2a-2f show block diagrams of a scalar type conversion instruction processing apparatus according to an embodiment of the present disclosure.

FIG. 3 shows a schematic diagram of an application scenario of an apparatus for processing a scalar type conversion instruction according to an embodiment of the present disclosure.

4a and 4b illustrate block diagrams of a combined processing apparatus according to an embodiment of the present disclosure.

FIG. 5 shows a schematic structural diagram of a board according to an embodiment of the present disclosure.

FIG. 6 shows a flowchart of a method for processing a scalar type conversion instruction according to an embodiment of the present disclosure.

Detailed ways

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, but not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present disclosure.

It should be understood that the terms "zeroth", "first", "second" and the like in the claims, description and drawings of the present disclosure are used to distinguish different objects, rather than to describe a specific order. The terms "comprising" and "comprising" as used in the specification and claims of this disclosure indicate the presence of the described features, integers, steps, operations, elements and/or components, but do not exclude one or more other features, integers , step, operation, element, component and/or the presence or addition of a collection thereof.

It should also be understood that the terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to limit the present disclosure. As used in this disclosure and the claims, the singular forms "a," "an," and "the" are intended to include the plural unless the context clearly dictates otherwise. It should further be understood that, as used in this disclosure and the claims, the term "and/or" refers to and including any and all possible combinations of one or more of the associated listed items.

As used in this specification and in the claims, the term "if" may be contextually interpreted as "when" or "once" or "in response to determining" or "in response to detecting". Similarly, the phrases "if it is determined" or "if the [described condition or event] is detected" may be interpreted, depending on the context, to mean "once it is determined" or "in response to the determination" or "once the [described condition or event] is detected. ]" or "in response to detection of the [described condition or event]".

Due to the widespread use of neural network algorithms and the continuous improvement of computer hardware computing capabilities, the types and quantities of data operations involved in practical applications continue to increase. Due to the variety of programming languages, in order to realize the operation process of scalar operations in different language environments, in the related art, since there are no scalar type conversion instructions that can be widely applied to various programming languages at this stage, technicians need to customize corresponding The type conversion of scalar is realized by multiple instructions of its programming language environment, resulting in low efficiency and slow speed of type conversion. The present disclosure provides a type conversion instruction processing method, device, computer equipment and storage medium, which can realize scalar type conversion with only one instruction, and can significantly improve the efficiency and speed of scalar type conversion.

FIG. 1 shows a block diagram of a scalar type conversion instruction processing apparatus according to an embodiment of the present disclosure. As shown in FIG. 1 , the device includes a control module 11 and an arithmetic module 12 .

The control module 11 is used to parse the acquired scalar type conversion instruction, obtain the operation code and operation field of the scalar type conversion instruction, and obtain the scalar to be operated and the target required for executing the scalar type conversion instruction according to the operation code and operation field address, and determine the destination data type and the initial data type of the scalar to be operated on. The operation code is used to indicate that the operation performed by the scalar type conversion instruction on the data is a scalar type conversion operation, and the operation domain includes the scalar address to be operated and the target address.

The operation module 12 is configured to perform scalar type conversion operation on the scalar to be operated on the initial data type according to the target data type, obtain the operation result, and store the operation result in the target address. The data type of the operation result is the target data type.

In this embodiment, the control module may acquire the scalar to be calculated from the address of the scalar to be calculated. The control module can obtain the scalar type conversion instruction and the to-be-operated scalar through the data input and output unit, and the data input and output unit can be one or more data I/O interfaces or I/O pins.

In this embodiment, the operation code may be the part of the instruction or field (usually represented by code) specified in the computer program to perform the operation, and the instruction sequence number, which is used to inform the device that executes the instruction which instruction needs to be executed. . The operation domain may be the source of all data required to execute the corresponding instruction, and all the data required to execute the corresponding instruction includes parameter data, scalar to be operated, corresponding operation method, and so on. For a scalar type conversion instruction, it must include an operation code and an operation field, wherein the operation field at least includes the address of the scalar to be operated and the target address.

It should be understood that those skilled in the art can set the instruction format of the scalar type conversion instruction and the included operation codes and operation fields as required, which is not limited in the present disclosure.

In this embodiment, the device may include one or more control modules and one or more operation modules, and the number of control modules and operation modules may be set according to actual needs, which is not limited in the present disclosure. When the device includes a control module, the control module can receive a scalar type conversion instruction, and control one or more operation modules to perform a scalar type conversion operation. When the apparatus includes multiple control modules, the multiple control modules can respectively receive scalar type conversion instructions, and control one or more corresponding operation modules to perform scalar type conversion operations.

The apparatus for processing a scalar type conversion instruction provided by an embodiment of the present disclosure includes a control module and an operation module. The control module is used to parse the acquired scalar type conversion instruction, obtain the operation code and operation field of the scalar type conversion instruction, and obtain the scalar to be operated and the target address required to execute the scalar type conversion instruction according to the operation code and operation field, As well as determining the target data type and the initial data type of the scalar to be operated on. The operation module is used to perform scalar type conversion operation on the scalar to be operated on the initial data type according to the target data type, obtain the operation result, and store the operation result in the target address. The scalar type conversion instruction processing device provided by the embodiment of the present disclosure has a wide range of applications, and has high processing efficiency and fast processing speed for scalar type conversion instructions, and high processing efficiency and fast processing speed for scalar type conversion.

Fig. 2a shows a block diagram of a scalar type conversion instruction processing apparatus according to an embodiment of the present disclosure. In a possible implementation manner, as shown in FIG. 2a, the operation module 12 may include a plurality of scalar operators 120 for performing scalar type conversion operations.

In this implementation manner, the operation module may also include a scalar operator. The number of scalar operators may be set according to the size of the data required to perform the scalar type conversion operation, the processing speed and efficiency of the scalar type conversion operation, etc., which is not limited in the present disclosure.

FIG. 2b shows a block diagram of a scalar type conversion instruction processing apparatus according to an embodiment of the present disclosure. In a possible implementation manner, as shown in FIG. 2 b , the operation module 12 may include a master operation sub-module 121 and a plurality of slave operation sub-modules 122 . The main operation sub-module 121 may include a plurality of scalar operators 120 (not shown in the figure).

The main operation sub-module 121 is configured to use a plurality of scalar operators 120 to perform a scalar type conversion operation, obtain an operation result, and store the operation result in a target address.

In a possible implementation manner, the control module 11 is further configured to parse the acquired calculation instruction, obtain the operation domain and operation code of the calculation instruction, and obtain the waiting list required to execute the calculation instruction according to the operation domain and the operation code. Operational data. The operation module 12 is further configured to perform operation on the data to be operated according to the calculation instruction to obtain the calculation result of the calculation instruction. Wherein, the operation module may include a plurality of operators for executing operations corresponding to the operation types of the calculation instructions.

In this implementation manner, the calculation instructions may be other instructions for performing arithmetic operations, logical operations and other operations on data such as scalars, vectors, matrices, and tensors. Those skilled in the art can set the calculation instructions according to actual needs. This is not limited.

In this implementation manner, the operator may include an operator, such as an adder, a divider, a multiplier, and a comparator, that can perform arithmetic operations, logical operations, and other operations on data. The type and quantity of arithmetic units can be set according to the size of the data volume of the operation to be performed, the type of operation, the processing speed and efficiency of the operation on the data, etc., which are not limited in the present disclosure.

In a possible implementation manner, the control module 11 is further configured to parse the calculation instruction to obtain multiple operation instructions, and send the data to be calculated and the multiple operation instructions to the main operation sub-module 121 .

The master operation sub-module 121 is used to perform pre-order processing on the data to be operated, and transmit data and operation instructions with a plurality of slave operation sub-modules 122 .

The slave operation sub-module 122 is configured to perform intermediate operations in parallel according to the data and operation instructions transmitted from the master operation sub-module 121 to obtain multiple intermediate results, and transmit the multiple intermediate results to the master operation sub-module 122 .

The main operation sub-module 121 is further configured to perform subsequent processing on a plurality of intermediate results, obtain the calculation result of the calculation instruction, and store the calculation result in the corresponding address.

In this implementation manner, when the calculation instruction is an operation performed on scalar or vector data, the apparatus can control the main operation sub-module to use the operator therein to perform an operation corresponding to the calculation instruction. When the calculation instruction is to perform operations on data whose dimensions are greater than or equal to 2, such as matrices and tensors, the apparatus may control the operation sub-module to perform operations corresponding to the calculation instructions using the operators therein.

It should be noted that those skilled in the art can set the connection mode between the main operation sub-module and multiple slave operation sub-modules according to actual needs, so as to realize the architecture setting of the operation module. For example, the architecture of the operation module can be "H"-type architecture, array-type architecture, tree-type architecture, etc., are not limited in the present disclosure.

FIG. 2c shows a block diagram of a scalar type conversion instruction processing apparatus according to an embodiment of the present disclosure. In a possible implementation manner, as shown in FIG. 2c, the operation module 12 may further include one or more branch operation sub-modules 123, and the branch operation sub-module 123 is used for forwarding the master operation sub-module 121 and the slave operation sub-module 122 between data and/or operation instructions. Wherein, the main operation sub-module 121 is connected with one or more branch operation sub-modules 123 . In this way, the main operation sub-module, the branch operation sub-module and the slave operation sub-module in the operation module are connected by an "H" type structure, and data and/or operation instructions are forwarded through the branch operation sub-module, saving the need for the main operation sub-module. resource consumption, thereby improving the processing speed of instructions.

FIG. 2d shows a block diagram of a scalar type conversion instruction processing apparatus according to an embodiment of the present disclosure. In a possible implementation manner, as shown in FIG. 2d , a plurality of slave operation sub-modules 122 are distributed in an array.

Each slave operation sub-module 122 is connected to other adjacent slave operation sub-modules 122, the master operation sub-module 121 is connected to k slave operation sub-modules 122 in the plurality of slave operation sub-modules 122, and the k slave operation sub-modules 122 are : n slave operation submodules 122 in the first row, n slave operation submodules 122 in the mth row, and m slave operation submodules 122 in the first column.

Among them, as shown in Figure 2d, the k slave operation submodules only include n slave operation submodules in the first row, n slave operation submodules in the mth row, and m slave operation submodules in the first column, that is, The k slave operation submodules are slave operation submodules that are directly connected to the master operation submodule among the plurality of slave operation submodules. The k slave operation submodules are used for data and instruction forwarding between the master operation submodule and a plurality of slave operation submodules. In this way, the plurality of slave operation sub-modules are distributed in an array, which can improve the speed at which the master operation sub-module sends data and/or operation instructions to the slave operation sub-modules, thereby increasing the instruction processing speed.

FIG. 2e shows a block diagram of a scalar type conversion instruction processing apparatus according to an embodiment of the present disclosure. In a possible implementation manner, as shown in FIG. 2e , the operation module may further include a tree-type sub-module 124 . The tree-type sub-module 124 includes a root port 401 and a plurality of branch ports 402 . The root port 401 is connected to the master operation sub-module 121 , and the multiple branch ports 402 are respectively connected to the multiple slave operation sub-modules 122 . The tree-type sub-module 124 has the function of sending and receiving, and is used to forward data and/or operation instructions between the master operation sub-module 121 and the slave operation sub-module 122 . In this way, the operation modules are connected in a tree structure through the function of the tree-type sub-module, and the forwarding function of the tree-type sub-module can be used to improve the speed at which the master operation sub-module sends data and/or operation instructions to the slave operation sub-module, thereby improving the The processing speed of the instruction.

In a possible implementation manner, the tree-type sub-module 124 may be an optional result of the apparatus, which may include at least one level of nodes. The node is a line structure with forwarding function, and the node itself does not have the computing function. The node at the lowest level is connected to the slave operation sub-module to forward data and/or operation instructions between the master operation sub-module 121 and the slave operation sub-module 122 . In particular, if the tree-type sub-module has zero-level nodes, the device does not need the tree-type sub-module.

In a possible implementation manner, the tree sub-module 124 may include multiple nodes in an n-ary tree structure, and the multiple nodes in the n-ary tree structure may have multiple layers.

For example, FIG. 2f shows a block diagram of a scalar type conversion instruction processing apparatus according to an embodiment of the present disclosure. As shown in FIG. 2f , the n-ary tree structure may be a binary tree structure, and the tree-type sub-module includes 2-layer nodes 01 . The lowermost node 01 is connected to the slave operation sub-module 122 to forward data and/or operation instructions between the master operation sub-module 121 and the slave operation sub-module 122 .

In this implementation manner, the n-ary tree structure may also be a ternary tree structure, etc., and n is a positive integer greater than or equal to 2. Those skilled in the art can set n in the n-ary tree structure and the number of layers of nodes in the n-ary tree structure as required, which is not limited in the present disclosure.

In a possible implementation manner, the operation domain may further include an initial data type and a target data type. The control module 11 is further configured to determine the target data type and the initial data type of the to-be-operated scalar according to the operation domain.

In one possible implementation, the opcode can also be used to indicate the initial data type and the target data type. The control module 11 is further configured to determine the target data type and the initial data type of the to-be-operated scalar according to the operation code.

In a possible implementation manner, when the initial data type and/or target data type cannot be determined according to either the operation code or the operation domain, the initial data type and/or target data type may be determined according to the preset default initial data type and default target data type. or the target data type. The preset default initial data type may be determined as the initial data type of the current scalar type conversion instruction, and the preset default target data type may be determined as the current target data type of the scalar type conversion instruction. Those skilled in the art can set the determination manner of the target data type and the initial data type according to actual needs, which is not limited in the present disclosure.

In a possible implementation manner, the target data type may include any one of 16-bit floating point numbers, 32-bit floating point numbers, 48-bit floating point numbers, 16-bit integers, 32-bit integers, and 48-bit integers, and the initial data type may be Including any one of 16-bit signed number, 32-bit signed number, 48-bit signed number, 16-bit unsigned number, 32-bit unsigned number, 48-bit unsigned number and pointer data types.

In this implementation manner, the target data type and the initial data type can also be data types such as 64-bit integers. Those skilled in the art can set the target data type and initial data type according to actual needs, as long as the target data type and the initial data type are ensured The data types indicated by the data types only need to be different, which is not limited in the present disclosure.

In this implementation manner, identifiers (or codes) such as the number and name of the target data type and initial data type can be set to determine the target indicated by the scalar type conversion instruction according to the identifier (or code) in the scalar type conversion instruction Data types and initial data types. For example, you can set the identity of 16-bit floating-point numbers to cvtf16, the identity of 32-bit floating-point numbers to cvtf32, the identity of 48-bit floating-point numbers to cvtf48, the identity of 16-bit integers to be set to cvti16, and the identity of 32-bit integers to be set to cvti32 and set the identity of the 48-bit integer to cvti48. You can set the 16-bit signed number to s16, 32-bit signed number to s32, 48-bit signed number to s48, 16-bit unsigned number to u16, 32-bit unsigned The identifier of the number is set to u32, the identifier of the 48-bit unsigned number is set to u48 and the identifier of the pointer data type is set to ptr. Those skilled in the art can set the identifiers of the target data type and the initial data type according to actual needs, which is not limited in the present disclosure.

In a possible implementation manner, as shown in FIGS. 2 a to 2 f , the apparatus may further include a storage module 13 . The storage module 13 is used for storing the scalar to be calculated.

In this implementation manner, the storage module may include one or more of a cache and a register, the cache may include a temporary cache, and may also include at least one NRAM (Neuron Random Access Memory, neuron random access memory). The cache can be used to store the data to be calculated, and the register can be used to store the scalar to be calculated.

In one possible implementation, the cache may include a neuron cache. The neuron cache, that is, the above-mentioned neuron random access memory, may be used to store neuron data in the data to be operated, and the neuron data may include neuron vector data. The data to be operated includes data related to scalar type conversion, and/or data related to operations of other computing instructions.

In a possible implementation manner, the apparatus may further include a direct memory access module for reading or storing data from the storage module.

In a possible implementation manner, as shown in FIGS. 2 a to 2 f , the control module 11 may include an instruction storage sub-module 111 , an instruction processing sub-module 112 and a queue storage sub-module 113 .

The instruction storage sub-module 111 is used for storing scalar type conversion instructions.

The instruction processing sub-module 112 is configured to parse the scalar type conversion instruction to obtain the operation code and operation field of the scalar type conversion instruction.

The queue storage sub-module 113 is used to store an instruction queue, and the instruction queue includes a plurality of instructions to be executed sequentially arranged in an execution order, and the multiple instructions to be executed may include scalar type conversion instructions.

In this implementation manner, the to-be-executed instruction may also include a calculation instruction that is related to or irrelevant to the scalar type conversion instruction, which can be set by those skilled in the art according to actual needs, which is not limited in the present disclosure. An instruction queue can be obtained by arranging the execution order of multiple instructions to be executed according to the receiving time, priority level, etc. of the instructions to be executed, so as to execute the multiple instructions to be executed in sequence according to the instruction queue.

In a possible implementation manner, as shown in FIGS. 2 a to 2 f , the control module 11 may include a dependency relationship processing sub-module 114 .

The dependency relationship processing sub-module 114 is configured to cache the first to-be-executed instruction in the In the storage sub-module 111 , after the execution of the zeroth to-be-executed instruction is completed, the first to-be-executed instruction is extracted from the instruction storage sub-module 111 and sent to the operation module 12 . Wherein, the first to-be-executed instruction and the zeroth to-be-executed instruction are instructions in a plurality of to-be-executed instructions.

Wherein, the relationship between the first instruction to be executed and the zeroth instruction to be executed before the first instruction to be executed includes: a first storage address range for storing data required by the first instruction to be executed and data required for storing the zeroth instruction to be executed The zeroth memory address range of has overlapping regions. Conversely, if there is no association between the first instruction to be executed and the zeroth instruction to be executed, it may be that the first storage address interval and the zeroth storage address interval have no overlapping area.

In this way, according to the dependencies between the to-be-executed instructions, after the previous to-be-executed instruction is executed, the subsequent to-be-executed instruction is executed to ensure the accuracy of the operation result.

In a possible implementation, the instruction format of the scalar type conversion instruction may be:

scalar dst src0 opcode.type

Among them, scalar is the opcode of the scalar type conversion instruction, and dst, src0, and opcode.type are the operation fields of the scalar type conversion instruction. where dst is the destination address. src0 is the scalar address to be operated on. The opcode in opcode.type is the target data type, and the type in opcode.type is the initial data type of the scalar to be operated.

In a possible implementation manner, the instruction format of the scalar type conversion instruction may also be:

opcode.scalar.type dstsrc0

Among them, opcode.scalar.type is the opcode of the scalar type conversion instruction, and dst and src0 are the operation fields of the scalar type conversion instruction. Among them, opcode in opcode.scalar.type is used to indicate the target data type, type in opcode.scalar.type is used to indicate the initial data type of the scalar to be operated, and scalar in opcode.scalar.type is used to indicate that the instruction is Scalar type conversion instructions. dst is the destination address, and src0 is the address of the scalar to be computed.

It should be understood that those skilled in the art can set the operation code of the scalar type conversion instruction, the location of the operation code and the operation field in the instruction format as required, which is not limited in the present disclosure.

In a possible implementation manner, the apparatus may be provided in a graphics processing unit (Graphics Processing Unit, GPU for short), a central processing unit (Central Processing Unit, CPU for short), and an embedded neural-network processing unit (Neural-network Processing Unit, abbreviated as NPU) among one or more of them.

It should be noted that although the above-mentioned embodiment is used as an example to describe the scalar type conversion instruction processing apparatus as above, those skilled in the art can understand that the present disclosure should not be limited thereto. In fact, the user can flexibly set each module according to personal preferences and/or actual application scenarios, as long as it conforms to the technical solutions of the present disclosure.

Application example

In the following, an application example according to the embodiment of the present disclosure is given in conjunction with "using a scalar type conversion instruction processing apparatus to perform a scalar type conversion operation" as an exemplary application scenario, so as to facilitate the understanding of the flow of the scalar type conversion instruction processing apparatus. Those skilled in the art should understand that the following application examples are only for the purpose of facilitating the understanding of the embodiments of the present disclosure, and should not be regarded as limitations of the embodiments of the present disclosure.

FIG. 3 shows a schematic diagram of an application scenario of an apparatus for processing a scalar type conversion instruction according to an embodiment of the present disclosure. As shown in FIG. 3 , the process of processing the scalar type conversion instruction by the scalar type conversion instruction processing device is as follows:

The control module 11 parses the acquired scalar type conversion instruction 1 (for example, the scalar type conversion instruction 1 is scalar 500100 cvtf16.u32), and obtains the operation code and operation field of the scalar type conversion instruction 1. Among them, the opcode of the scalar type conversion instruction 1 is scalar, the target address is 500, the address of the scalar to be operated is 100, the target data type is cvtf16 (that is, 16 is a floating-point number), and the initial data type of the scalar to be operated is u32 (also i.e. 32-bit unsigned number). The control module 11 acquires the scalar to be calculated from the address 100 of the scalar to be calculated.

The operation module 12 performs a scalar type conversion operation on the scalar to be operated on the initial data type according to the target data type (that is, converts the data type of the 32-bit unsigned scalar to be operated into a floating-point number of 16), obtains the operation result, and calculates the operation result. The result is stored in target address 500.

For the working process of the above modules, reference may be made to the above related descriptions.

In this way, the scalar type conversion instruction processing device can efficiently and quickly process the scalar type conversion instruction, and the processing efficiency and processing speed of the scalar type conversion are high.

The present disclosure provides a machine learning computing device. The machine learning computing device may include one or more of the above-mentioned scalar type conversion instruction processing devices, which are used to obtain the scalar to be computed and control information from other processing devices, and execute specified machine learning operations. . The machine learning computing device can obtain scalar type conversion instructions from other machine learning computing devices or non-machine learning computing devices, and transmit the execution results to peripheral devices (also called other processing devices) through the I/O interface. Peripherals such as camera, monitor, mouse, keyboard, network card, wifi interface, server. When more than one scalar type conversion instruction processing device is included, the scalar type conversion instruction processing devices can be linked through a specific structure and transmit data, for example, interconnect and transmit data through the PCIE bus to support larger-scale neural networks operation. At this time, the same control system can be shared, or there can be independent control systems; memory can be shared, or each accelerator can have its own memory. In addition, the interconnection method can be any interconnection topology.

The machine learning computing device has high compatibility and can be connected with various types of servers through the PCIE interface.

FIG. 4a shows a block diagram of a combined processing apparatus according to an embodiment of the present disclosure. As shown in Fig. 4a, the combined processing device includes the above-mentioned machine learning computing device, a general interconnection interface and other processing devices. The machine learning computing device interacts with other processing devices to jointly complete the operation specified by the user.

Other processing devices include one or more processor types among general-purpose/special-purpose processors such as a central processing unit (CPU), a graphics processing unit (GPU), and a neural network processor. The number of processors included in other processing devices is not limited. Other processing devices serve as the interface between the machine learning computing device and external data and control, including data transfer, to complete the basic control of starting and stopping the machine learning computing device; other processing devices can also cooperate with the machine learning computing device to complete computing tasks.

A universal interconnect interface for transferring data and control instructions between machine learning computing devices and other processing devices. The machine learning computing device obtains required input data from other processing devices, and writes it into a storage device on-chip of the machine learning computing device; it can obtain control instructions from other processing devices and write it into the control cache on the machine learning computing device chip; The data in the storage module of the machine learning computing device can be read and transmitted to other processing devices.

FIG. 4b shows a block diagram of a combined processing apparatus according to an embodiment of the present disclosure. In a possible implementation manner, as shown in FIG. 4b, the combined processing device may further include a storage device, and the storage device is respectively connected to the machine learning computing device and the other processing devices. The storage device is used to save data in the machine learning computing device and the other processing devices, and is especially suitable for data that cannot be fully stored in the internal storage of the machine learning computing device or other processing devices.

The combined processing device can be used as an SOC system for mobile phones, robots, drones, video surveillance equipment and other equipment, effectively reducing the core area of the control part, improving the processing speed and reducing the overall power consumption. In this case, the general interconnection interface of the combined processing device is connected to certain components of the apparatus. Some components such as camera, monitor, mouse, keyboard, network card, wifi interface.

The present disclosure provides a machine learning chip, which includes the above-mentioned machine learning computing device or combined processing device.

The present disclosure provides a machine learning chip packaging structure, and the machine learning chip packaging structure includes the above-mentioned machine learning chip.

The present disclosure provides a board, and FIG. 5 shows a schematic structural diagram of the board according to an embodiment of the present disclosure. As shown in FIG. 5 , the board includes the above-mentioned machine learning chip packaging structure or the above-mentioned machine learning chip. In addition to the machine learning chip 389 , the board may also include other supporting components, including but not limited to: a storage device 390 , an interface device 391 and a control device 392 .

The storage device 390 is connected to the machine learning chip 389 (or the machine learning chip in the machine learning chip package structure) through a bus for storing data. The memory device 390 may include groups of memory cells 393 . Each group of storage units 393 is connected to the machine learning chip 389 through a bus. It can be understood that each group of storage units 393 may be DDR SDRAM (English: Double Data Rate SDRAM, double-rate synchronous dynamic random access memory).

DDR does not need to increase the clock frequency to double the speed of SDRAM. DDR allows data to be read out on both the rising and falling edges of the clock pulse. DDR is twice as fast as standard SDRAM.

In one embodiment, the memory device 390 may include four sets of memory cells 393 . Each set of memory cells 393 may include a plurality of DDR4 particles (chips). In one embodiment, the machine learning chip 389 may include four 72-bit DDR4 controllers inside, where 64 bits of the 72-bit DDR4 controllers are used for data transmission and 8 bits are used for ECC verification. It can be understood that when DDR4-3200 particles are used in each group of storage units 393, the theoretical bandwidth of data transmission can reach 25600MB/s.

In one embodiment, each set of memory cells 393 includes a plurality of double-rate synchronous dynamic random access memories arranged in parallel. DDR can transfer data twice in one clock cycle. A controller for controlling the DDR is provided in the machine learning chip 389 for controlling data transmission and data storage of each storage unit 393 .

The interface device 391 is electrically connected to the machine learning chip 389 (or the machine learning chip within the machine learning chip package structure). The interface device 391 is used to realize data transmission between the machine learning chip 389 and an external device (such as a server or a computer). For example, in one embodiment, the interface device 391 may be a standard PCIE interface. For example, the data to be processed is transmitted by the server to the machine learning chip 289 through a standard PCIE interface to realize data transfer. Preferably, when the PCIE 3.0X 16 interface is used for transmission, the theoretical bandwidth can reach 16000MB/s. In another embodiment, the interface device 391 may also be other interfaces, and the present disclosure does not limit the specific expression forms of the other interfaces, as long as the interface device can realize the switching function. In addition, the calculation result of the machine learning chip is still transmitted back to the external device (such as a server) by the interface device.

The control device 392 is electrically connected to the machine learning chip 389 . The control device 392 is used to monitor the state of the machine learning chip 389 . Specifically, the machine learning chip 389 and the control device 392 may be electrically connected through an SPI interface. The control device 392 may include a Micro Controller Unit (MCU). For example, the machine learning chip 389 may include multiple processing chips, multiple processing cores or multiple processing circuits, and may drive multiple loads. Therefore, the machine learning chip 389 can be in different working states such as multi-load and light-load. The control device can realize the regulation of the working states of multiple processing chips, multiple processing and/or multiple processing circuits in the machine learning chip.

The present disclosure provides an electronic device including the above-mentioned machine learning chip or board.

Electronic equipment may include data processing devices, computer equipment, robots, computers, printers, scanners, tablet computers, smart terminals, mobile phones, driving recorders, navigators, sensors, cameras, servers, cloud servers, cameras, video cameras, and projectors , watches, headphones, mobile storage, wearables, vehicles, home appliances, and/or medical equipment.

Vehicles may include aircraft, ships and/or vehicles. Household appliances may include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods. Medical equipment may include MRI machines, ultrasound machines and/or electrocardiographs.

FIG. 6 shows a flowchart of a method for processing a scalar type conversion instruction according to an embodiment of the present disclosure. The method can be applied to a computer device that includes a memory and a processor, wherein the memory is used to store data used in the process of executing the method; the processor is used to execute related processing and operation steps, such as executing the following steps S51 and steps S52. As shown in FIG. 6, the method is applied to the above-mentioned scalar type conversion instruction processing apparatus, and the method includes step S51 and step S52.

In step S51, the acquired scalar type conversion instruction is parsed by the control module, the operation code and operation field of the scalar type conversion instruction are obtained, and the scalar to be operated required for executing the scalar type conversion instruction is obtained according to the operation code and operation field and the destination address, as well as determine the destination data type and the initial data type of the scalar to be operated on. The operation code is used to indicate that the operation performed by the scalar type conversion instruction on the data is a scalar type conversion operation, and the operation domain includes the scalar address to be operated and the target address.

In step S52, use the operation module to perform scalar type conversion operation on the scalar to be operated on the initial data type according to the target data type, obtain the operation result, and store the operation result in the target address, and the data type of the operation result is the target data type.

In a possible implementation manner, performing a scalar type conversion operation on the scalar to be operated on the initial data type according to the target data type, which may include:

Use multiple scalar operators in the operation module to perform scalar type conversion operations.

In a possible implementation manner, the operation module includes a master operation submodule and multiple slave operation submodules, and the master operation submodule includes multiple scalar operators. Wherein, step S52 may include:

Use multiple scalar operators in the main operation sub-module to perform scalar type conversion operation, obtain the operation result, and store the operation result in the target address.

In a possible implementation manner, the operation domain may further include an initial data type and a target data type, and step S51 may include: determining the target data type and the initial data type of the scalar to be operated according to the operation domain.

In a possible implementation manner, the operation code is also used to indicate the initial data type and the target data type, and step S51 may include: determining the target data type and the initial data type of the scalar to be operated according to the operation code

In a possible implementation manner, the target data type may include any one of 16-bit floating point numbers, 32-bit floating point numbers, 48-bit floating point numbers, 16-bit integers, 32-bit integers, and 48-bit integers, and the initial data type may be Including any one of 16-bit signed number, 32-bit signed number, 48-bit signed number, 16-bit unsigned number, 32-bit unsigned number, 48-bit unsigned number and pointer data types.

In a possible implementation manner, the method may further include: using a storage module of the device to store the scalar to be calculated,

Wherein, the storage module includes at least one of a register and a cache,

The cache is used to store the data to be operated, and the cache includes at least one neuron cache NRAM;

Register, used to store the scalar to be operated;

The neuron cache is used to store neuron data in the data to be operated, and the neuron data includes neuron vector data.

In a possible implementation, step S51 may include:

Store scalar type conversion instructions;

Parse the scalar type conversion instruction to obtain the opcode and operation field of the scalar type conversion instruction;

An instruction queue is stored, and the instruction queue includes multiple instructions to be executed sequentially arranged in an execution order, and the multiple instructions to be executed may include scalar type conversion instructions.

In a possible implementation, the method may further include:

When it is determined that the first to-be-executed instruction in the plurality of to-be-executed instructions has an associated relationship with the zeroth to-be-executed instruction before the first to-be-executed instruction, the first to-be-executed instruction is cached, and after it is determined that the zeroth to-be-executed instruction is executed , control the execution of the first instruction to be executed,

Wherein, the relationship between the first instruction to be executed and the zeroth instruction to be executed before the first instruction to be executed includes:

The first storage address interval storing the data required by the first instruction to be executed and the zeroth storage address interval storing the data required by the zeroth instruction to be executed have an overlapping area.

It should be noted that although the above-mentioned embodiment is used as an example to describe the processing method of a scalar type conversion instruction as above, those skilled in the art can understand that the present disclosure should not be limited thereto. In fact, the user can flexibly set each step according to personal preference and/or actual application scenarios, as long as it conforms to the technical solutions of the present disclosure.

The scalar type conversion instruction processing method provided by the embodiment of the present disclosure has a wide range of applications, and has high processing efficiency and fast processing speed for scalar type conversion instructions, and high processing efficiency and fast processing speed for scalar type conversion.

The present disclosure also provides a non-volatile computer-readable storage medium on which computer program instructions are stored, and when the computer program instructions are executed by a processor, implement the above-mentioned scalar type conversion instruction processing method.

It should be noted that, for the sake of simple description, the foregoing method embodiments are all expressed as a series of action combinations, but those skilled in the art should know that the present disclosure is not limited by the described action sequence. As in accordance with the present disclosure, certain steps may be performed in other orders or concurrently. Secondly, those skilled in the art should also know that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present disclosure.

It should be further noted that although the steps in the flowchart of FIG. 6 are displayed in sequence according to the arrows, these steps are not necessarily executed in the sequence indicated by the arrows. Unless explicitly stated herein, the execution of these steps is not strictly limited to the order, and these steps may be performed in other orders. Moreover, at least a part of the steps in FIG. 6 may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed and completed at the same time, but may be executed at different times. The execution of these sub-steps or stages The sequence is also not necessarily sequential, but may be performed alternately or alternately with other steps or sub-steps of other steps or at least a portion of a phase.

It should be understood that the above device embodiments are only illustrative, and the device of the present disclosure can also be implemented in other ways. For example, the division of units/modules described in the above embodiments is only a logical function division, and other division methods may be used in actual implementation. For example, multiple units, modules or components may be combined, or may be integrated into another system, or some features may be omitted or not implemented.

In addition, unless otherwise specified, each functional unit/module in each embodiment of the present disclosure may be integrated into one unit/module, or each unit/module may exist physically alone, or two or more units/modules may exist. modules are integrated together. The above-mentioned integrated units/modules can be implemented in the form of hardware, or can be implemented in the form of software program modules.

If the integrated unit/module is implemented in the form of hardware, the hardware may be a digital circuit, an analog circuit, or the like. Physical implementations of hardware structures include, but are not limited to, transistors, memristors, and the like. Unless otherwise specified, the above-mentioned storage module can be any suitable magnetic storage medium or magneto-optical storage medium, for example, resistive random access memory (RRAM), dynamic random access memory (DRAM) Memory), static random access memory SRAM (Static Random-Access Memory), enhanced dynamic random access memory EDRAM (Enhanced Dynamic Random Access Memory), high bandwidth memory HBM (High-Bandwidth Memory), hybrid storage cube HMC (Hybrid Memory) Cube) and so on.

The integrated unit/module, if implemented in the form of a software program module and sold or used as a stand-alone product, may be stored in a computer readable memory. Based on this understanding, the technical solutions of the present disclosure essentially or the part that contributes to the prior art or the whole or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a memory, Several instructions are included to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present disclosure. The aforementioned memory includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program codes.

In the above-mentioned embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference may be made to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, it should be It is considered to be the range described in this specification.

The foregoing can be better understood in accordance with the following terms:

Clause A1. A scalar type conversion instruction processing apparatus, the apparatus comprising:

The control module is used to parse the acquired scalar type conversion instruction, obtain the operation code and operation field of the scalar type conversion instruction, and obtain the pending operation required to execute the scalar type conversion instruction according to the operation code and the operation field scalar and target address, and determine the target data type and the initial data type of the scalar to be operated;

The operation module is configured to perform a scalar type conversion operation on the to-be-operated scalar of the initial data type according to the target data type, obtain an operation result, and store the operation result in the target address. the data type is the target data type,

The operation code is used to indicate that the operation performed by the scalar type conversion instruction on the data is a scalar type conversion operation, and the operation field includes the scalar address to be operated and the target address.

Clause A2. The device according to Clause A1, the operation module, comprising:

a plurality of scalar operators for performing the scalar type conversion operation.

Clause A3. The apparatus of Clause A2, the operation module comprising a master operation sub-module and a plurality of slave operation sub-modules, the master operation sub-module including the plurality of scalar operators,

The main operation submodule is configured to use the plurality of scalar operators to perform the scalar type conversion operation, obtain an operation result, and store the operation result in the target address.

Clause A4. The apparatus according to Clause A1, wherein the operation domain further includes an initial data type and a target data type,

Wherein, the control module is further configured to determine the target data type and the initial data type of the to-be-operated scalar according to the operation domain.

Clause A5. The apparatus of Clause A1, wherein the opcode is further used to indicate an initial data type and a target data type,

Wherein, the control module is further configured to determine the target data type and the initial data type of the to-be-operated scalar according to the operation code.

Clause A6. The apparatus according to Clause A1, wherein the target data type includes any one of 16-bit floating-point numbers, 32-bit floating-point numbers, 48-bit floating-point numbers, 16-bit integers, 32-bit integers, and 48-bit integers, so The initial data type includes any one of 16-bit signed number, 32-bit signed number, 48-bit signed number, 16-bit unsigned number, 32-bit unsigned number, 48-bit unsigned number and pointer data types.

Clause A7. The apparatus of clause A1, further comprising:

a storage module for storing the to-be-operated scalar,

Wherein, the storage module includes at least one of a register and a cache,

The cache is used to store the data to be calculated, and the cache includes at least one neuron cache NRAM;

the register for storing the to-be-operated scalar;

The neuron cache is used to store neuron data in the data to be operated, and the neuron data includes neuron vector data.

Clause A8. The apparatus of clause A1, the control module comprising:

an instruction storage submodule for storing the scalar type conversion instruction;

an instruction processing submodule, used for parsing the scalar type conversion instruction to obtain the operation code and operation domain of the scalar type conversion instruction;

The queue storage submodule is used to store an instruction queue, where the instruction queue includes a plurality of instructions to be executed sequentially arranged in an execution order, and the multiple instructions to be executed include the scalar type conversion instruction.

Clause A9. The apparatus according to Clause A8, the control module, further comprising:

The dependency relationship processing submodule is configured to, when it is determined that the first to-be-executed instruction in the plurality of to-be-executed instructions has an associated relationship with the zeroth to-be-executed instruction before the first to-be-executed instruction, to process the first to-be-executed instruction The execution instruction is cached in the instruction storage sub-module, and after the execution of the zeroth instruction to be executed is completed, the first instruction to be executed is extracted from the instruction storage sub-module and sent to the operation module,

Wherein, the relationship between the first instruction to be executed and the zeroth instruction to be executed before the first instruction to be executed includes:

The first storage address interval storing the data required by the first instruction to be executed and the zeroth storage address interval storing the data required by the zeroth instruction to be executed have an overlapping area.

Clause A10. A machine learning computing device, the device comprising:

One or more scalar type conversion instruction processing devices as described in any one of Clause A1 to Clause A9, used to obtain the scalar to be calculated and control information from other processing means, and execute the specified machine learning operation, and pass the execution result through. The I/O interface is passed to other processing devices;

When the machine learning computing device includes a plurality of the scalar type conversion instruction processing devices, the plurality of the scalar type conversion instruction processing devices can be connected through a specific structure and data can be transmitted;

Wherein, a plurality of the scalar type conversion instruction processing devices are interconnected and transmit data through the fast peripheral device interconnection bus PCIE bus to support larger-scale machine learning operations; a plurality of the scalar type conversion instruction processing devices share the same The control system may have its own control system; a plurality of the scalar type conversion instruction processing devices share memory or have their own memory; the interconnection mode of the plurality of scalar type conversion instruction processing devices is any interconnection topology.

Clause A11. A combined processing device, the combined processing device comprising:

Machine learning computing devices, general interconnection interfaces and other processing devices as described in Clause A10;

The machine learning computing device interacts with the other processing devices to jointly complete the computing operation specified by the user,

Wherein, the combined processing device further includes: a storage device, the storage device is respectively connected to the machine learning computing device and the other processing device, and is used for saving the data of the machine learning computing device and the other processing device.

Clause A12. A machine learning chip, the machine learning chip comprising:

The machine learning computing device as described in Item A10 or the combined processing device as described in Item A11.

Clause A13, an electronic device, the electronic device comprising:

A machine learning chip as described in Item A12.

Item A14. A board, the board comprising: a storage device, an interface device and a control device, and the machine learning chip as described in Item A12;

Wherein, the machine learning chip is connected to the storage device, the control device and the interface device respectively;

the storage device for storing data;

The interface device is used to realize data transmission between the machine learning chip and an external device;

The control device is used for monitoring the state of the machine learning chip.

Clause A15. A scalar type conversion instruction processing method, the method is applied to a scalar type conversion instruction processing apparatus, the apparatus includes a control module and an operation module, and the method includes:

Use the control module to parse the acquired scalar type conversion instruction, obtain the operation code and operation field of the scalar type conversion instruction, and obtain the scalar to be calculated and the operation field required to execute the scalar type conversion instruction according to the operation code and the operation field target address, and determine the target data type and the initial data type of the to-be-operated scalar;

The operation module is used to perform a scalar type conversion operation on the to-be-operated scalar of the initial data type according to the target data type, obtain an operation result, and store the operation result in the target address. The data type of the operation result is for the target data type,

The operation code is used to indicate that the operation performed by the scalar type conversion instruction on the data is a scalar type conversion operation, and the operation field includes the scalar address to be operated and the target address.

Item A16. The method according to Item A15, performing a scalar type conversion operation on the to-be-operated scalar of the initial data type according to the target data type, including:

The scalar type conversion operation is performed by using a plurality of scalar operators in the operation module.

Clause A17. The method according to Clause A16, wherein the operation module includes a master operation submodule and a plurality of slave operation submodules, the master operation submodule includes the plurality of scalar operators,

Wherein, performing a scalar type conversion operation on the to-be-operated scalar of the initial data type according to the target data type, obtaining an operation result, and storing the operation result in the target address, including:

The scalar type conversion operation is performed by using a plurality of scalar operators in the main operation submodule to obtain an operation result, and the operation result is stored in the target address.

Clause A18. The method according to Clause A15, wherein the operation domain further includes an initial data type and a target data type,

Wherein, determining the target data type and the initial data type of the to-be-operated scalar includes:

The target data type and the initial data type of the to-be-operated scalar are determined according to the operation domain.

Clause A19. The method of clause A15, wherein the opcode is further used to indicate an initial data type and a target data type,

Wherein, determining the target data type and the initial data type of the to-be-operated scalar includes:

The target data type and the initial data type of the to-be-operated scalar are determined according to the operation code.

Clause A20. The method according to Clause A15, wherein the target data type includes any one of 16-bit floating-point numbers, 32-bit floating-point numbers, 48-bit floating-point numbers, 16-bit integers, 32-bit integers, and 48-bit integers, so The initial data type includes any one of 16-bit signed number, 32-bit signed number, 48-bit signed number, 16-bit unsigned number, 32-bit unsigned number, 48-bit unsigned number and pointer data types.

Clause A21. The method according to Clause A16, the method further comprising:

Using the storage module of the device to store the to-be-operated scalar,

Wherein, the storage module includes at least one of a register and a cache,

The cache is used to store the data to be calculated, and the cache includes at least one neuron cache NRAM;

the register for storing the to-be-operated scalar;

The neuron cache is used to store neuron data in the data to be operated, and the neuron data includes neuron vector data.

Item A22. According to the method described in Item A15, parse the scalar type conversion instruction to obtain the operation code and operation domain of the scalar type conversion instruction, including:

storing the scalar type conversion instruction;

Analyzing the scalar type conversion instruction to obtain the operation code and operation domain of the scalar type conversion instruction;

An instruction queue is stored, where the instruction queue includes a plurality of instructions to be executed sequentially arranged in an execution order, and the multiple instructions to be executed include the scalar type conversion instruction.

Clause A23. The method according to Clause A22, the method further comprising:

When it is determined that the first to-be-executed instruction in the plurality of to-be-executed instructions has an associated relationship with the zeroth to-be-executed instruction before the first to-be-executed instruction, the first to-be-executed instruction is cached, and the first to-be-executed instruction is determined when the After the execution of the zeroth instruction to be executed is completed, the execution of the first instruction to be executed is controlled to be executed,

Wherein, the relationship between the first instruction to be executed and the zeroth instruction to be executed before the first instruction to be executed includes:

The first storage address interval storing the data required by the first instruction to be executed and the zeroth storage address interval storing the data required by the zeroth instruction to be executed have an overlapping area.

Clause A24. A non-transitory computer-readable storage medium having stored thereon computer program instructions that, when executed by a processor, implement the method of any one of clauses A15 to A23.

The embodiments of the present application have been introduced in detail above, and the principles and implementations of the present application are described in this paper by using specific examples. The descriptions of the above embodiments are only used to help understand the methods and core ideas of the present application; at the same time, for Persons of ordinary skill in the art, based on the idea of the present application, will have changes in the specific implementation manner and application scope. In summary, the contents of this specification should not be construed as limitations on the present application.

Claims (10)

1. An apparatus for processing scalar type conversion instructions, the apparatus comprising:

the control module is used for analyzing the obtained scalar type conversion instruction to obtain an operation code and an operation domain of the scalar type conversion instruction, obtaining a scalar to be operated and a target address which are required by executing the scalar type conversion instruction according to the operation code and the operation domain, and determining a target data type and an initial data type of the scalar to be operated;

the operation module is used for carrying out scalar type conversion operation on the scalar to be operated of the initial data type according to the target data type to obtain an operation result and storing the operation result into the target address, wherein the data type of the operation result is the target data type,

the operation code is used for indicating that the operation performed on data by the scalar type conversion instruction is a scalar type conversion operation, and the operation domain comprises a scalar address to be operated on and the target address.

2. The apparatus of claim 1, wherein the computing module comprises:

a plurality of scalar operators for performing the scalar type conversion operations.

3. The apparatus of claim 2, wherein the operation module comprises a master operation submodule and a plurality of slave operation submodule, the master operation submodule comprising the plurality of scalar operators,

and the main operation sub-module is used for executing the scalar type conversion operation by utilizing the scalar operators to obtain an operation result and storing the operation result into the target address.

4. A machine learning arithmetic device, the device comprising:

one or more scalar type conversion instruction processing devices according to any one of claims 1 to 3, for obtaining scalar to be operated and control information from other processing devices, executing a specified machine learning operation, and transmitting the execution result to other processing devices through an I/O interface;

when the machine learning operation device comprises a plurality of scalar type conversion instruction processing devices, the scalar type conversion instruction processing devices can be connected through a specific structure and transmit data;

the scalar type conversion instruction processing devices are interconnected through a Peripheral Component Interface Express (PCIE) bus and transmit data so as to support larger-scale machine learning operation; a plurality of scalar type conversion instruction processing devices share the same control system or own respective control systems; the scalar type conversion instruction processing devices share a memory or own respective memories; the interconnection mode of the scalar type conversion instruction processing devices is any interconnection topology.

5. A combined processing apparatus, characterized in that the combined processing apparatus comprises:

the machine learning computing device, the universal interconnect interface, and the other processing device of claim 4;

the machine learning arithmetic device interacts with the other processing devices to jointly complete the calculation operation designated by the user,

wherein the combination processing apparatus further comprises: and a storage device connected to the machine learning arithmetic device and the other processing device, respectively, for storing data of the machine learning arithmetic device and the other processing device.

6. A machine learning chip, the machine learning chip comprising:

the machine learning arithmetic device according to claim 4 or the combined processing device according to claim 5.

7. An electronic device, characterized in that the electronic device comprises:

the machine learning chip of claim 6.

8. The utility model provides a board card, its characterized in that, the board card includes: a memory device, an interface device and a control device and a machine learning chip according to claim 6;

wherein the machine learning chip is connected with the storage device, the control device and the interface device respectively;

the storage device is used for storing data;

the interface device is used for realizing data transmission between the machine learning chip and external equipment;

and the control device is used for monitoring the state of the machine learning chip.

9. A scalar type conversion instruction processing method is applied to a scalar type conversion instruction processing apparatus including a control module and an operation module, and includes:

analyzing the obtained scalar type conversion instruction by using a control module to obtain an operation code and an operation domain of the scalar type conversion instruction, obtaining a scalar to be operated and a target address required by executing the scalar type conversion instruction according to the operation code and the operation domain, and determining a target data type and an initial data type of the scalar to be operated;

performing scalar type conversion operation on the scalar to be operated of the initial data type by using an operation module according to the target data type to obtain an operation result, storing the operation result into the target address, wherein the data type of the operation result is the target data type,

the operation code is used for indicating that the operation performed on data by the scalar type conversion instruction is a scalar type conversion operation, and the operation domain comprises a scalar address to be operated on and the target address.

10. A non-transitory computer readable storage medium having computer program instructions stored thereon, wherein the computer program instructions, when executed by a processor, implement the method of claim 9.

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