CN111274162A - Dual inline memory module arrangement for storage level memory and method for accessing data - Google Patents

Abstract

The present invention relates to a dual in-line memory module DIMM device of a storage class memory SCM and a data access method. The device and the method for reading and writing data of the present invention can increase the memory space of the device, improve the speed performance of the device, reduce the design difficulty of the printed circuit board, and enable the host to access the non-volatile memory with low overhead.

Description

Dual in-line memory module device for storage class memory and data access method

technical field

The present invention relates to the field of memory. More particularly, the present invention relates to a dual in-line memory module DIMM (Dual In-line Memory Module) device of a storage class memory SCM (Storage Class Memory) and a data access method.

Background technique

The storage class memory SCM's dual in-line memory module DIMM is a new type of dual in-line memory module, and there is memory space on the module that can be accessed in the form of storage.

A schematic diagram of a signal flow and an interface in a dual in-line memory module DIMM of a known storage-class memory SCM existing in the prior art is shown in FIG. 1 . In FIG. 1, using the stub signal, the host or the central processing unit (CPU) can access the dynamic random access memory DRAM (Dynamic Random Access Memory) and the controller such as non-volatile memory during normal operation. Volatile controller NVC (Non-Volatile Controller), and the purpose of accessing non-volatile memory such as NAND Flash is achieved through the access controller, thereby increasing the memory space of the system.

The bifurcation signal is embodied in the following aspects: after the command/address CA (Command/Address) signal is output from the DIMM slot (slot), there is a bifurcation (stub) signal, and the bifurcated signal is respectively connected to the register clock driver RCD (Register Clock Driver). Driver) and controller; the data DQ signal also has a bifurcation signal between the data buffer DB (Data Buffer) and the dynamic random access memory DRAM. This kind of bifurcation signal is very difficult to realize high-speed signal on the printed circuit board, because the feedback of the high-speed signal will interfere with the signal of the other channel and affect the rate performance.

Another known technical solution for removing bifurcated signals existing in the prior art is shown in FIG. 2 . In FIG. 2 , both the command/address CA signal and the data DQ signal enter the controller first, omitting the bifurcation signal shown in FIG. 1 . However, there are two problems in the situation shown in Figure 2:

First, the data DQ signal is enhanced with the driving capability through the data buffer DB, but after entering the controller, it is difficult to maintain and transmit the enhanced driving signal to a non-volatile memory such as NAND Flash in the chip.

Secondly, the high-speed data DQ signal is on both sides of the DIMM slot, so that it is difficult to realize the same length of connection between the high-speed data DQ signal and the controller when wiring on the printed circuit board. However, the unequal lengths of high-speed parallel signals cause the signals to arrive at the destination at different times, which will also result in degraded rate performance.

Therefore, there is an urgent need for a dual in-line memory module DIMM device and a data access method for the storage class memory SCM capable of solving the above problems.

SUMMARY OF THE INVENTION

The present invention relates to a dual in-line memory module DIMM capable of increasing the memory space of a device, improving the speed performance of the device, reducing the difficulty of printed circuit board design, and enabling a host to access a non-volatile memory storage-class memory SCM with low overhead Device and method of accessing data.

According to a first aspect of the present invention, there is provided a dual in-line memory module device for storage-level memory, comprising:

a first storage area that stores data having a first range of host access frequencies; and

a second storage area, the second storage area stores data having a second range of host access frequencies;

Wherein, the access frequency of hosts in the first range is greater than the access frequency of hosts in the second range.

Thus, the storage area of the dual in-line storage module device is divided into a "hot area" (ie, the first storage area) that is frequently read and written by the host or the central processing unit and a "hot area" that is not frequently read and written by the host or the central processing unit. The "cold zone" (ie, the second storage zone), the "hot zone" has a relatively fast processing speed, and the "cold zone" has a relatively slow processing speed. In this way, the rate performance of the module device can be improved.

According to a preferred embodiment of the storage class memory dual inline memory module device of the present invention, the data having the second range of host access frequencies is indirectly stored in the second storage area via the first storage area. in the storage area.

Thus, the present invention clarifies the method of accessing the "cold area" (ie, the second storage area), that is, the "cold area" needs to be accessed via the "hot area" (ie, the first storage area), by accessing the "cold area" area" to increase the memory space of the device.

According to a preferred embodiment of the dual in-line memory module device of the storage class memory of the present invention, the first storage area includes a storage space of a predetermined size for data having a second range of host access frequencies.

Preferably, the sizes of these storage spaces are each greater than 64KB. Factors that need to be considered when sizing these storage spaces are the data rate at which the host accesses DRAM, the data rate at which the controller accesses DRAM, and the controller accesses non-volatile memory such as NAND Flash. data rate, etc.

According to a preferred embodiment of the dual in-line memory module device of the storage-class memory of the present invention, the second storage area includes a plurality of sub-storage areas, each of the plurality of sub-storage areas stores data having different ranges of host access frequencies. data.

According to a preferred embodiment of the dual in-line memory module device of the storage-level memory of the present invention, the second storage area includes two sub-storage areas, and the two sub-storage areas are:

a first sub-storage area, the first sub-storage area stores data with a first sub-range of host access frequencies;

a second sub-storage area, the second sub-storage area stores data with a second sub-range of host access frequencies;

Wherein, the access frequency of hosts in the first sub-range is greater than the access frequency of hosts in the second sub-range.

According to a preferred embodiment of the dual in-line memory module device of the storage class memory of the present invention, the first storage area is a plurality of dynamic random access memories.

Since the processing speed of the dynamic random access memory is relatively fast, by storing the data frequently read and written by the host or the central processing unit in the dynamic random access memory, the rate performance of the module device can be improved.

According to a preferred embodiment of the dual in-line memory module device of the storage class memory of the present invention, the first sub-storage area is a dynamic random access memory cache module; and the second sub-storage area is a non-volatile memory area Sexual memory.

As a result, data in the "cold data" with a relatively high host access frequency is written to the DRAM cache module, and data in the "cold data" with a relatively low host access frequency is written to the non- in volatile memory. In this way, the speed performance of the device is further improved, and frequent access to the non-volatile memory is avoided, thereby avoiding damage to the non-volatile memory.

A preferred embodiment of the dual in-line memory module device for storage-level memory according to the present invention further comprises:

and a controller, which is respectively connected with the dynamic random access memory cache module and the non-volatile memory.

The dual in-line memory module device for storage-level memory according to the present invention further comprises:

a clock driver, connected with the controller.

According to a preferred embodiment of the storage class memory dual inline memory module device of the present invention, in response to a host writing data having a second range of host access frequencies into the plurality of dynamic random access memories one or more, and in response to the controller receiving the address of the data with the host access frequency of the second range notified by the host via the system management bus, the controller sends a get data command to the plurality of data buffers one or more of the plurality of data buffers to command one or more of the plurality of data buffers to obtain the host access frequency having the second range from one or more of the plurality of dynamic random access memories and sending the data having the second range of host access frequencies to the controller; and,

In response to receiving the data having the second range of host access frequencies, the controller writes the data having the second range of host access frequencies to the DRAM cache module or the non-volatile memory cache module. in volatile memory.

Thereby, the host can access the controller during normal operation, and by writing data having the second range of host access frequency into the controller, the memory space of the device is increased. In addition, writing data that is not frequently accessed by the host (ie, cold data) into the DRAM cache module or the non-volatile memory can improve the rate performance of the device.

According to a preferred embodiment of the storage-level memory dual-in-line memory module device of the present invention, the clock driver is connected to the controller via a local command bus; the clock driver is connected to the controller via a data buffer command bus each of a plurality of data buffers is connected; and each of the plurality of data buffers is connected to the controller via a local data bus.

According to a preferred embodiment of the storage class memory dual inline memory module device of the present invention, the controller sends the get data command to the fetch data command via the local command bus and the data buffer command bus One or more of multiple data buffers.

According to a preferred embodiment of the storage class memory dual inline memory module device of the present invention, one or more of the plurality of data buffers connect the host having the second range to the host via the local data bus The data of the access frequency is sent to the controller.

Thus, the difficulty of designing the printed circuit board of the device is reduced. At the same time, the cache is used to balance the speed difference between the non-volatile memory and the memory, so that the host can stably access the non-volatile memory with low overhead.

According to a preferred embodiment of the storage class memory dual inline memory module device of the present invention, the controller writes data having the host access frequency of the first sub-range to the dynamic random access memory in the cache module; and the controller writes data having the host access frequency of the second sub-range into the non-volatile memory.

According to a preferred embodiment of the storage class memory dual in-line memory module device of the present invention, the host directly writes data to the plurality of dynamic data buffers via one or more of the plurality of data buffers one or more of random access memories.

Therefore, it is possible to prevent the host computer and the controller from connecting high-speed signals at the same time, so as not to cause difficulties in the design of the printed circuit board.

According to a preferred embodiment of the storage class memory dual inline memory module device of the present invention, in response to receiving the address of the data with the host access frequency of the second range notified by the host via the system management bus, the control A processor reads the data having the host access frequency of the second range from the DRAM cache module or the non-volatile memory and sends a write data command to the data buffers in the plurality of data buffers. one or more to command one or more of the plurality of data buffers to obtain data from the controller with the host access frequency of the second range and then access the host with the second range frequency data is written into one or more of the plurality of dynamic random access memories; and,

The host reads data from one or more of the plurality of dynamic random access memories.

According to a preferred embodiment of the storage-level memory dual-in-line memory module device of the present invention, the clock driver is connected to the controller via a local command bus; the clock driver is connected to the controller via a data buffer command bus each of a plurality of data buffers is connected; and each of the plurality of data buffers is connected to the controller via a local data bus.

According to a preferred embodiment of the storage class memory dual inline memory module device of the present invention, the controller sends a write data command to the multiplexer via the local command bus and the data buffer command bus one or more of the data buffers.

According to a preferred embodiment of the storage class memory dual in-line memory module device of the present invention, one or more of the plurality of data buffers are obtained from the controller via the local data bus Data with a first range of host access frequencies.

Thus, the difficulty of designing the printed circuit board of the device is reduced. At the same time, the cache is used to balance the speed difference between the non-volatile memory and the memory, so that the host can stably access the non-volatile memory with low overhead.

According to a preferred embodiment of the dual inline memory module device of the storage class memory of the present invention, the controller reads the host access frequency having the first sub-range from the dynamic random access memory cache module and the controller reads the data of the host access frequency having the second sub-range from the non-volatile memory.

According to a preferred embodiment of the storage class memory dual inline memory module device of the present invention, the host directly accesses the plurality of DRAMs via one or more of the plurality of data buffers One or more of the read data.

Therefore, it is possible to prevent the host computer and the controller from connecting high-speed signals at the same time, so as not to cause difficulties in the design of the printed circuit board.

According to a preferred embodiment of the dual in-line memory module device of the storage class memory of the present invention, the wiring of the printed circuit board between the plurality of dynamic random access memories and the plurality of data buffers is of equal length of.

As a result, the arrival time of the signal at the destination will not be different, and the rate performance is further improved.

According to a second aspect of the present invention, there is provided a data access method for a dual in-line memory module device for storage class memory, the dual in-line memory module device including a first storage area and a second storage area Area;

The method for accessing data includes:

storing data having a first range of host access frequencies in the first storage area; and

storing data with a second range of host access frequencies in the second storage area;

Wherein, the access frequency of hosts in the first range is greater than the access frequency of hosts in the second range.

According to a preferred embodiment of the method for accessing data of the present invention, the method for accessing data further comprises:

The data having the second range of host access frequencies is indirectly stored in the second storage area via the first storage area.

According to a preferred embodiment of the method for accessing data of the present invention, the first storage area includes a storage space of a predetermined size for data having a host access frequency of a second range.

According to a preferred embodiment of the data access method of the present invention, the second storage area includes a plurality of sub-storage areas;

The method for accessing data further includes:

Data having different ranges of host access frequencies are each stored in the plurality of sub-storage areas.

According to a preferred embodiment of the data access method of the present invention, the second storage area includes two sub-storage areas, and the two sub-storage areas are a first sub-storage area and a second storage area;

The method for accessing data further includes:

storing data with a first sub-range of host access frequencies in the first sub-storage area; and

storing data with a second sub-range of host access frequencies in the second sub-storage area;

Wherein, the access frequency of hosts in the first sub-range is greater than the access frequency of hosts in the second sub-range.

According to a preferred embodiment of the data access method of the present invention, the first storage area is a plurality of dynamic random access memories.

According to a preferred embodiment of the data access method of the present invention, the first sub-storage area is a dynamic random access memory cache module; and the second sub-storage area is a non-volatile memory.

According to a preferred embodiment of the data access method of the present invention, the dual in-line storage module device further includes a controller;

The method for accessing data further includes:

The controller is connected to the dynamic random access memory cache module and the non-volatile memory, respectively.

According to a preferred embodiment of the data access method of the present invention, the dual in-line memory module device further includes a clock driver;

The method for accessing data further includes:

Connect the clock driver to the controller.

According to a preferred embodiment of the method for accessing data of the present invention, the method for accessing data further comprises:

in response to the host writing data having a second range of host access frequencies to one or more of the plurality of dynamic random access memories, and in response to the controller receiving a notification from the host via the system management bus an address of data having a second range of host access frequencies, the controller sending a get data command to one or more of the plurality of data buffers to command one or more of the plurality of data buffers obtaining the data having the second range of host access frequencies from one or more of the dynamic random access memories and sending the data having the second range of host access frequencies to the controller; and

In response to receiving the data having the second range of host access frequencies, the controller writes the data having the second range of host access frequencies to the DRAM cache module or the non-volatile memory cache module. in volatile memory.

According to a preferred embodiment of the method for accessing data of the present invention, the method for accessing data further comprises:

the clock driver is connected to the controller via a local command bus;

the clock driver is connected to each of the plurality of data buffers via a data buffer command bus; and

The plurality of data buffers are each connected to the controller via a local data bus.

According to a preferred embodiment of the method for accessing data of the present invention, the method for accessing data further comprises:

The controller sends the get data command to one or more of the plurality of data buffers via the local command bus and the data buffer command bus.

According to a preferred embodiment of the method for accessing data of the present invention, the method for accessing data further comprises:

One or more of the plurality of data buffers transmit the data having the second range of host access frequencies to the controller via the local data bus.

According to a preferred embodiment of the method for accessing data of the present invention, the method for accessing data further comprises:

the controller writes data having the first sub-range of host access frequencies into the DRAM cache module; and

The controller writes data having the host access frequency of the second sub-range into the non-volatile memory.

According to a preferred embodiment of the method for accessing data of the present invention, the method for accessing data further comprises:

The host directly writes data to one or more of the plurality of dynamic random access memories via one or more of the plurality of data buffers.

According to a preferred embodiment of the method for accessing data of the present invention, the method for accessing data further comprises:

The controller reads from the dynamic random access memory cache module or the non-volatile memory in response to receiving an address of data having a second range of host access frequencies notified by the host via the system management bus The host accesses data with the second range of frequencies and sends a write data command to one or more of the plurality of data buffers to command one or more of the plurality of data buffers to the controller obtains the data having the second range of host access frequencies and then writes the data having the second range of host access frequencies into one or more of the plurality of dynamic random access memories; as well as

The host reads data from one or more of the plurality of dynamic random access memories.

According to a preferred embodiment of the method for accessing data of the present invention, the method for accessing data further comprises:

the clock driver is connected to the controller via a local command bus;

the clock driver is connected to each of the plurality of data buffers via a data buffer command bus; and

The plurality of data buffers are each connected to the controller via a local data bus.

According to a preferred embodiment of the method for accessing data of the present invention, the method for accessing data further comprises:

The controller sends a write data command to one or more of the plurality of data buffers via the local command bus and the data buffer command bus.

According to a preferred embodiment of the method for accessing data of the present invention, the method for accessing data further comprises:

One or more of the plurality of data buffers obtain the data having the first range of host access frequencies from the controller via the local data bus.

According to a preferred embodiment of the method for accessing data of the present invention, the method for accessing data further comprises:

the controller reads the data having the host access frequency of the first sub-range from the DRAM cache module; and

The controller reads the data having the host access frequency of the second sub-range from the non-volatile memory.

According to a preferred embodiment of the method for accessing data of the present invention, the method for accessing data further comprises:

The host directly reads data from one or more of the plurality of dynamic random access memories via one or more of the plurality of data buffers.

According to a preferred embodiment of the method for accessing data of the present invention, the method for accessing data further comprises:

The wirings of the printed circuit board between the plurality of dynamic random access memories and the plurality of data buffers are arranged to be of equal length.

It should be understood by those skilled in the art that the technical effects as recited in relation to the first aspect of the present invention can be achieved according to the second aspect of the present invention.

Description of drawings

The present invention will be more readily understood from the following description in conjunction with the accompanying drawings, in which:

FIG. 1 is a schematic diagram of a signal flow and an interface in a dual in-line memory module DIMM of a storage class memory SCM in the prior art.

FIG. 2 is a schematic diagram of signal flow and interfaces in a dual in-line memory module DIMM, another storage class memory SCM in the prior art.

3 is a configuration in a dual in-line memory module DIMM of a storage class memory SCM according to one embodiment of the present invention.

Detailed ways

The embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

3 is a configuration in a dual in-line memory module DIMM of a storage class memory SCM according to one embodiment of the present invention.

In the configuration of FIG. 3, the host can access the dynamic random access memory DRAM 301 and the controller 304 during normal operation, and access the non-volatile memory such as NAND Flash 302 through the access controller 304, thereby increasing the system memory space.

Compared to FIG. 2, in the configuration of FIG. 3, the clock driver RCD 305 and the data buffer DB 306 are used to improve the driving capability of the data DQ signal and the command/address CA signal, respectively. In addition, the host directly writes data into the dynamic random access memory DRAM 301 via the data buffer DB 306, so as to prevent the host and the controller 304 from connecting high-speed signals at the same time, and will not bring difficulties to the design of the printed circuit board. In addition, the wiring of the printed circuit board between the data buffer DB 306 and the dynamic random access memory DRAM 301 is also of the same length, which will not cause the signals to arrive at the destination at different times, thereby further improving the rate performance.

In addition, when the host needs to access non-volatile memory such as NAND Flash 302, it notifies the controller 304 via the system management bus SMBus that it wants to access the address segment of the non-volatile memory such as NAND Flash 302; A portion of the dynamic random access memory DRAM 301 is used as a buffer to enable host access to non-volatile memory such as NAND Flash 302 .

Therefore, the design difficulty of the system printed circuit board is reduced, and the speed difference between the non-volatile memory and the memory is balanced by the cache, so that the host can stably access the non-volatile memory with low overhead.

The configuration of FIG. 3 is described in further detail below.

As shown in FIG. 3, the dual in-line memory module DIMM of the storage class memory SCM includes a plurality of dynamic random access memory DRAM 301, non-volatile memory such as NAND Flash 302, and dynamic random access memory DRAM cache (Cache) ) module 303.

In the present invention, "hot data" is finally stored in the dynamic random access memory DRAM 301, while "cold data" is stored in the non-volatile memory such as NAND Flash 302 and the dynamic random access memory DRAM cache module 303, and dynamic Random access memory DRAM cache module 303 stores data with relatively high host access frequency in "cold data", and non-volatile memory such as NAND Flash 302 stores "cold data" with relatively low host access frequency frequency data.

In the present invention, "hot data" refers to data frequently accessed by a host or central processing unit, and "cold data" refers to data that is not frequently accessed by a host or central processing unit.

In the definition of "hot data" and "cold data", frequent access is defined according to specific situations, and there is no specific value to define.

The configuration as described in the present invention can improve the speed performance of the device and avoid frequent access to the non-volatile memory, thereby avoiding damage to the non-volatile memory.

As further shown in FIG. 3 , the dual in-line memory module DIMM of the storage class memory SCM includes a controller 304 , a clock driver RCD 305 and a plurality of data buffers DB 306 . The clock driver RCD 305 is connected to the controller 304 via a local command bus LCOM, the clock driver RCD 305 is connected to each of the plurality of data buffers DB 306 via a data buffer command bus BCOM, the The data buffers DB 306 are each connected to the controller 304 via a local data bus LDQ.

The structure in FIG. 3 is further understood below in conjunction with the process of writing and reading data from the host to the controller 304 or the dynamic random access memory DRAM cache module 303 .

When the host writes data to non-volatile memory such as NAND Flash 302 or DRAM cache module 303 , the host first writes the data to one or more of the plurality of dynamic random access memory DRAMs 301 . In the method of the present invention, this "data" refers to "cold data" since this "data" will eventually be written to a non-volatile memory such as NANDFlash 302 or a dynamic random access memory DRAM cache module 303 .

It should be understood that the host can write hot and cold data into the dynamic random access memory DRAM 301, the hot data is ultimately stored in the dynamic random access memory DRAM 301, and the cold data is finally stored in a non-volatile memory such as NAND Flash 302 or dynamic random access memory DRAM cache module 303 . In the present invention, in each of the plurality of dynamic random access memory DRAMs 301, there is a buffer area reserved for caching cold data with a fixed space size.

Preferably, the space sizes of these buffer areas are each greater than 64KB. Factors such as the data rate at which the host accesses the dynamic random access memory DRAM, the data rate at which the controller 304 accesses the dynamic random access memory DRAM, and the controller 304 accesses to the non-volatile memory, need to be considered when opening up the size of these buffer areas. Such as the data rate of NAND Flash 302, etc.

After the host writes the cold data into one or more of the plurality of dynamic random access memory DRAMs 301 , the controller 304 retrieves the "cold data" from one or more of the plurality of dynamic random access memory DRAMs 301 And these "cold data" are written into non-volatile memory such as NAND Flash 302 and dynamic random access memory DRAM cache module 303 according to the cache algorithm.

In the present invention, the host can directly write data into one or more of the plurality of dynamic random access memories 301 via one or more of the plurality of data buffers DB 306, when the host has a plurality of dynamic random access memories 301 Operation control of the random access memory DRAM 301 .

The host then informs the controller 304 via the system management bus SMBus of the address of the data with the second range of host access frequencies (ie, "cold data" that the host does not frequently access), which controller 304 sends the dynamic random access memory DRAM The operation control of 301 is switched from the host. Then, the controller 304 communicates between the clock driver RCD 305 and each of the plurality of data buffers DB 306 via the local command bus LCOM between the clock driver RCD 305 and the controller 304 sending the get data command to one or more of the plurality of data buffer DBs 306 to command one or more of the plurality of data buffer DBs 306 Each obtains the "cold data" from one or more of the plurality of dynamic random access memory DRAMs 301 and sends the "cold data" to the controller 304 via the local data bus LDQ. Finally, the controller 304 writes the "cold data" into the dynamic random access memory DRAM cache module 303 or the non-volatile memory such as NAND Flash 302 according to a cache algorithm.

The general idea of the caching algorithm is: write data with a first sub-range of host access frequency (ie, a relatively high host access frequency) in the "cold data" into the DRAM cache module 303; and , data in the "cold data" having a host access frequency of the second sub-range (ie, a relatively low host access frequency) is written into the non-volatile memory 302 .

When the host reads data from a non-volatile memory such as NAND Flash 302 or a dynamic random access memory DRAM cache module 303, the host first notifies the controller 304 of the address of the "cold data", and the controller 304 reads the data from the address according to the address. Read "cold data" from non-volatile memory such as NAND Flash 302 and DRAM cache module 303 and write these "cold data" to one or more of the plurality of dynamic random access memory DRAMs 301 . Of these, the host then reads "cold data" from one or more of the plurality of dynamic random access memory DRAMs 301 .

Specifically, the host first notifies the controller 304 via the system management bus SMBus of the address of the data (ie, "cold data") with a first range of host access frequencies, according to which the controller 304 switches from the non-volatile "Cold data" is read in memory such as NAND Flash 302 and DRAM cache module 303 and via the local command bus LCOM between the clock driver RCD 305 and the controller 304 and the clock The data buffer command bus BCOM between the driver RCD 305 and one or more of the plurality of data buffers DB 306 sends the write data command to the plurality of data buffers DB 306 In one or more, to command one or more of the plurality of data buffers DB 306 to obtain the "cold data" from the controller 304 via the local data bus LDQ and then to store the "cold data" Data" is written into one or more of the plurality of dynamic random access memory DRAMs 301 . Finally, the host reads data from one or more of the plurality of dynamic random access memory DRAMs 301 .

In addition, the dual in-line memory module DIMM of the storage class memory SCM shown in FIG. 3 is a typical NVDIMM-N type. A typical SAVE_n signal between the host and the dual in-line memory module DIMM of the storage class memory SCM is shown in FIG. 3 . The SAVE_n signal is used to be pulled low by the host when the system is powered down abnormally to notify the dual in-line storage module NVDIMM to perform data backup.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. It should be understood that the scope of the present invention is defined by the claims.

Claims (10)

1. A dual in-line memory module apparatus of a storage class memory, comprising:

a first storage area storing data having a first range of host access frequencies; and

a second storage area storing data having a second range of host access frequencies;

wherein the first range of host access frequencies is greater than the second range of host access frequencies.

2. The dual in-line memory module arrangement of storage level memory according to claim 1,

the data having a second range of host access frequencies is stored in the second storage area indirectly via the first storage area.

3. The dual in-line memory module arrangement of storage level memory according to claim 2,

the first storage area includes a predetermined size of storage space for data having a second range of host access frequencies.

4. The dual in-line memory module arrangement of storage level memories according to any of claims 1-3,

the second storage area includes a plurality of sub-storage areas each storing data having a different range of host access frequencies.

5. The dual in-line memory module arrangement of storage level memory according to claim 4,

the second memory area comprises two sub memory areas, wherein the two sub memory areas are as follows:

a first sub-storage area storing data having a first sub-range host access frequency;

a second sub-storage area storing data having a second sub-range host access frequency;

wherein the first sub-range host access frequency is greater than the second sub-range host access frequency.

6. A method of accessing data for a dual in-line memory module arrangement for storage class memory, characterized in that the dual in-line memory module arrangement comprises a first memory area and a second memory area;

the data access method comprises the following steps:

storing data having a first range of host access frequencies in a first storage area; and

storing data having a second range of host access frequencies in a second storage area;

wherein the first range of host access frequencies is greater than the second range of host access frequencies.

7. The method of accessing data of claim 6,

the method for accessing data further comprises the following steps:

storing the data having the second range of host access frequencies in the second storage area indirectly via the first storage area.

8. The method of accessing data of claim 7,

the first storage area includes a predetermined size of storage space for data having a second range of host access frequencies.

9. Method for accessing data according to any of claims 6-8, characterised in that the second memory area comprises a plurality of sub memory areas;

the method for accessing data further comprises the following steps:

storing data having different ranges of host access frequencies in the plurality of sub-storage areas, respectively.

10. The method for accessing data according to claim 9, wherein the second storage area includes two sub-storage areas, the two sub-storage areas being a first sub-storage area and a second storage area;

the method for accessing data further comprises the following steps:

storing data having a first sub-range host access frequency in the first sub-storage area; and

storing data having a second sub-range host access frequency in the second sub-storage area;

wherein the first sub-range host access frequency is greater than the second sub-range host access frequency.

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