CN111257838A - Multichannel signal preprocessing method based on broadband receiver - Google Patents

Abstract

The invention belongs to the field of radar signal processing, and in particular relates to a multi-channel signal preprocessing method based on a wideband receiver, which satisfies the sampling processing of large bandwidth signals and can also complete radar signal preprocessing, thereby improving the anti-jamming performance of the system.

Description

A Multi-Channel Signal Preprocessing Method Based on Wideband Receiver

technical field

The invention belongs to the field of radar signal processing, in particular to a multi-channel signal preprocessing method based on a wideband receiver.

Background technique

With the development of radar technology and modern broadband communication technology, the system has higher and higher requirements for the analog input bandwidth, and then requires a higher sampling rate analog-to-digital converter (ADC) to meet this demand, but the high-speed analog-to-digital conversion The large bandwidth signal obtained by the ADC (ADC) requires the subsequent processor to have extremely high processing capabilities, which consumes a lot of resources, especially multi-channel parallel processing is difficult to achieve. The built-in digital down-conversion module (DDC) digitally down-converts the original signal to reduce the data rate, and the obtained data can be easily processed by a field programmable gate array (FPGA).

In addition, since the radar works in an increasingly harsh electromagnetic interference environment, the receiver will preprocess the digital signal to improve the anti-interference performance of the system and further reduce the burden of the signal processor. Therefore, an efficient broadband digital receiver is developed. It is of great significance to complete the digital transformation of the broadband communication receiving system, improve the performance of the radar, telemetry and other communication receiving systems, and realize the final software radio receiving system.

SUMMARY OF THE INVENTION

In order to solve the above problems existing in the prior art, the present invention provides a multi-channel signal preprocessing method based on a wideband receiver. The technical problem to be solved by the present invention is realized by the following technical solutions:

A multi-channel signal preprocessing method based on a wideband receiver, comprising:

其中f_H＝f₀+B/2，f_L＝f₀-B/2，f_h称为上限频率，f_l称为下限频率；由此我们可以确定采样频率f_s；由于需要利用模数转换器ADC的内置数字下变频模块，所以还需要确定抽取倍数及滤波器带宽，参数确定后，便可以将模数转换器ADC配置在相应的模式下进行工作；First determine the intermediate frequency f ₀ and modulation bandwidth B of the echo signal, and then obtain the sampling frequency f _s of the ADC, which must satisfy:

Where f _H = f ₀ +B/2, f _L =f ₀ -B/2, f _h is called the upper limit frequency, and f _l is called the lower limit frequency; thus we can determine the sampling frequency f _s ; The built-in digital down-conversion module of the converter ADC, so it is necessary to determine the decimation multiple and filter bandwidth. After the parameters are determined, the analog-to-digital converter ADC can be configured to work in the corresponding mode;

The multi-chip analog-to-digital converter ADC works under the same parameters, and the data frame encoded by the multi-chip multi-channel analog-to-digital converter ADC is sent to the field programmable gate array FPGA for de-frame processing; After the frame, the data after the first-level digital down-conversion can be obtained;

After the above processing, the data has been mixed to near zero frequency, and the data rate is greatly reduced after two-stage half-band filtering, which is suitable for field programmable gate array FPGA for signal preprocessing. This step will affect the data of one of the channels. Perform spectrum analysis, complete the fast Fourier transform FFT operation by the field programmable gate array FPGA, and the obtained FFT calculation result will be sent to the signal processor by the optical fiber, and the signal processor will further find the frequency point with the least interference. The intermediate frequency value that can be used for the next mixing, so as to achieve frequency agility, and can guide the radar operating frequency to the gap or weak area of the interference spectrum;

The radar works in the frequency conversion mode, and needs to complete the second-stage digital down-conversion DDC, mix the signal to the baseband, and further complete the extraction of larger multiples; the center frequency of the mixing coefficient is analyzed from the mode word received by the fiber ; According to the frequency point value, the DDS_IP core is used in the field programmable gate array FPGA to generate the mixing coefficients, and the multiplication is completed with the input data; the m mixing coefficients Δθ corresponding to the previous step are stored in the ROM, and the mode word is analyzed by analyzing the mode word. Complete the frequency point selection; use the FIR_IP core in the field programmable gate array FPGA to complete the filter extraction, the coefficients of the filter can be generated by the FDA tool of MATLAB, and the generated coefficients are also stored in the rom, and the coefficients will be automatically read when the system starts. In FIR_IP, complete the operation;

The external strong and narrow pulses appear as a few larger values after the digital down-conversion DDC. With the difference in the width and intensity of the narrow pulses, the number of expansion points after the digital down-conversion DDC is different, which will lead to the formation of a pulse pressure after the DDC. Steps, false alarms occur; therefore, narrow pulse rejection needs to be performed after the completion of the digital down-conversion DDC;

The various preprocessing results are sent to the signal processor through the optical fiber, and the optical fiber also accepts the mode word sent by the signal processor, and analyzes the working parameters of each part of the receiver.

Description of drawings

1 is a schematic flowchart of a multi-channel signal preprocessing method based on a wideband receiver provided by an embodiment of the present invention;

2 is a structural block diagram of a built-in DDC of a high-speed analog-to-digital converter based on a multi-channel signal preprocessing method of a wideband receiver provided by an embodiment of the present invention;

3 is an internal DDC implementation structure of a field programmable gate array based on a multi-channel signal preprocessing method for a wideband receiver provided by an embodiment of the present invention;

4 is a schematic diagram of a narrowband signal filter based on a multi-channel signal preprocessing method for a wideband receiver provided by an embodiment of the present invention;

5 is an implementation structure of narrow pulse elimination based on a multi-channel signal preprocessing method for a wideband receiver provided by an embodiment of the present invention;

FIG. 6 is a structural diagram of an implementation of anti-asynchronous interference based on a multi-channel signal preprocessing method based on a wideband receiver provided by an embodiment of the present invention.

Detailed ways

The present invention will be described in further detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

Please refer to FIG. 1. FIG. 1 is a schematic flowchart of a multi-channel signal preprocessing method based on a wideband receiver provided by an embodiment of the present invention, including:

其中f_H＝f₀+B/2，f_L＝f₀-B/2，f_h称为上限频率，f_l称为下限频率；由此我们可以确定采样频率f_s；由于需要利用模数转换器ADC的内置数字下变频模块，所以还需要确定抽取倍数及滤波器带宽，参数确定后，便可以将模数转换器ADC配置在相应的模式下进行工作；First determine the intermediate frequency f ₀ and modulation bandwidth B of the echo signal, and then obtain the sampling frequency f _s of the ADC, which must satisfy:

Where f _H = f ₀ +B/2, f _L = f ₀ -B/2, f _h is called the upper limit frequency, and f _l is called the lower limit frequency; thus we can determine the sampling frequency f _s ; The built-in digital down-conversion module of the converter ADC, so it is necessary to determine the decimation multiple and filter bandwidth. After the parameters are determined, the analog-to-digital converter ADC can be configured to work in the corresponding mode;

The multi-chip analog-to-digital converter ADC works under the same parameters, and the data frame encoded by the multi-chip multi-channel analog-to-digital converter ADC is sent to the field programmable gate array FPGA for de-frame processing; After the frame, the data after the first-level digital down-conversion can be obtained;

After the above processing, the data has been mixed to near zero frequency, and the data rate is greatly reduced after two-stage half-band filtering, which is suitable for field programmable gate array FPGA for signal preprocessing. This step will affect the data of one of the channels. Perform spectrum analysis, complete the fast Fourier transform FFT operation by the field programmable gate array FPGA, and the obtained FFT calculation result will be sent to the signal processor by the optical fiber, and the signal processor will further find the frequency point with the least interference. The intermediate frequency value that can be used for the next mixing, so as to achieve frequency agility, and can guide the radar operating frequency to the gap or weak area of the interference spectrum;

The radar works in the frequency conversion mode, and needs to complete the second-stage digital down-conversion DDC, mix the signal to the baseband, and further complete the extraction of larger multiples; the center frequency of the mixing coefficient is analyzed from the mode word received by the fiber ; According to the frequency point value, the DDS_IP core is used in the field programmable gate array FPGA to generate the mixing coefficients, and the multiplication is completed with the input data; the m mixing coefficients Δθ corresponding to the previous step are stored in the ROM, and the mode word is analyzed by analyzing the mode word. Complete the frequency point selection; use the FIR_IP core in the field programmable gate array FPGA to complete the filter extraction, the coefficients of the filter can be generated by the FDA tool of MATLAB, and the generated coefficients are also stored in the rom, and the coefficients will be automatically read when the system starts. In FIR_IP, complete the operation;

The external strong and narrow pulses appear as a few larger values after the digital down-conversion DDC. With the difference in the width and intensity of the narrow pulses, the number of expansion points after the digital down-conversion DDC is different, which will lead to the formation of a pulse pressure after the DDC. Steps, false alarms occur; therefore, narrow pulse rejection needs to be performed after the completion of the digital down-conversion DDC;

Realization algorithm: Take PT protection units on the left and right of the judgment point, and then take several points to average, and use relative threshold and absolute threshold to judge. If both are satisfied, remove the point by setting zero, otherwise keep it. Among them, the function of the relative threshold is to judge whether the point is a narrow pulse point, and its high position controls the opening and disabling of the module; the function of the absolute threshold is to avoid eliminating noise and signals.

The various preprocessing results are sent to the signal processor through the optical fiber, and the optical fiber also accepts the mode word sent by the signal processor, and analyzes the working parameters of each part of the receiver.

The present invention is an overall implementation block diagram of a multi-channel signal preprocessing system and method based on a wideband receiver. The processing flow of the system:

Due to the use of high sampling rate f _s around 1GHz for data acquisition, high data rates are difficult to handle directly within a field programmable gate array FPGA. Therefore, it is necessary to preprocess the data before entering the field programmable gate array FPGA to reduce the data rate. That is, the entire design is divided into two steps to complete the digital down-conversion of the signal.

First, in the ADC, the built-in digital down-conversion DDC module is used to complete data filtering and decimation based on the full frequency band, and its filter coefficients are all fixed.

If only 1-stage half-band filter is used to complete decimation by 2, it is verified by simulation that spectral aliasing will not occur. At this time, the data rate is reduced to f _s /2, which is 500MHz. Although this data rate can be processed in the field programmable gate array FPGA, it is still relatively high, and it will increase the resources and power consumption in the subsequent processing of the field programmable gate array FPGA. .

If a 2-stage half-band filter is used, decimation by a factor of 4 is completed, and it is verified that no spectral aliasing occurs. At this time, the data rate is reduced to about 250MHz, which is suitable for FPGA processing.

内的信号不混叠。The digital down-conversion is further completed in the field programmable gate array FPGA to achieve more accurate mixing, and the data needs to be extracted to smaller multiples. In the ADC, the built-in DDC is used to complete the first down-conversion, which is called DDC_1. The ideal mixing frequency is f _c , but in reality, the NCO bit width is too small and only 12 bits, resulting in a frequency slightly larger than f _c , denoted as fc_actual; signal The bandwidth is B, and 4 times decimation is performed to reduce the data rate to f _s /4, which is guaranteed

The signal inside is not aliased.

After the data is input to the field programmable gate array FPGA, the second down-conversion is called DDC_2. This processing is not performed in the whole frequency band, and the frequency is shifted down according to the frequency of the signal, or up-shifted and further extracted to reduce the data rate.

其中f_H＝f₀+B/2，f_L＝f₀-B/2确定，模拟数据经过内置ADC模块后完成模数转换，得到数字信号，该信号需混频到基带上，混频所需的本振信号由其内部数控振荡器NCO产生，NCO的频率调谐字可通过下式计算：Please refer to FIG. 2. FIG. 2 is a structural block diagram of a built-in DDC of a high-speed analog-to-digital converter based on a multi-channel signal preprocessing method of a wideband receiver provided by an embodiment of the present invention, which is a structural block diagram of a built-in digital down-conversion DDC of a high-speed analog-to-digital converter. ; The data processed by the front-end analog completes the analog-to-digital conversion in this step, and completes the first-level digital down-conversion. The sampling frequency f _s is obtained by the intermediate frequency sampling theorem:

Where f _H =f ₀ +B/2, f _L =f ₀ -B/2 is determined, the analog data is converted through the built-in ADC module to complete the analog-to-digital conversion, and a digital signal is obtained. The signal needs to be mixed to the baseband. The required local oscillator signal is generated by its internal numerically controlled oscillator NCO, and the frequency tuning word of the NCO can be calculated by the following formula:

fc为中频，fs为采样频率，mod为求余函数，round为四舍五入函数，需要说明，由于数控振荡器NCO的位宽仅有12bit，所以得到的频率调谐字并不精确，也说明了在现场可编程门阵列FPGA中完成第二级数字下变频的必要性。ADC内置的滤波器为半带滤波器，最多为四级半带滤波器级联，可完成最多16倍的抽取，原理上可以在ADC内部完成16倍的抽取，减轻优化现场可编程门阵列FPGA运算所需资源，但由于半带滤波器频响特性较差，过渡带较宽，容易发生频谱混叠，所以不在ADC内部完成大倍数的抽取，该部分数字下变频的主要目的为降低数据率，减轻现场可编程门阵列FPGA的运算负担。

fc is the intermediate frequency, fs is the sampling frequency, mod is the remainder function, and round is the rounding function. It needs to be explained that since the bit width of the numerical control oscillator NCO is only 12 bits, the frequency tuning word obtained is not accurate, which also shows that in the field The necessity of completing the second stage of digital downconversion in programmable gate array FPGAs. The built-in filter of the ADC is a half-band filter, which can be cascaded up to four stages of half-band filters, which can complete up to 16 times of decimation. However, due to the poor frequency response characteristics of the half-band filter and the wide transition band, spectrum aliasing is prone to occur, so the decimation of large multiples is not completed inside the ADC. The main purpose of this part of the digital down-conversion is to reduce the data rate. , reduce the computational burden of field programmable gate array FPGA.

After obtaining the working parameters required by the ADC, the field programmable gate array FPGA completes the configuration through the SPI protocol. After the configuration is successful, the ADC can successfully communicate with the field programmable gate array FPGA, and the data will be encoded in the 204b protocol inside the ADC. The data is sent to the field programmable gate array FPGA through the GTX link layer of the gigabit transceiver, and then the field programmable gate array FPGA completes the data analysis processing and subsequent preprocessing process.

In this design, after the ADC completes the first-stage digital down-conversion DDC, the data is transmitted to the field programmable gate array FPGA, and the interference spectrum analysis is performed on the data of one of the channels in the field programmable gate array FPGA. Implementation algorithm: choose to intercept the data in the middle and back sections of each pulse repetition period based on the rising edge of the pulse, and every 256 data is a unit. The purpose is to increase the suppression of side lobes, and then continuously perform 8 groups of 256-point fast Fourier transform FFT, accumulate the results of each group of fast Fourier transform FFT, and perform FFTSHIFT operation to obtain 256 points. The obtained 256 points are sent to the signal processing extension through the optical fiber, which is used for the signal processing extension to perform anti-interference processing, establish a look-up table, and complete the corresponding relationship between the 256 fast Fourier transform FFT values and m frequency points, and then use the signal The processing extension finds the frequency band with the least interference, adds it to the mode word, and finds the corresponding frequency point from the correspondence of the look-up table to complete the frequency agility.

Please refer to FIG. 3 , FIG. 3 is an internal DDC implementation structure of a field programmable gate array based on a multi-channel signal preprocessing method of a wideband receiver provided by an embodiment of the present invention, which is an internal digital down-conversion DDC implementation structure of the field programmable gate array; The ADC transmits the data to the field programmable gate array FPGA through the serial high-speed line. After the JESD204B decoding in the field programmable gate array FPGA, the data is restored to f _s /4, 32bit after data recombination.

In the design, the narrowband and wideband switching is done, and the full frequency band is always processed. Figure 3 shows the processing flow of one channel. In the FPGA design, the mixing coefficient generated by DDS is only related to the actual intermediate frequency of the signal, and has nothing to do with the signal bandwidth, so the mixing module can be used for wide/narrowband multiplexing. However, the structure of wide and narrowband filtering is different, so this module cannot be reused. For the full frequency band, the low beam signal is temporarily processed in the field programmable gate array FPGA for fast Fourier transform FFT spectral analysis. The processing method of multiple DDC_2 in the field programmable gate array FPGA is the same.

rem为求余函数，round四舍五入函数，fs采样频率，f₀为中频。经仿真，当N＝48时，DDS核产生的混频系数是准确的。计算f₀时将ADC产生的频偏考虑在内，将对应产生的m个Δθ存储在ROM中。通过改变Δθ即可产生不同的混频系数。The center frequency of the mixing coefficient depends on the frequency value in the mode word transmitted by the optical fiber to the field programmable gate array FPGA. According to the value of the frequency point, the DDS_IP core is used in the field programmable gate array FPGA to generate the mixing coefficient and complete the complex multiplication with the input data. Calculation formula:

rem is the remainder function, round is the rounding function, fs sampling frequency, and f ₀ is the intermediate frequency. Through simulation, when N=48, the mixing coefficient generated by the DDS core is accurate. When calculating f ₀ , the frequency offset generated by the ADC is taken into account, and the corresponding generated m Δθ are stored in the ROM. Different mixing coefficients can be generated by changing Δθ.

After completing the multi-channel data mixing, enter the filtering module to complete the low-pass filtering of the multi-channel data, the main purpose is to filter out the "image frequency" component introduced by the mixing. When implementing low-pass filtering, use the FIR_IP core of the FPGA. The narrowband filter coefficient is set to 1426th order or 2015th order here. Because the extraction multiple is too high, an improved "polyphase filter structure" is adopted, and the filtering and extraction are completed at the same time.

The low-pass filter LPF of narrow-band filtering is designed with 1426 order coefficients, 1427 coefficients, a passband of 1M, a transition bandwidth of 0.5M, and an out-of-band rejection of 85dB. The narrowband filter coefficients are designed using the Fdatool tool in MATLAB. If the narrowband filter directly uses the structure of polyphase filtering, it needs to add zeros to 1440 after 1427 coefficients. Assuming that 90 times of extraction needs to be completed, it needs to be divided into 90 channels with 16 coefficients per channel. The usage analysis is as follows: each channel I or Each Q uses 1 DSP48, configures 16 coefficients, uses 90+90 DSP48, and 5 channels requires 900 DSP48, which will waste a lot of DSP48.

Narrowband filtering uses a new structure. Filtering is equivalent to correlating data with filter coefficients. If each data coefficient is slid once to complete the correlation operation, 1427 DSP48s are required, and then 90-fold decimation is performed to obtain the final digital down-conversion DDC result. In this design, every 90 data coefficients slide once to complete the correlation operation, and the filtering and decimation are completed at the same time. After 1427 coefficients are filled with zeros to 1440, 1440/90=16 DSP48s are required, the working speed is 180MHz, and each channel I +Q requires 32 DSP48s. Please refer to FIG. 4. FIG. 4 is a schematic diagram of a narrowband signal filter based on a multi-channel signal preprocessing method of a wideband receiver provided by an embodiment of the present invention. The design schematic diagram of the narrowband signal filter is shown in FIG. 4. The real and imaginary part processing is the same:

In the broadband mode, the mixed data is windowed, and the window length and window position are parsed from the mode word, and the data rate is diluted from f _s /4 to f _s /8 for subsequent broadband filtering. After completing the multi-channel data windowing, enter the broadband filtering module to complete the low-pass filtering of the multi-channel data, the main purpose is to filter out the "image frequency" component introduced by the mixing. When implementing low-pass filtering, use the FIR_IP core of the field programmable gate array FPGA. The broadband filter coefficients are generated by the FDA tool. Due to the high order of the filter coefficients, a "polyphase filter structure" is adopted, and the filtering and extraction are completed at the same time.

The external strong and narrow pulses appear as a few large values after the digital down-conversion DDC. With the difference in the width and intensity of the narrow pulses, the number of expansion points after DDC is different, which will lead to the formation of a step after the pulse pressure. "False alarm". Therefore, narrow pulse rejection needs to be performed after the DDC is completed.

Implementation algorithm: Take PT protection units on the left and right of the judgment point, and then take n points to average, and use relative threshold and absolute threshold to judge. If both are satisfied, remove the point by setting zero, otherwise keep it. Among them, the function of the relative threshold is to judge whether the point is a narrow pulse point, and its high position controls the opening and disabling of the module; the function of the absolute threshold is to avoid eliminating noise and signals.

Please refer to FIG. 5 . FIG. 5 is an implementation structure of narrow pulse elimination based on a multi-channel signal preprocessing method of a wideband receiver provided by an embodiment of the present invention, where T represents the point of judgment, and PT represents the number of protection units. If the protection unit is set to 1, narrow pulses with an intensity of less than -31dB and a width of 1.0us can be rejected, but for the strong and narrow pulse echoes of 1.5us in the near area, the middle point will be rejected to form a notch. In order to avoid eliminating the 1.5us narrow pulse echo in the near area emitted by the whole machine, only the narrow pulse interference in the "wide pulse echo area" is excluded in this design, and the corresponding distance is beyond 15Km.

Please refer to FIG. 6. FIG. 6 is a structure diagram of an implementation of anti-asynchronous interference based on a multi-channel signal preprocessing method of a wideband receiver provided by an embodiment of the present invention, which is an implementation structure of anti-asynchronous interference; Influence, anti-asynchronous processing. Since the repetition frequency of other radars is different from that of the local radar, the position of the range gate is different in the adjacent pulse repetition period (PRT); and the greater the repetition frequency difference, the greater the range gate difference.

Implementation algorithm: use RAM to store the data of a PRT, each time 1/8*PRT+7/8*RAMPRT represents the value of the current PRT, and RAM represents the value of the previous PRT stored in the RAM to be updated to the RAM. Use the relative threshold and the absolute threshold to judge the value of the same orientation in the current PRT and RAM. If the two thresholds are satisfied at the same time, the point is eliminated by setting zero, otherwise it is retained. The relative threshold determines that the point is an asynchronous interference point, and its high bit controls the opening and disabling of the module; the function of the absolute threshold is to avoid eliminating noise and signals.

After the above process is completed, the multi-channel data will be packaged and sent to the signal processing extension by the optical fiber transmission module, and the entire data reception and preprocessing process is completed at this point.

The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be considered that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deductions or substitutions can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (1)

1. A multichannel signal preprocessing method based on a broadband receiver is characterized by comprising the following steps:

determining the intermediate frequency f of the echo signal₀And modulating the bandwidth B to obtain the sampling frequency f of the ADC_sThe following requirements are met:

wherein f is_H＝f₀+B/2，f_L＝f₀-B/2，f_hReferred to as the upper limit frequency, f_lReferred to as the lower limit frequency; from which we can determine the sampling frequency f_s(ii) a Because a built-in digital down-conversion module of an analog-to-digital converter (ADC) is required to be utilized, an extraction multiple and a filter bandwidth are required to be determined, and after parameters are determined, the ADC can be configured to work in a corresponding mode;

the multi-chip analog-to-digital converter (ADC) works under the same parameter, and a data frame obtained by encoding data of the multi-chip multi-channel analog-to-digital converter (ADC) through a 204b protocol is sent to a Field Programmable Gate Array (FPGA) for de-framing; after the frame is decoded, data after the first-stage digital down-conversion can be obtained;

the processed data are mixed to be near zero frequency, the data rate is greatly reduced after two-stage half-band filtering, the data are suitable for being preprocessed by a Field Programmable Gate Array (FPGA), the data of a certain channel are subjected to frequency spectrum analysis in the step, the Field Programmable Gate Array (FPGA) completes fast Fourier transform ((FFT) operation, the obtained FFT calculation result is sent to a signal processor by an optical fiber, the signal processor further finds out a frequency point with minimum interference, and the frequency point can be used for an intermediate frequency value of next mixing, so that frequency agility is achieved, and the working frequency of the radar can be guided to a gap or a weak area of an interference frequency spectrum;

when the radar works in a frequency conversion mode, a second-stage Digital Down Conversion (DDC) is required to be completed, signals are mixed to a baseband, and further, extraction of a larger multiple is completed; the center frequency of the mixing coefficient is resolved from the mode word received by the optical fiber; according to the frequency point value, generating a mixing coefficient by using a DDS _ IP core in a Field Programmable Gate Array (FPGA), and completing complex multiplication with input data; storing m mixing coefficients delta theta generated corresponding to the previous step in a ROM, and completing frequency point selection through analyzing mode words; the FIR _ IP core in a Field Programmable Gate Array (FPGA) is used for finishing filtering extraction, the coefficient of the filter can be generated by an FDA tool of MATLAB, the generated coefficient is stored in rom, and the coefficient can be automatically read into the FIR _ IP to finish operation when the system is started;

the external strong and narrow pulse is represented as a few larger values after digital down-conversion (DDC) (along with the difference of the width and the strength of the narrow pulse, the number of extension points after the digital down-conversion (DDC) is different), which can cause a step to be formed after pulse pressure and a false alarm to appear; therefore, narrow pulse rejection is required after Digital Down Conversion (DDC) is completed;

the various preprocessing results are sent to the signal processor through the optical fiber, and the optical fiber also receives the mode words sent by the signal processor and analyzes the working parameters of all parts of the receiver.

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