CN111223916A - Semiconductor device, method of making the same, and three-dimensional memory - Google Patents
Semiconductor device, method of making the same, and three-dimensional memory Download PDFInfo
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- CN111223916A CN111223916A CN202010032358.8A CN202010032358A CN111223916A CN 111223916 A CN111223916 A CN 111223916A CN 202010032358 A CN202010032358 A CN 202010032358A CN 111223916 A CN111223916 A CN 111223916A
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- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
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- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
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- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
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Abstract
The invention provides a semiconductor device, a preparation method thereof and a three-dimensional memory device, wherein in the preparation method of the semiconductor device, the etching step of a gate insulating layer at two sides of a gate structure (comprising a gate and an offset interval formed on the side wall of the gate) of a high-voltage region is adjusted between the light doping leakage processing step and the forming step of an interval side wall, so that the problem that when the bottom gate insulating layer at two sides of the gate structure of the high-voltage region is etched in the prior art, an oxide interval side wall (a first interval side wall) in the interval side wall of the gate structure and an oxide offset interval in the offset interval cause undesirable etching at the same time, and a defect groove is formed at the top of the oxide interval side wall and the oxide offset interval can be effectively avoided.
Description
Technical Field
The invention belongs to the field of semiconductor design and manufacture, and particularly relates to a semiconductor device, a preparation method thereof and a three-dimensional memory.
Background
TAS SPACER ETCH, a two-step method is currently used to ensure that the desired thickness of insulating film spacers (insulating film spacers) and gate insulating layer GOX of the high-voltage region is obtained, but when the gate insulating layer GOX of the high-voltage region is etched, the top of the oxide layer of the offset spacers (generally including the oxide layer and the nitride layer from inside to outside) formed on the sidewalls of the gate is also etched, so that a recess is formed on the oxide layer of the offset spacers and the top of the oxide layer of the spacer sidewalls, which may cause a problem in the stability of the device to be subsequently manufactured.
Therefore, how to provide a semiconductor device, a method for manufacturing the same, and a three-dimensional memory to solve the above problems of the prior art is necessary.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a semiconductor device, a method for fabricating the same, and a three-dimensional memory, which are used to solve the technical problems of TAS SPACER ETCH in the prior art, such as the top of the oxide layer of the offset spacers and the spacer sidewalls (typically including the oxide layer and the nitride layer from inside to outside) being etched, and forming a recess on the top of the oxide layer of the offset spacers and the spacer sidewalls, which is a hidden danger for the stability of the device to be fabricated subsequently.
To achieve the above and other related objects, the present invention provides a semiconductor device manufacturing method, including:
providing a semiconductor structure comprising a substrate having a first region and a second region, a first gate insulating layer and a second gate insulating layer formed on the first region and the second region, respectively, and a number of discrete gate structures formed on the first gate insulating layer and the second gate insulating layer, respectively;
carrying out light doping leakage treatment on the first region;
thinning the first gate insulation layer positioned at two sides of the gate structure on the first region to form a boss structure on the upper surface of the first gate insulation layer;
the gate structure on the first gate insulating layer is located on the boss structure, and the lower surface of the gate structure on the boss structure completely covers the upper surface of the boss structure.
In one embodiment, the forming process of the gate structure includes:
forming a plurality of discrete gates on the first gate insulating layer and the second gate insulating layer, respectively;
offset spacers are formed on sidewalls of the gate.
In an embodiment, the step of forming the offset spacers on the sidewalls of the gate includes sequentially forming a first offset spacer and a second offset spacer from inside to outside on the sidewalls of the gate.
In one embodiment, the material of the first offset spacers comprises an oxide and the second offset spacers comprises a nitride.
In one embodiment, the material of the gate comprises polysilicon.
In an embodiment, after the first gate insulating layer on the first region on both sides of the gate structure is thinned to form the mesa structure on the upper surface of the first gate insulating layer, the method further includes forming a spacer on a sidewall of the gate structure.
In one embodiment, the step of forming spacer sidewalls on the sidewalls of the gate structure comprises:
and forming a spacing side wall material layer covering the gate structure, and etching to remove the spacing side wall material layer at the top of the gate structure so as to form the spacing side wall on the common side wall of the gate structure and the boss structure on the first region and the side wall of the gate structure in the second region respectively.
In one embodiment, the step of forming a spacer sidewall material layer covering the gate structure, and etching away the spacer sidewall material layer on top of the gate structure to form the spacer sidewall on the common sidewall of the gate structure and the mesa structure in the first region and the sidewall of the gate structure in the second region respectively includes:
forming a first spacer sidewall material layer overlying the gate structure;
forming a second spacer sidewall material layer overlying the first spacer sidewall material layer;
and etching and removing the second interval side wall material layer and the first interval side wall material layer positioned at the top of the gate structure in sequence so as to form a first interval side wall and a second interval side wall from inside to outside respectively on the common side wall of the gate structure and the boss structure positioned in the first area and the side wall of the gate structure positioned in the second area.
In one embodiment, the material of the first spacer sidewalls comprises an oxide and the material of the second spacer sidewalls comprises a nitride.
In an embodiment, the thickness of the first spacer sidewall material layer is less than the thickness of the mesa structure.
In an embodiment, an isolation structure is formed in the substrate, the isolation structure dividing the substrate into the first region and the second region.
In an embodiment, the isolation structure comprises shallow trench isolation.
In an embodiment, before the thinning process is not performed, the thickness of the first gate insulating layer is greater than the thickness of the second gate insulating layer.
In one embodiment, the first region is a high pressure region and the second region is a low pressure region.
In an embodiment, the material of the first gate insulating layer comprises an oxide, and the material of the second gate insulating layer comprises an oxide.
In an embodiment, the step of performing lightly doped drain processing on the first region includes:
forming a patterned mask on the semiconductor structure, wherein the patterned mask exposes the first gate insulating layer and the gate structure formed on the first gate insulating layer;
and carrying out light doping leakage treatment on the first region by utilizing the graphical mask.
In an embodiment, the step of thinning the first gate insulating layer on both sides of the gate structure on the first region to form a mesa structure on the upper surface of the first gate insulating layer includes:
and thinning the first gate insulating layers on two sides of the gate structure on the first region by using the graphical mask.
To achieve the above and other related objects, the present invention also provides a semiconductor device including:
a semiconductor structure, the semiconductor structure comprising:
a substrate having a first region and a second region;
the first grid insulating layer and the second grid insulating layer are respectively positioned on the first area and the second area, and the first grid insulating layer is provided with a main body part and a boss structure which is formed by upwards protruding from the upper surface of the main body part; and
a plurality of discrete gate structures formed on the mesa structure of the first gate insulating layer and on the second gate insulating layer, respectively;
and a lightly doped drain region is formed in the substrate at two sides of the gate structure in the first region, and the lower surface of the gate structure formed above the boss structure completely covers the upper surface of the boss structure.
In one embodiment, the gate structure includes a gate and an offset spacer formed on a sidewall of the gate.
In an embodiment, the offset spacers include a first offset spacer and a second offset spacer sequentially formed on sidewalls of the gate from inside to outside.
In one embodiment, the material of the first offset spacers comprises an oxide and the second offset spacers comprises a nitride.
In one embodiment, the material of the gate comprises polysilicon.
In an embodiment, an isolation structure is formed in the substrate, the isolation structure dividing the substrate into the first region and the second region.
In an embodiment, the isolation structure comprises shallow trench isolation.
In an embodiment, a thickness of the first gate structure at the mesa structure is greater than a thickness of the second gate insulation layer.
In one embodiment, the first region is a high pressure region and the second region is a low pressure region.
In an embodiment, the material of the first gate insulating layer comprises an oxide, and the material of the second gate insulating layer comprises an oxide.
In an embodiment, the semiconductor device further includes spacer sidewalls formed on a common sidewall of the gate structure and the mesa structure on the first region and a sidewall of the gate structure on the second region, respectively.
In an embodiment, the spacer sidewalls are sequentially formed on a common sidewall of the gate structure and the mesa structure in the first region and a first spacer sidewall and a second spacer sidewall of a sidewall of the gate structure in the second region from inside to outside, respectively.
In one embodiment, a bottom surface of the second spacer sidewall is lower than an upper surface of the mesa structure.
In one embodiment, the material of the first spacer sidewalls comprises an oxide and the material of the second spacer sidewalls comprises a nitride.
The invention also provides a three-dimensional memory prepared by adopting the semiconductor structure.
In the invention, by optimizing the process steps, the etching step of the gate insulating layer at two sides of the gate structure (comprising the gate and the offset interval formed on the side wall of the gate) of the high-voltage region is adjusted between the lightly doped drain processing step and the forming step of the interval side wall, so that the problem that when the bottom gate insulating layer at two sides of the gate structure of the high-voltage region is etched in the prior art, the oxide interval side wall (first interval side wall) in the interval side wall of the gate structure and the oxide offset interval in the offset interval can be simultaneously subjected to undesired etching, and thus a defective groove is formed at the top of the oxide interval side wall and the oxide offset interval can be effectively avoided;
by using the invention, the etching step of the grid insulation layer at two sides of the grid structure of the high-voltage area and the process step of lightly doping the drain LDD in the high-voltage area share one MASK MASK, thereby reducing the production cost.
Drawings
Fig. 1 shows a flow chart of an exemplary semiconductor device fabrication process.
Fig. 2 is a schematic structural view of a semiconductor device manufactured by a manufacturing process of the semiconductor device of fig. 1.
Fig. 3 shows an enlarged view of the area indicated by the circle in fig. 2.
Fig. 4 is a TEM photograph showing a semiconductor device manufactured by the manufacturing process of the semiconductor device of fig. 1.
Fig. 5 is a schematic flow chart showing a method for manufacturing a semiconductor device according to the present invention.
Fig. 6 is a schematic view showing a semiconductor structure in the manufacturing method of the semiconductor device of the present invention.
Fig. 7 is a schematic cross-sectional view of a patterned mask layer formed on a semiconductor structure in a method for fabricating a semiconductor device according to the present invention.
Fig. 8 is a schematic cross-sectional view illustrating a lightly doped drain process performed on the first region by using a patterned mask layer in the method for manufacturing a semiconductor device according to the present invention.
Fig. 9 is a schematic cross-sectional view of the semiconductor device according to the present invention after thinning the first gate insulating layer on both sides of the gate structure in the first region by using a patterned mask layer.
Fig. 10 is a schematic cross-sectional view illustrating a spacer sidewall material layer covering a gate structure formed in a method for fabricating a semiconductor device according to the present invention.
Fig. 11 is a schematic cross-sectional view illustrating the formation of spacer sidewalls with sidewalls of the gate structure in the method for fabricating a semiconductor device according to the present invention.
Fig. 12 shows a TEM photograph of a semiconductor device manufactured by the manufacturing method of the semiconductor device of the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Fig. 1 shows a flow chart of a method for manufacturing the semiconductor device in TAS SPACER ETCH. The preparation method of the semiconductor device comprises the following steps:
providing a semiconductor structure, wherein the semiconductor structure comprises a substrate 1' having a high-voltage region and a low-voltage region, a first gate insulating layer 81' and a second gate insulating layer 82' formed on the high-voltage region and the low-voltage region, respectively, and a plurality of discrete gate structures formed on the first gate insulating layer 81' and the second gate insulating layer 82', respectively, wherein the substrate 1' is divided into a high-voltage region a1 and a low-voltage region a2 by shallow trench isolation 2' disposed therein, the gate structures comprise a gate 3' and offset spacers (offset spacers) formed on sidewalls of both sides of the gate 3', and the offset spacers include, but are not limited to, an oxide offset spacer 4' and a nitride offset spacer 5 ';
step two, forming a first patterned mask exposing the high-voltage area A1 on the semiconductor structure by adopting a photoetching process;
step three, performing lightly doped drain ion implantation (HV LDD IMP) on the high-voltage region a1 by using the first mask to form lightly doped drain regions (not shown) in the substrate 1' on both sides of the gate structure on the high-voltage region a1, and in addition, before performing step four, removing the first mask and performing a cleaning process;
forming a spacer sidewall material layer on the gate structures of the two regions, specifically, forming an oxide layer on the gate structures of the two regions, and then forming a nitride layer on the surface of the oxide layer;
etching the spacer sidewall material layer to form spacer sidewalls on sidewalls of the gate structures in the two regions, wherein the spacer sidewalls include but are not limited to oxide spacer sidewalls 6 'and nitride spacer sidewalls 7';
step six, forming a second mask for exposing the high-voltage area A1 on the structure formed in the step five through a photoetching process;
and step seven, thinning the first gate insulating layer 81 in the high-voltage area by using the second mask to form the semiconductor device shown in fig. 2, and also performing mask removal and cleaning processes after the step. Referring to fig. 2, a bump structure 812 'is formed on the upper surface of the first gate insulating layer 81'; the gate structure on the first gate insulating layer 81 'and the spacer sidewalls at two sides thereof are located on the mesa structure 812', and a common lower surface of the gate structure on the mesa structure 812 'and the spacer sidewalls at two sides thereof coincides with an upper surface of the mesa structure 812'.
In the above process steps, when the first gate insulating layer 81 'of the high voltage region a1 is thinned in step seven, since the offset spacers and the spacer sidewalls of the high voltage region a1 are also exposed by the second mask, the oxide offset spacers 4' and the tops of the oxide spacer sidewalls 6 'in the offset spacers and the spacer sidewalls are also etched away, so that defects (not shown) are formed at the tops of the oxide offset spacers 4', and defects 61 'are also formed at the tops of the oxide spacer sidewalls 6', which may adversely affect the stability of the subsequently fabricated semiconductor device; in addition, since two-step photolithography (requiring two mask lays) is employed, this increases the production process steps, thereby increasing the production cost.
Based on this, as shown in fig. 5, the present invention provides a semiconductor device, a method for manufacturing the same, and a three-dimensional memory, wherein the etching step of the gate insulating layer on both sides of the gate structure (including the gate 3 and the offset spacer formed on the sidewall of the gate 3) in the high voltage region is adjusted between the lightly doped drain process step and the spacer sidewall forming step, so as to effectively avoid the problem that the oxide spacer sidewall (the first spacer sidewall 6) in the spacer sidewall of the gate structure and the oxide offset spacer in the offset spacer are undesirably etched simultaneously when the bottom gate insulating layer on both sides of the gate structure in the high voltage region is etched in the prior art, thereby forming a defective recess on the oxide spacer sidewall and the top of the oxide offset spacer. The technical solution of the present invention will be described with reference to specific examples.
Example one
Referring to fig. 5, the present embodiment provides a method for manufacturing a semiconductor device, including:
step S10, providing a semiconductor structure including a substrate 1 having a first region a1 and a second region a2, a first gate insulating layer 81 and a second gate insulating layer 82 formed on the first region a1 and the second region a2, respectively, and a number of discrete gate structures formed on the first gate insulating layer 81 and the second gate insulating layer 82, respectively;
step S20, lightly doping the first region A1 with LDD;
step S30, thinning the first gate insulating layer 81 on both sides of the gate structure on the first region a1 to form a bump structure 812 on the top of the first gate insulating layer 81; the gate structure on the first gate insulating layer 81 is located on the mesa structure 812, and a lower surface of the gate structure on the mesa structure 812 completely covers an upper surface of the mesa structure 812.
The method for manufacturing the semiconductor device according to the present embodiment will be described in detail with reference to the accompanying drawings, in which fig. 6 to 11 are sectional views of the structure of the semiconductor device during the manufacturing process of the semiconductor device according to the present embodiment.
In step S10, referring to fig. 6, a semiconductor structure is provided, the semiconductor structure includes a substrate 1 at the bottom, the substrate 1 is, for example, a semiconductor substrate 1, and the semiconductor substrate is divided into two regions, namely, a high voltage region (i.e., a first region a1) for forming high voltage devices (e.g., high voltage transistors) and a low voltage region (i.e., a second region a2) for forming low voltage devices. It should be noted that the substrate 1 may be selected according to actual requirements of a device, the substrate 1 may include a Silicon substrate, a Germanium (Ge) substrate, a Silicon Germanium (SiGe) substrate, an SOI (Silicon-on-Insulator) substrate, a GOI (Germanium-on-Insulator) substrate, and the like, in other embodiments, the substrate 1 may also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or Silicon carbide, and the substrate 1 may also be a stacked structure, such as a Silicon/Germanium-Silicon stacked layer, and in this embodiment, the substrate 1 includes a single crystal Silicon substrate. The substrate 1 may be ion-doped, P-doped, or N-doped.
It should be noted that, although the first area a1 is a high-pressure area and the second area a2 is a low-pressure area in the present embodiment, in other embodiments, the first area a1 and the second area a2 may adopt other forms of division.
Referring to fig. 6, an isolation structure is formed in the substrate 1, and the substrate 1 is divided into high and low voltage regions by the isolation structure. As an example, the isolation structure may be, for example, a shallow trench isolation 2, the substrate 1 is divided into the first region a1 and the second region a2 by the shallow trench isolation 2, and the process of forming the shallow trench isolation 2 region includes the process steps of isolation oxide deposition, mask layer deposition (e.g., nitride), etching to form a trench, filling the trench with an insulating material (e.g., oxide), planarization, and the like.
Referring to fig. 6, in the present embodiment, the isolation structure is a shallow trench isolation 2, and before the etching and thinning process is not performed, the height of the shallow trench isolation 2 is higher than the first gate insulation layer 81 located on the first region a1 and the second gate insulation layer 82 located on the second region a 2. It should be noted that, in some embodiments, the height of the shallow trench isolation 2 may be adjusted according to actual needs; in some embodiments, the shallow trench isolation 2 may be replaced by other types of isolation structures.
Referring to fig. 6, a high voltage gate insulating layer is formed on the high voltage region of the substrate 1 as a first gate insulating layer 81, and a low voltage gate insulating layer is formed on the high voltage region of the substrate 1 as a second gate insulating layer 82; the thicknesses of the high-voltage gate insulating layer and the low-voltage gate insulating layer are related to the turn-on voltage or the threshold voltage of the device formed in the region, and generally, the thicker the gate insulating layer is, the higher the turn-on voltage is, so that the thickness of the first gate insulating layer 81 disposed on the surface of the high-voltage region is greater than the thickness of the second gate insulating layer 82 disposed on the surface of the low-voltage region. As an example, the material of the first and second gate insulating layers 82 may be, for example, oxide. In a specific example, the material of the first and second gate insulating layers 81 and 82 may be silicon dioxide, for example.
In step S10, referring to fig. 6, the forming process of the gate structure includes: forming a plurality of discrete gate electrodes 3 on the first gate insulating layer 81 and the second gate insulating layer 82, respectively; offset spacers are formed on the sidewalls of the gate 3. As an example, a gate material layer may be formed on the first gate insulating layer 81 and the second gate insulating layer 82, respectively, and then several discrete gates 3 may be formed on the first gate insulating layer 81 and the second gate insulating layer 82, respectively, through an etching process, for example. As an example, the material of the gate material layer may include polysilicon, for example. In an example, in the step of forming a plurality of discrete gates 3 on the first gate insulating layer 81 and the second gate insulating layer 82, the plurality of discrete gates 3 may be formed on the first gate insulating layer 81 and the second gate insulating layer 82 in the same process step, and the gates on the first gate insulating layer 81 and the second gate insulating layer 82 have the same structure; in another example, the step of forming a plurality of discrete gates 3 on the first gate insulating layer 81 and the second gate insulating layer 82 may be to form the gates 3 on the first gate insulating layer 81 and the gates 3 on the second gate insulating layer 82 respectively in different process steps, and when the process steps are different, the gates 3 on the first gate insulating layer 81 and the gates 3 on the second gate insulating layer 82 may have the same structure or different structures.
In step S10, the step of forming the offset spacers on the sidewalls of the gate 3 includes sequentially forming a first offset spacer 4 and a second offset spacer 5 on the sidewalls of the gate 3 from inside to outside. By way of example, the material of the first offset spacers 4 includes, but is not limited to, an oxide, such as silicon dioxide or the like; the material of the second offset spacers 5 includes, but is not limited to, nitride, such as silicon nitride, etc. In an example, a first offset spacer material layer covering the gate 3 and other exposed areas of the semiconductor structure may be deposited on the gate 3 in the two regions, then a second offset spacer material layer may be deposited on the first offset spacer material layer, and finally, the second offset spacer material layer and the first offset spacer material layer except the second offset spacer material layer covering the top of the gate 3 and both sides of the gate 3 may be sequentially etched away, so as to sequentially form a first offset spacer 4 and a second offset spacer 5 on the sidewalls of the gate 3 in the two regions from inside to outside. In another example, a first offset spacer material layer covering the gate 3 and other exposed areas of the semiconductor structure may be deposited on the gate 3 in the two regions, and then the first offset spacer material layer covering the top of the gate 3 and both sides of the gate 3 is removed by etching, so as to form first offset spacers 4 on the sidewalls of the gate 3 in the two regions from inside to outside in sequence; then, a second offset spacer material layer is formed on the surface of the structure formed in the previous step, and then the second offset spacer material layer covering the top of the gate 3 and the exposed sidewall of the first offset spacer 4 is etched away to form a second offset spacer 5 on the exposed sidewall of the first offset spacer 4 in two regions. Note that, for example, the first offset spacer material Layer and the second offset spacer material Layer may be formed by using a process such as a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, or an Atomic Layer Deposition (ALD). It should be noted that, as the size of the device is further reduced, the reaching length of the device is smaller and smaller, the ion implantation depth of the source and drain is also smaller and smaller, and the offset interval functions to improve the channel length of the formed transistor, and reduce the short channel effect and the hot carrier effect caused by the short channel effect.
In step S20, referring to fig. 7 and 8, as the width of the gate 3 is continuously decreased, the channel length under the gate 3 is continuously decreased, in order to effectively prevent the short channel effect, the first region a1 needs to be lightly doped with drain LDD (using a downward arrow in fig. 8), and the step of lightly doping the first region a1 includes forming a patterned mask 9 on the semiconductor structure, where the patterned mask 9 exposes the first gate insulating layer 81 and the gate structure formed on the first gate insulating layer 81; the first region a1 is subjected to a lightly doped drain process using the patterned mask 9. As an example, the patterned mask 9 may be formed by using a photolithography process, the material of the patterned mask 9 may be, for example, a photoresist PH, and in other examples, the patterned mask 9 may also use other suitable mask materials. As an example, the method of forming the LDD may be an ion implantation process or a diffusion process, and the ion implantation process may be performed in one or more steps according to the concentration of the desired dopant ions. As an example, when performing lightly doped drain LDD processing, large-mass dopant ions may be used, and a shallow junction formed by combining a large-mass material and an amorphous state on the surface of the substrate 1 may be used to reduce the channel leakage current effect between the source and the drain. As an example, lightly doped drain implant LDD can be divided into N-lightly doped drain implant N-LDD, and P-lightly doped drain implant P-LDD; when performing N-LDD implantation, one or a combination of phosphorus, arsenic, antimony and bismuth can be adopted, for example, arsenic ions are selected, arsenic ion implantation is performed in a region which is not protected by the graphical mask 9 (such as photoresist), so that low-energy shallow junctions are formed, arsenic is selected as the implantation ions of the N-LDD, and the large molecular weight of arsenic is favorable for amorphization of the silicon surface, so that more uniform doping depth can be obtained in the implantation; and when P-LDD implantation is carried out, boron fluoride which is easier to amorphize the silicon surface is adopted for ion implantation to form a shallow junction with low energy. After the ion implantation is completed, a step of annealing the ion-implanted device is further included to remove semiconductor defects caused by the ion implantation and activate the implanted ions.
In step S30, referring to fig. 9, the step of thinning the first gate insulating layer 81 on both sides of the gate structure on the first region a1 to form a bump structure 812 on the upper surface of the first gate insulating layer 81 includes: the first gate insulating layer 81 on both sides of the gate structure on the first region a1 is thinned by using the patterned mask 9, so as to form a bump structure 812 on the upper surface of the first gate insulating layer 81. As an example, the thinning process may employ a dry etching process to etch the first gate insulating layer 81 exposed by the patterned mask 9, and the gate structure (the gate 3 and the offset space on both sides thereof) located above the first region a1 may effectively protect a portion of the first gate insulating layer 81 directly below the first region a1 from being etched, so that only the first gate insulating layer 81 on both sides of the gate structure on the first region a1 is etched during etching, thereby forming the mesa structure 812, and the lower surface of the gate structure on the mesa structure 812 completely covers the upper surface of the mesa structure 812, that is, the area of the lower surface of the gate structure on the mesa structure 812 is greater than or equal to the area of the upper surface of the mesa structure 812. As an example, when the thinning process is performed, the thickness of the first gate insulating layer 81 at both sides of the gate structure, that is, the thickness of the main body portion 811 may be controlled by controlling the etching parameters. As an example, when the first gate insulating layer 81 on both sides of the gate structure on the first region a1 is thinned, the top of the shallow trench isolation 2 in the region is simultaneously etched, so that the surface of the shallow trench isolation 2 in the first region a1 is lower than the surface of the shallow trench isolation 2 in the second region a 2. It should be noted that, during the process of thinning the first gate insulating layer 81 on both sides of the gate structure on the first region a1, the top of the oxide layer OX (the first offset spacer 4) in the offset spacer on both sides of the gate 3 is etched, and a recess defect (not shown) is formed on the top of the oxide layer in the offset spacer, but the recess defect is filled when the first spacer sidewall material layer 60 (typically, an oxide is also selected) is filled in the subsequent step S40, so as to compensate the recess defect.
It should be noted that, in this embodiment, the same patterned mask 9 is used in the step S20 and the step S30 to perform the LDD process of the high voltage region and the thinning process of the first gate insulating layer 81 of the high voltage region, so as to effectively reduce the production cost. Of course, in other embodiments, different patterned masks 9 may be used in step S20 and step S30, respectively, so that after the LDD processing in the high voltage region, the mask material on the semiconductor device needs to be removed first, and then after cleaning, a new patterned mask 9 is made again, and the first gate insulating layer 81 in the high voltage region is thinned by the new patterned mask 9.
Referring to fig. 5, after the first gate insulating layer 81 on both sides of the gate structure on the first region a1 is thinned to form the mesa structure 812 on the upper surface of the first gate insulating layer 81, in order to prevent the source-drain implantation with a large dose from being too close to the channel, which may result in too short channel and even source-drain connection, the method further includes step S40 of forming a spacer sidewall on the sidewall of the gate structure.
In step S40, the step of forming a spacer sidewall on the sidewall of the gate structure includes forming a spacer sidewall material layer covering the gate structure; etching and removing the spacer side wall material layer on the top of the gate structure to form the spacer side wall on the side wall of the gate structure; the spacer sidewall material layer covers the exposed surface of the semiconductor device on both sides of the gate structure and the sidewall of the mesa structure 812 in addition to the gate structure, and the spacer sidewalls formed after etching are also formed on the sidewall of the mesa structure 812, in other words, the spacer sidewalls are respectively formed on the common sidewall of the gate structure and the mesa structure 812 located in the first region a1 and the sidewall of the gate structure located in the second region a 2.
Specifically, in this embodiment, referring to fig. 10 and 11, the step of forming a spacer material layer covering the gate structure, and etching to remove the spacer material layer at the top of the gate structure so as to form the spacer on the sidewall of the gate structure includes: forming a first spacer sidewall material layer 60 covering the gate structure, wherein the first spacer sidewall material layer 60 covers the exposed surface of the semiconductor device on both sides of the gate structure and the sidewall of the mesa structure 812, in addition to the gate structure; forming a second spacer sidewall material layer 70 overlying the first spacer sidewall material layer 60; the second spacer sidewall material layer 70 and the first spacer sidewall material layer 60 on top of the gate structure are sequentially etched away to form a first spacer sidewall 6 and a second spacer sidewall 7 from the inside and the outside respectively on the common sidewall of the gate structure and the mesa structure 812 in the first region a1 and the sidewall of the gate structure in the second region a 2. By way of example, the material of the first spacer sidewalls 6 includes, but is not limited to, an oxide, such as silicon dioxide; the material of the second spacer sidewalls 7 includes, but is not limited to, nitride, such as silicon nitride. Referring to fig. 11, among the spacer sidewalls formed, the first spacer sidewall 6 has an L shape; the bottom surface of the horizontal portion of the first spacer 6 is flush with the top surface of the body portion 811 of the oxide layer of the first gate 3, and the top exposed surface of the horizontal portion of the first spacer 6 is formed with the second spacer 7, the second spacer 7 being in contact with the sidewall of the vertical portion of the first spacer 6. Referring to fig. 11, in one example, the thickness of the first spacer sidewall material layer is much smaller than the thickness of the mesa structure 812, and therefore, the height of the bottom of the second spacer sidewall 7 is much lower than the top surface of the mesa structure 812, it can be understood that in other examples, the thickness of the first spacer sidewall material layer can be adjusted as needed. In a specific example, the thickness of the first spacer sidewall 6 is, for example, 9-12nm, the thickness of the mesa structure 812 is 36-45nm, the thickness of the second spacer sidewall 7 is 25-35nm, and the height difference between the bottom of the second spacer sidewall 7 and the mesa structure 812 is 24-36 nm. Fig. 12 shows a TEM photograph of the semiconductor device manufactured by the method of this embodiment, and it can be seen that, in the semiconductor device obtained by the manufacturing method of this embodiment, neither the top of the first spacer sidewall 6 nor the top of the first offset spacer 4 has a notch, so that the manufacturing method of this embodiment can effectively solve the problem existing in the manufacturing flow shown in fig. 1, that is, when etching the bottom gate insulating layers on both sides of the gate structure in the high-voltage region, the oxide spacer sidewall (the first spacer sidewall 6) in the spacer sidewall of the gate structure and the top of the oxide offset spacer (the first offset spacer 4) in the offset spacer are etched at the same time, and a recess defect is formed at a corresponding position, which affects the stability of the device.
In other embodiments, the forming a spacer sidewall material layer covering the gate structure, and etching away the spacer sidewall material layer on the top of the gate structure to form the spacer sidewall on the sidewall of the gate structure includes: forming a first spacer sidewall material layer 60 covering the gate structure, and etching away the first spacer sidewall material layer 60 on top of the gate structure to form first spacer sidewalls 6 from inside and outside on the common sidewalls of the gate structure and the mesa structure 812 in the first region a1 and the sidewalls of the gate structure in the second region a2, respectively; next, a second spacer sidewall material layer 70 covering the first spacer sidewall 6 and the gate structure is formed, and the second spacer sidewall material layer 70 on the top of the gate structure and the top of the first spacer sidewall 6 is etched to remove, so as to form a second spacer sidewall 7 on the exposed sidewall of the first spacer sidewall 6, wherein the bottom surfaces of the first spacer sidewall 6 and the second spacer sidewall 7 are flush with the surfaces of the first gate insulating layer 81 on both sides of the ion-thinned mesa structure 812, that is, the bottom height of the second spacer sidewall 7 is also far lower than the top surface of the mesa structure 812.
Example two
Referring to fig. 11, the present embodiment further provides a semiconductor device manufactured by the manufacturing method of the embodiment, where the semiconductor device includes:
a semiconductor structure, the semiconductor structure comprising:
a substrate 1 having a first region a1 and a second region a 2;
a first gate insulating layer 81 and a second gate insulating layer 82 respectively located on the first region a1 and the second region a2, the first gate insulating layer 81 having a body portion 811 and a mesa structure 812 formed to protrude upward from an upper surface of the body portion 811; and
a plurality of discrete gate structures formed on the mesa structures 812 of the first gate insulating layer 81 and on the second gate insulating layer 82, respectively;
the lower surface of the gate structure formed above a mesa structure 812 completely covers the upper surface of the mesa structure 812.
Referring to fig. 11, the semiconductor structure includes a substrate 1 located at the bottom, where the substrate 1 is, for example, a semiconductor substrate 1, and the semiconductor substrate 1 is divided into two regions, namely, a high voltage region (i.e., a first region a1) for forming high voltage devices (e.g., high voltage transistors) and a low voltage region (i.e., a second region a2) for forming low voltage devices. It should be noted that the substrate 1 may be selected according to actual requirements of a device, the substrate 1 may include a Silicon substrate, a Germanium (Ge) substrate, a Silicon Germanium (SiGe) substrate, an SOI (Silicon-on-Insulator) substrate, a GOI (Germanium-on-Insulator) substrate, and the like, in other embodiments, the substrate 1 may also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or Silicon carbide, and the substrate 1 may also be a stacked structure, such as a Silicon/Germanium-Silicon stacked layer, and in this embodiment, the substrate 1 includes a single crystal Silicon substrate. The substrate 1 may be ion-doped, P-doped, or N-doped.
It should be noted that, although the first area a1 is a high-pressure area and the second area a2 is a low-pressure area in the present embodiment, in other embodiments, the first area a1 and the second area a2 may adopt other forms of division.
Referring to fig. 11, an isolation structure is formed in the substrate 1, and the substrate 1 is divided into high and low voltage regions by the isolation structure. As an example, the isolation structure may be, for example, a shallow trench isolation 2, the substrate 1 is divided into the first region a1 and the second region a2 by the shallow trench isolation 2, and the process of forming the shallow trench isolation 2 region includes the process steps of isolation oxide deposition, mask layer deposition (e.g., nitride), etching to form a trench, filling the trench with an insulating material (e.g., oxide), planarization, and the like. Referring to fig. 11, in the present embodiment, the isolation structure is a shallow trench isolation 2, and the shallow trench isolation 2 may be replaced by other types of isolation structures.
Referring to fig. 11, the thickness of the high-voltage gate insulating layer (the first gate insulating layer 81) at the bottom of the gate structure in the high-voltage region and the thickness of the low-voltage gate insulating layer (the second gate insulating layer 82) at the bottom of the gate structure in the low-voltage region are related to the turn-on voltage or the threshold voltage of the device formed in the region, and generally, the thicker the gate insulating layer is, the higher the corresponding turn-on voltage is, so that the thickness of the high-voltage gate insulating layer (i.e., the sum of the thickness of the mesa structure 812 and the thickness of the body portion 11 at the bottom of the gate structure in the high-voltage region) is greater than the thickness of the low-voltage gate insulating layer at the bottom of the gate structure in the low-voltage region, that is, the thickness of the first gate structure 81. As an example, the material of the first and second gate insulating layers 82 may be, for example, oxide. In a specific example, the material of the first and second gate insulating layers 82 may be silicon dioxide, for example.
It should be noted that the gate structure includes a gate 3 and an offset spacer formed on a sidewall of the gate 3. As an example, the gate 3 and the material of the gate 3 include polysilicon. As an example, the offset spacers include a first offset spacer 4 and a second offset spacer 5 formed on the sidewall of the gate 3 from inside to outside, the material of the first offset spacer 4 includes but is not limited to oxide (e.g., silicon dioxide), and the second offset spacer 5 includes but is not limited to nitride (e.g., silicon nitride). It should be noted that, as the size of the device is further reduced, the reaching length of the device is smaller and smaller, the ion implantation depth of the source and drain is also smaller and smaller, and the offset interval functions to improve the channel length of the formed transistor, and reduce the short channel effect and the hot carrier effect caused by the short channel effect. The process for forming the offset spacers is described in detail in a related part of the embodiments, and is not described again.
It should be noted that, as the width of the gate 3 is continuously reduced, the channel length under the gate 3 is continuously reduced, and in order to effectively prevent the short channel effect, the first region a1 needs to be lightly doped with a drain LDD (indicated by a downward arrow in fig. 8), and the first region a1 is further lightly doped with a drain LDD, so as to form LDD regions (not shown) in the substrate 1 at both sides of the gate structure of the high voltage region. It should be noted that, details of the lightly doped drain LDD processing process performed on the first region a1 are shown in relevant parts of the embodiments and will not be described herein.
Referring to fig. 11, in order to prevent the source-drain implantation with a large dose from being too close to the channel, which may result in too short channel and even source-drain connection, the semiconductor device further includes a spacer sidewall formed on the sidewalls of the gate structure and the mesa structure 812 in the first region a1 and the sidewall of the gate structure in the second region a2, that is, in the first region a1, the spacer sidewall is formed on both sidewalls of the gate structure in the first region a1 and both sidewalls of the mesa structure 812 below the gate structure, and in the second region a2, the spacer sidewall is formed on both sidewalls of the gate structure in the second region a 2. As an example, the spacer sidewalls include sidewalls of the gate structure and the mesa structure 812 formed on the first region a1 and first and second spacer sidewalls 6 and 7 of the gate structure on the second region a2 in order from the inside out. By way of example, the material of the first spacer sidewalls 6 includes, but is not limited to, an oxide, such as silicon dioxide; the material of the second spacer sidewalls 7 includes, but is not limited to, nitride, such as silicon nitride. Referring to fig. 11, among the spacer sidewalls formed, the first spacer sidewall 6 has an L shape; the bottom surface of the horizontal portion of the first spacer 6 is flush with the top surface of the body portion 811 of the oxide layer of the first gate 3, and the top exposed surface of the horizontal portion of the first spacer 6 is formed with the second spacer 7, the second spacer 7 being in contact with the sidewall of the vertical portion of the first spacer 6. Referring to fig. 11, since the thickness of the first spacer sidewall 6 is much smaller than the thickness of the first gate insulating layer 81 at the location of the mesa structure 812, the height of the bottom of the second spacer sidewall 7 is much lower than the top surface of the mesa structure 812. In a specific example, the thickness of the first spacer sidewall 6 is, for example, 9-12nm, the thickness of the mesa structure 812 is 36-45nm, the thickness of the second spacer sidewall 7 is 25-35nm, and the height difference between the bottom of the second spacer sidewall 7 and the mesa structure 812 is 24-36 nm. Fig. 12 shows a TEM photograph of the semiconductor device manufactured by the method of this embodiment, and it can be seen that, in the semiconductor device obtained by the manufacturing method of this embodiment, neither the top of the first spacer sidewall 6 nor the top of the first offset spacer 4 have a notch, so that the manufacturing method of this embodiment can effectively solve the problem existing in the manufacturing flow shown in fig. 1, that is, when etching the bottom gate insulating layers on both sides of the gate structure in the high-voltage region, the top of the oxide spacer sidewall (the first spacer sidewall 6) in the spacer sidewall of the gate structure and the top of the oxide offset spacer (the first offset spacer 4) in the offset spacer are etched at the same time, so that a groove defect is formed at a corresponding position, and the stability of the device is affected. It should be noted that the forming process of the spacer sidewalls is described in detail in the relevant part above, and is not described herein again.
In other embodiments, the first spacer sidewall 6 and the second spacer sidewall 7 are parallel structures, and the bottoms of the first spacer sidewall 6 and the second spacer sidewall 7 are respectively in direct contact with the surface of the body portion 811 of the second gate insulating layer 81, that is, the bottom height of the second spacer sidewall 7 is also far lower than the top surface of the mesa structure 812.
It should be noted that the semiconductor device of this embodiment may be used as an intermediate structure in a process of manufacturing a three-dimensional memory.
In summary, in the present invention, by optimizing the process, the etching step of the gate insulating layer on both sides of the gate structure (including the gate 3 and the offset spacer formed on the sidewall of the gate 3) in the high voltage region is adjusted to be between the lightly doped drain processing step and the spacer sidewall forming step, so as to effectively avoid the problem that the oxide spacer sidewall (the first spacer sidewall 6) in the spacer sidewall of the gate structure and the oxide offset spacer in the offset spacer are undesirably etched simultaneously when the bottom gate insulating layer on both sides of the gate structure in the high voltage region is etched in the prior art, thereby forming a defective recess on the oxide spacer sidewall and the top of the oxide offset spacer. In addition, in the invention, the etching step of the grid insulating layer at two sides of the grid structure of the high-voltage area and the process step of lightly doping the drain LDD in the high-voltage area share one MASK MASK, thereby reducing the production cost. Therefore, the invention effectively overcomes various defects in the prior art and has industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (30)
1. A semiconductor device manufacturing method, characterized by comprising:
providing a semiconductor structure comprising a substrate having a first region and a second region, a first gate insulating layer and a second gate insulating layer formed on the first region and the second region, respectively, and a number of discrete gate structures formed on the first gate insulating layer and the second gate insulating layer, respectively;
carrying out light doping leakage treatment on the first region;
thinning the first gate insulation layer positioned at two sides of the gate structure on the first region to form a boss structure on the upper surface of the first gate insulation layer;
the gate structure on the first gate insulating layer is located on the boss structure, and the lower surface of the gate structure on the boss structure completely covers the upper surface of the boss structure.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the forming process of the gate structure comprises:
forming a plurality of discrete gates on the first gate insulating layer and the second gate insulating layer, respectively;
offset spacers are formed on sidewalls of the gate.
3. The method of claim 2, wherein the step of forming the offset spacers on the sidewalls of the gate comprises sequentially forming a first offset spacer and a second offset spacer on the sidewalls of the gate from inside to outside.
4. The method of manufacturing a semiconductor device according to claim 3, wherein the material of the first offset spacers comprises an oxide, and the second offset spacers comprises a nitride.
5. The method for manufacturing a semiconductor device according to claim 2, wherein a material of the gate electrode comprises polysilicon.
6. The method of claim 1, wherein the first gate insulating layer on the first region on both sides of the gate structure is thinned to form a mesa structure on an upper surface of the first gate insulating layer, and further comprising forming spacer sidewalls on sidewalls of the gate structure.
7. The method of claim 6, wherein the step of forming spacer sidewalls on the sidewalls of the gate structure comprises:
and forming a spacing side wall material layer covering the gate structure, and etching to remove the spacing side wall material layer at the top of the gate structure so as to form the spacing side wall on the common side wall of the gate structure and the boss structure on the first region and the side wall of the gate structure in the second region respectively.
8. The method of claim 7, wherein the step of forming a spacer sidewall material layer covering the gate structure, and etching away the spacer sidewall material layer on top of the gate structure to form the spacer sidewall on the common sidewall of the gate structure and the mesa structure in the first region and the sidewall of the gate structure in the second region respectively comprises:
forming a first spacer sidewall material layer overlying the gate structure;
forming a second spacer sidewall material layer overlying the first spacer sidewall material layer;
and etching and removing the second interval side wall material layer and the first interval side wall material layer positioned at the top of the gate structure in sequence so as to form a first interval side wall and a second interval side wall from inside to outside respectively on the common side wall of the gate structure and the boss structure positioned in the first area and the side wall of the gate structure positioned in the second area.
9. The method of claim 8, wherein the material of the first spacer sidewalls comprises an oxide and the material of the second spacer sidewalls comprises a nitride.
10. The method of claim 8, wherein a thickness of the first spacer sidewall material layer is less than a thickness of the mesa structure.
11. The method for manufacturing a semiconductor device according to claim 1, wherein an isolation structure is formed in the substrate, the isolation structure dividing the substrate into the first region and the second region.
12. The method for manufacturing a semiconductor device according to claim 1, wherein a thickness of the first gate insulating layer is larger than a thickness of the second gate insulating layer before the thinning process is not performed.
13. The method for manufacturing a semiconductor device according to claim 1, wherein the first region is a high-voltage region, and the second region is a low-voltage region.
14. The method for manufacturing a semiconductor device according to claim 1, wherein a material of the first gate insulating layer comprises an oxide, and a material of the second gate insulating layer comprises an oxide.
15. The method for manufacturing a semiconductor device according to any one of claims 1 to 14, wherein the step of performing the lightly doped drain process on the first region includes:
forming a patterned mask on the semiconductor structure, wherein the patterned mask exposes the first gate insulating layer and the gate structure formed on the first gate insulating layer;
and carrying out light doping leakage treatment on the first region by utilizing the graphical mask.
16. The method for manufacturing a semiconductor device according to claim 15, wherein the step of thinning the first gate insulating layer on both sides of the gate structure on the first region to form a mesa structure on an upper surface of the first gate insulating layer comprises:
and thinning the first grid insulation layer positioned on the two sides of the grid structure on the first area by using the graphical mask so as to form a boss structure on the upper surface of the first grid insulation layer.
17. A semiconductor device, characterized in that the semiconductor device comprises:
a semiconductor structure, the semiconductor structure comprising:
a substrate having a first region and a second region;
the first grid insulating layer and the second grid insulating layer are respectively positioned on the first area and the second area, and the first grid insulating layer is provided with a main body part and a boss structure which is formed by upwards protruding from the upper surface of the main body part; and
a plurality of discrete gate structures formed on the mesa structure of the first gate insulating layer and on the second gate insulating layer, respectively;
and a lightly doped drain region is formed in the substrate at two sides of the gate structure in the first region, and the lower surface of the gate structure formed above the boss structure completely covers the upper surface of the boss structure.
18. The semiconductor device of claim 17, wherein the gate structure comprises a gate and an offset spacer formed on a sidewall of the gate.
19. The semiconductor device of claim 18, wherein the offset spacers comprise a first offset spacer and a second offset spacer formed on sidewalls of the gate in sequence from inside to outside.
20. The semiconductor device of claim 19, wherein the material of the first offset spacers comprises an oxide and the second offset spacers comprises a nitride.
21. The semiconductor device of claim 18, wherein the material of the gate comprises polysilicon.
22. The semiconductor device according to claim 17, wherein an isolation structure is formed in the substrate, the isolation structure dividing the substrate into the first region and the second region.
23. The semiconductor device of claim 17, wherein a thickness of the first gate structure at the mesa structure is greater than a thickness of the second gate insulation layer.
24. The semiconductor device according to claim 17, wherein the first region is a high-voltage region, and wherein the second region is a low-voltage region.
25. The method for manufacturing a semiconductor device according to claim 17, wherein a material of the first gate insulating layer comprises an oxide, and a material of the second gate insulating layer comprises an oxide.
26. The semiconductor device according to any one of claims 17 to 25, further comprising spacer sidewalls formed on common sidewalls of the gate structure and the mesa structure on the first region and sidewalls of the gate structure on the second region, respectively.
27. The semiconductor device of claim 26, wherein the spacer sidewalls are formed on a common sidewall of the gate structure and the mesa structure in the first region and a first spacer sidewall and a second spacer sidewall of a sidewall of the gate structure in the second region, respectively, in sequence from inside to outside.
28. The semiconductor device of claim 27, wherein a bottom surface of the second spacer sidewall is lower than an upper surface of the mesa structure.
29. The semiconductor device of claim 27, wherein the material of the first spacer sidewalls comprises an oxide and the material of the second spacer sidewalls comprises a nitride.
30. A three-dimensional memory device, wherein the three-dimensional memory device is fabricated using the semiconductor structure of any one of claims 17-29.
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| CN113921386A (en) * | 2020-07-10 | 2022-01-11 | 长鑫存储技术有限公司 | Semiconductor device and method of making the same |
| CN113921524A (en) * | 2021-09-06 | 2022-01-11 | 长江存储科技有限责任公司 | Semiconductor structure and preparation method thereof, integrated circuit, three-dimensional memory and system |
| CN114284211A (en) * | 2021-12-31 | 2022-04-05 | 长江存储科技有限责任公司 | Manufacturing method of semiconductor device and manufacturing method of memory |
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| CN114284211A (en) * | 2021-12-31 | 2022-04-05 | 长江存储科技有限责任公司 | Manufacturing method of semiconductor device and manufacturing method of memory |
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