CN111211778A

CN111211778A - Clock generation circuit, multiphase switching converter and control circuit thereof

Info

Publication number: CN111211778A
Application number: CN202010159872.8A
Authority: CN
Inventors: 徐爱民; 任远程; 周逊伟
Original assignee: Joulwatt Technology Hangzhou Co Ltd
Current assignee: Joulwatt Technology Hangzhou Co Ltd
Priority date: 2020-03-06
Filing date: 2020-03-06
Publication date: 2020-05-29

Abstract

The invention discloses a clock generating circuit, a multi-phase switching converter and a control circuit thereof. A clock generating circuit includes N clock circuits. A first end of the first clock circuit receives a clock input signal, or a Each clock circuit generates a clock input signal, and according to the clock input signal, the second end of the first clock circuit generates a clock output signal; the second to N clock circuits include: The second terminal receives the clock input signal; the second terminal: generates the clock output signal according to the clock input signal of the first terminal; each clock circuit locks the phase of the clock input signal and shifts the phase of the clock input signal by 360/N degrees, Generates a clock output signal. The invention can reliably generate a phase-shifted clock at a lower system clock frequency, and the design is simple.

Description

Clock generation circuit, multiphase switching converter and control circuit thereof

Technical Field

The invention relates to the technical field of power electronics, in particular to a clock generation circuit, a multiphase switch converter and a control circuit thereof.

Background

The phase-shifted clocks are required in many applications, such as in multiphase interleaved parallel switching circuits, where multiple phase-shifted clocks are required. In the prior art, a system generates a high frequency clock, and the high frequency clock performs frequency division to generate a plurality of relatively low frequency phase-shifted clocks. The method needs large working current, and the design of the phase-shifting frequency divider is relatively complex.

Disclosure of Invention

In view of the above, an object of the present invention is to provide a clock generating circuit, a multiphase switching converter and a control circuit thereof, so as to solve the problem in the prior art that a high frequency clock is required for frequency division to generate a phase-shifted clock.

The technical solution of the present invention is to provide a clock generation circuit, which includes N clock circuits,

the first end of the first clock circuit receives a clock input signal, or the first clock circuit generates the clock input signal, and the second end of the first clock circuit generates a clock output signal according to the clock input signal;

the 2 nd to the N th clock circuits include:

a first end: the second end of the upper-level control circuit is connected to receive a clock input signal;

a second end: generating a clock output signal according to the clock input signal of the first end;

each clock circuit carries out phase locking on a clock input signal, and shifts the phase of the clock input signal by 360/N degrees to generate a clock output signal;

wherein N is a natural number of 2 or more.

Optionally, the clock circuit comprises a phase frequency detector, an operational amplifier and a voltage controlled oscillator; the first input end of the phase frequency detector receives a clock input signal, the operational amplifier receives the output voltage of the phase frequency detector, the output voltage of the operational amplifier is connected to the first input end of the voltage-controlled oscillator, and the output end of the voltage-controlled oscillator is connected to the second input end of the phase frequency detector; the voltage-controlled oscillator is formed by connecting K delay units in series, wherein the output of one delay unit is the output of the clock circuit.

Optionally, the operational amplifier is a charge pump; the delay of the delay unit is controlled by the output voltage of the charge pump.

Optionally, the first input terminal of the voltage-controlled oscillator is a supply terminal of the voltage-controlled oscillator.

Optionally, K is set to a minimum of half the least common multiple of N configurable values.

Another technical solution of the present invention is to provide a control circuit of a multiphase switching converter, where the multiphase switching converter includes N switching circuits connected in parallel and corresponding control circuits;

the control circuit of the multiphase switching converter comprises the clock generation circuit according to any one of claims 1 to 4,

the control circuit comprises the clock circuit and a switching signal generating circuit; the switching signal generating circuit generates a switching signal according to the clock input signal;

the first end of the first control circuit is connected to the first end of the first clock circuit, and the second end of the first control circuit is connected to the second end of the clock circuit;

the 2 nd to the N th control circuits include:

a third end: a switching signal is generated in response to a clock input signal, and passes through a driving circuit to drive the switching circuit.

It is a further technical solution of the present invention to provide a multiphase switching converter, a plurality of parallel switching circuits, wherein each switching circuit is connected to a load to provide an output voltage.

Compared with the prior art, the circuit structure and the method have the following advantages that: the phase-shifted clock can be reliably generated at a lower system clock frequency.

Drawings

FIG. 1 is a schematic diagram of a clock generation circuit according to the present invention;

FIG. 2 is a schematic diagram of one embodiment of a clock circuit of the present invention;

FIG. 3 is a schematic diagram of a multiphase switching converter of the present invention;

FIG. 4 is a diagram of a control circuit according to an embodiment of the present invention.

Detailed Description

Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but the present invention is not limited to only these embodiments. The invention is intended to cover alternatives, modifications, equivalents and alternatives which may be included within the spirit and scope of the invention.

In the following description of the preferred embodiments of the present invention, specific details are set forth in order to provide a thorough understanding of the present invention, and it will be apparent to those skilled in the art that the present invention may be practiced without these specific details.

The invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. It should be noted that the drawings are in simplified form and are not to precise scale, which is only used for convenience and clarity to assist in describing the embodiments of the present invention.

Referring to fig. 1, a clock generating circuit according to the present invention includes N clock circuits, a first terminal of a first clock circuit receives a clock input signal CLK1, or a first clock circuit generates a clock input signal, and a second terminal of the first clock circuit generates a clock output signal according to the clock input signal; the 2 nd to the N th clock circuits include: a first end: the second end of the upper-level control circuit is connected to receive a clock input signal; a second end: generating a clock output signal according to the clock input signal of the first end; each clock circuit carries out phase locking on a clock input signal, and shifts the phase of the clock input signal by 360/N degrees to generate a clock output signal; wherein N is a natural number of 2 or more.

The invention can reliably generate the phase-shifting clock under lower system clock frequency.

Referring to fig. 2, the clock circuit includes a phase frequency detector 110, an operational amplifier 120, and a voltage controlled oscillator 130; a first input terminal of the phase frequency detector 110 receives a clock input signal CLKi, the operational amplifier 120 receives an output voltage of the phase frequency detector 110, the output voltage of the operational amplifier 120 is connected to a first input terminal of a voltage controlled oscillator 130, and an output terminal of the voltage controlled oscillator 130 is connected to a second input terminal of the phase frequency detector 120; the voltage-controlled oscillator is formed by connecting K delay units in series, wherein the output of one delay unit is the output CLK (i +1) of the clock circuit. It should be noted that the number K of delay units is designed according to N, and exactly one delay unit has a 360/N difference from the input clock. In one embodiment, N is a fixed value in the system, and will not change in various applications, and K — N may be set. However, in a system, N is not usually a fixed value, but a configurable value. At this point, K may be set to be at least equal to half the least common multiple of the configurable value of N. Since the output of each delay cell is differentially output, naturally with a phase difference of 180 degrees, it is possible to set the kemlest to half the least common multiple of the N configurable values, rather than the least common multiple of the N configurable values.

In one embodiment, the operational amplifier 120 is a charge pump; the delay of the delay unit is controlled by the output voltage of the charge pump. The first input end of the voltage-controlled oscillator is a power supply end of the voltage-controlled oscillator.

In one embodiment, the delay element is an inverter.

Another technical solution of the present invention is to provide a control circuit of a multi-phase switching converter, please refer to fig. 3, in which the multi-phase switching converter includes N parallel switching circuits and corresponding control circuits; the control circuit of the multiphase switching converter comprises a clock generation circuit; referring to fig. 4, the control circuit includes the clock circuit 100 and a switching signal generating circuit 200; the switching signal generating circuit 200 generates a switching signal PWM i according to the clock input signal CLKi; with continued reference to fig. 3, a first terminal of the first control circuit is connected to a first terminal of the first clock circuit, and a second terminal of the first control circuit is connected to a second terminal of the clock circuit; the 2 nd to the N th control circuits include: a first end: the second end of the upper-level control circuit is connected to receive a clock input signal; a second end: generating a clock output signal according to the clock input signal of the first end; a third end: a switching signal is generated in response to a clock input signal, and passes through a driving circuit to drive the switching circuit.

It is a further technical solution of the present invention to provide a multiphase switching converter, a plurality of parallel switching circuits, wherein each switching circuit is connected to a load to provide an output voltage. The number of the switch circuits connected in parallel is N.

Although the embodiments have been described and illustrated separately, it will be apparent to those skilled in the art that some common techniques may be substituted and integrated between the embodiments, and reference may be made to one of the embodiments not explicitly described, or to another embodiment described.

The above-described embodiments do not limit the scope of the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the above-described embodiments should be included in the protection scope of the technical solution.

Claims

1. A clock generation circuit, comprising N clock circuits,

The first end of the first clock circuit receives the clock input signal, or the first clock circuit generates the clock input signal, and according to the clock input signal, the second end of the first clock circuit generates the clock output signal;

The 2nd to Nth clock circuits include:

The first end: connected to the second end of the upper-level control circuit to receive the clock input signal;

The second end: generate a clock output signal according to the clock input signal of the first end;

Each clock circuit phase-locks the clock input signal and shifts the phase of the clock input signal by 360/N degrees to generate a clock output signal;

Among them, N is a natural number greater than or equal to 2.

2. The clock generation circuit according to claim 1, wherein the clock circuit comprises a frequency discriminator, an operational amplifier and a voltage-controlled oscillator; the first input terminal of the frequency discriminator receives a clock input signal, the operational amplifier receives the output voltage of the frequency discriminator and the phase detector, the output voltage of the operational amplifier is connected to the first input end of the voltage controlled oscillator, and the output end of the voltage controlled oscillator is connected to the discriminator The second input end of the frequency discriminator; the voltage-controlled oscillator is composed of K delay units connected in series, and the output of one delay unit is the output of the clock circuit.

3 . The clock generating circuit according to claim 2 , wherein the operational amplifier is a charge pump; and the delay of the delay unit is controlled by an output voltage of the charge pump. 4 .

4 . The clock generating circuit according to claim 2 , wherein the first input terminal of the voltage-controlled oscillator is a power supply terminal of the voltage-controlled oscillator. 5 .

5 . The clock generating circuit according to claim 2 , wherein K is set to be at least half of the least common multiple of a configurable value of N . 6 .

6. A control circuit of a multi-phase switching converter, the multi-phase switching converter comprising N parallel switching circuits and corresponding control circuits;

The control circuit of the multi-phase switching converter includes the clock generating circuit according to any one of claims 1 to 5,

The control circuit includes the clock circuit and a switch signal generation circuit; the switch signal generation circuit generates a switch signal according to the clock input signal;

The 2nd to Nth control circuits include:

The third terminal: according to the clock input signal, the switch signal is generated, and the switch circuit is driven by the drive circuit.

7. A multi-phase switching converter characterized by a plurality of switching circuits connected in parallel, wherein each switching circuit is connected to a load to provide an output voltage, and comprising a control circuit as claimed in claim 6.