CN111200434A - Delay locked loop circuit, method of synchronizing clock signal, and semiconductor memory - Google Patents
Delay locked loop circuit, method of synchronizing clock signal, and semiconductor memory Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means
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- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
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Abstract
本发明提供一种延时锁相环电路、同步时钟信号方法及半导体存储器。延时锁相环电路包括延时链、寄存器、译码器、控制单元、复制延时单元以及鉴相器；延时链用于对输入信号进行延迟；寄存器包括高频工作的时钟频率的设置编码；译码器用于读取设置编码，以得到预估时钟周期；控制单元连接于译码器和延时链之间，用于设置延时链的初始长度；复制延时单元连接延时链，用于产生复制延时信号；鉴相器连接复制延时单元和时钟信号，用于输出比较结果信号；控制单元连接鉴相器，用于沿初始长度继续调整接入延时链的长度。本发明通过读取寄存器内高频工作的时钟频率的设置编码，获取预估时钟周期，从而对延时链的长度进行快速调整，保证电路的可靠性和准确性。
The invention provides a delay phase locked loop circuit, a method for synchronizing clock signals and a semiconductor memory. The delay phase-locked loop circuit includes a delay chain, a register, a decoder, a control unit, a replica delay unit and a phase detector; the delay chain is used to delay the input signal; the register includes the setting of the clock frequency for high frequency operation Encoding; the decoder is used to read the setting code to obtain the estimated clock cycle; the control unit is connected between the decoder and the delay chain to set the initial length of the delay chain; the copy delay unit is connected to the delay chain , used to generate the replica delay signal; the phase detector is connected to the replica delay unit and the clock signal to output the comparison result signal; the control unit is connected to the phase detector to continue adjusting the length of the access delay chain along the initial length. The invention obtains the estimated clock cycle by reading the setting code of the high-frequency operating clock frequency in the register, thereby rapidly adjusting the length of the delay chain and ensuring the reliability and accuracy of the circuit.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuits, in particular to a delay phase-locked loop circuit, a clock signal synchronizing method and a semiconductor memory.
Background
This section is intended to provide a background or context to the embodiments of the invention that are recited in the claims. The description herein is not admitted to be prior art by inclusion in this section.
Since the operating clock frequency of a DDR (Double Data Rate SDRAM) chip changes, a delay pll circuit is required to always lock a clock quickly and accurately when the operating clock frequency changes.
When the working clock frequency is switched between a higher frequency and a lower frequency at will, the working clock period will also vary from picoseconds (ps) to nanoseconds (ns), and suitable delay times need to be set at different working clock frequencies. When the delay phase-locked loop circuit is in a high-frequency working clock, the conditions of overlong delay chain and overhigh power consumption can occur.
Disclosure of Invention
Embodiments of the present invention provide a delay locked loop circuit, a method for synchronizing clock signals, and a semiconductor memory, so as to at least alleviate or solve one or more technical problems in the prior art.
In a first aspect, an embodiment of the present invention provides a delay locked loop circuit, including:
the delay chain is used for inputting a clock signal and outputting a delay signal of the clock signal according to the length of the delay chain;
a register including a setting code reflecting a clock frequency of a high-frequency operation of the memory;
the decoder is connected with the register and is used for reading the setting codes in the register so as to obtain the estimated clock period of the clock signal, wherein the estimated clock period comprises the clock period under the high-speed clock frequency;
the control unit is connected between the decoder and the delay chain and used for setting the initial length of the delay chain according to the pre-estimated clock period so as to adjust the delay time of the delay signal to the clock signal;
the copying delay unit is connected to the output end of the delay chain and used for simulating the fixed delay of a section of path to generate a copying delay signal, and the fixed delay of the path is from the output clock end of the delay phase-locked loop to the clock end of the fixed trigger;
the two input ends of the phase discriminator are respectively connected with the output end of the replica delay unit and the clock signal, and the phase discriminator is used for comparing the phases of the clock signal and the replica delay signal and outputting a comparison result signal;
and the control unit is connected to the output end of the phase discriminator and used for continuously adjusting the length of the access delay chain along the initial length according to the comparison result signal.
In one implementation, the register includes a MR2 mode register.
In an embodiment, the delay chain includes a plurality of delay units connected in series, wherein an input terminal of the first delay unit is connected to the clock signal, and the control unit controls an output terminal of the nth delay unit as an initial output terminal of the delay chain, and sets a length between the input terminal of the first delay unit and the initial output terminal as an initial length.
In one embodiment, when the output of the nth delay unit is used as the initial output, the delay time matches half of the estimated clock period.
In one embodiment, the comparison result signal includes an increase signal, a decrease signal, and an alignment signal;
the control unit is used for: when the increasing signal is received, controlling the delay chain to increase the number of the delay units connected to the delay chain along the initial output end; when the reduction signal is received, controlling the delay chain to reduce the number of the delay units connected to the delay chain along the initial output end; maintaining the number of delay elements that are accessed into the delay chain when receiving the alignment signal.
In one possible embodiment, the high speed clock frequency includes a frequency between 1333Mb/s and 3200 Mb/s.
In a second aspect, an embodiment of the present invention provides a method for synchronizing a clock signal in a delay locked loop circuit, including:
inputting a clock signal into a delay chain, and outputting a delay signal of the clock signal according to the length of the delay chain;
reading a setting code reflecting a high-speed clock frequency range in a register to obtain an estimated clock period of the clock signal, wherein the estimated clock period comprises an estimated clock period under the high-speed clock frequency; and
setting the initial length of the delay chain according to the pre-estimated clock period so as to adjust the delay time of the delay signal to the clock signal;
generating a replica delay signal with the same phase according to the delay clock signal;
comparing the phases of the clock signal and the replica delay signal and outputting a comparison result signal;
and according to the comparison result signal, continuously adjusting the length of the access delay chain along the initial length.
In one embodiment, the delay chain comprises a plurality of delay units connected in series;
the step of setting the initial length of the delay chain according to the pre-estimated clock period comprises:
selecting an input end of a first delay unit to receive the clock signal;
selecting the output end of the Nth delay unit as the initial output end of the delay chain according to the estimated clock period, and taking the length from the input end of the first delay unit to the initial output end as the initial length;
when the output end of the Nth delay unit is used as the initial output end, the delay time is matched with half of the pre-estimated clock period.
In one embodiment, the comparison result signal includes an increase signal, a decrease signal, and an alignment signal;
the step of continuing to adjust the length of the access delay chain along the initial length according to the comparison result signal comprises:
when the increasing signal is received, controlling the delay chain to increase the number of the delay units connected to the delay chain along the initial output end;
when the reduction signal is received, controlling the delay chain to reduce the number of the delay units connected to the delay chain along the initial output end;
maintaining the number of delay elements that are accessed into the delay chain when receiving the alignment signal.
In a third aspect, an embodiment of the present invention provides a semiconductor memory, including the delay locked loop circuit described above.
The embodiment of the invention adopts the technical scheme, and has the following advantages: the high-frequency pre-estimated clock period is obtained by reflecting the setting code of the high-speed clock frequency range in the register, so that the length of a delay chain is reasonably set according to the high frequency, the consumption of a delay phase-locked loop circuit is reduced, and the reliability and the accuracy of the delay phase-locked loop circuit are ensured.
The foregoing summary is provided for the purpose of description only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present invention will be readily apparent by reference to the drawings and following detailed description.
Drawings
In the drawings, like reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily to scale. It is appreciated that these drawings depict only some embodiments in accordance with the disclosure and are therefore not to be considered limiting of its scope.
FIG. 1 is a schematic diagram of a delay locked loop circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a delay chain according to one embodiment of the present invention;
FIG. 3 is a flow chart of a method of synchronizing clock signals according to one embodiment of the present invention;
FIG. 4 is a flow chart of a method of synchronizing clock signals according to another embodiment of the present invention;
FIG. 5 is a flowchart of a method for synchronizing clock signals according to another embodiment of the present invention.
Reference numerals:
110 delay chains;
111 a delay unit;
120 registers;
130 a decoder;
140 a control unit;
150, copying a delay unit;
160 phase detector.
Detailed Description
In the following, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
In a first aspect, an embodiment of the present invention provides a delay locked loop circuit.
Referring to fig. 1, the delay locked loop circuit may include a delay chain 110, a decoder 130, a control unit 140, a replica delay unit 150, and a phase detector 160.
The delay chain 110 may be used to input a clock signal and output a delayed version of the clock signal according to the length of the delay chain 110. The clock frequency is switched during operation of the memory chip. For example, when the DDR4 clock signal is switched from 3200Mb/s to 1333Mb/s in synchronizing clock signals, the length of the delay chain 110 is shortened, the length of the delay chain 110 needs to be adjusted according to the operating clock frequency of the current clock signal, and the circuit consumption wasted by the redundant delay chain 110 is reduced, so as to ensure that the circuit can normally operate.
The memory requires different Column Address Strobe write Latency times (time of CASWRITE Latency, tCWL; where CAS stands for Column Address Strobe, which is collectively referred to as Column Address Strobe) at different operating frequencies. That is, the tCWL may reflect the current operating clock frequency of the memory. the configuration value of the tCWL may be registered in the MR2 mode register. Furthermore, the decoder 130 can predict the current high-speed clock frequency of the clock signal by reading the setting code in the register 120, so as to obtain the current predicted clock period of the clock signal.
The control unit 140 is connected between the decoder 130 and the delay chain 110, and the control unit 140 is configured to set an initial length of the delay chain 110 according to the estimated clock period to adjust a delay time of the delay signal to the clock signal. The length of the delay chain 110 is reasonably adjusted according to the estimated clock period of the clock signal obtained by the decoder 130, so as to quickly and accurately synchronize the clock signal and reduce the circuit power consumption wasted by the redundant delay chain 110.
A replica delay unit 150 is connected to the output of the delay chain 110. The replica delay unit 150 is used for generating a replica delay signal by simulating a fixed delay of one segment. The fixed delay of the path is from the output clock terminal of the delay locked loop to the clock terminal of the fixed flip-flop.
Two input terminals of the phase detector 160 are respectively connected to the output terminal of the replica delay unit 150 and the clock signal, and the phase detector 160 is configured to compare phases of the clock signal and the replica delay signal and output a comparison result signal.
The control unit 140 is connected to an output end of the phase detector 160, and the control unit 140 is configured to adjust the length of the access delay chain 110 with the initial length as a starting point according to the comparison result signal.
In one possible implementation, the high frequency clock may include a frequency between 3200Mb/s and 1333Mb/s, inclusive. Therefore, the high-frequency clock can cover the variation range of the high-frequency working clock commonly used in the DDR, so that the DDR can ensure the normal work of the circuit under different clock frequencies.
In one possible embodiment, referring to fig. 2, the delay chain 110 may include a plurality of delay cells 111 connected in series. The delay unit 111 may be a buffer. The Input (IN) of the first delay unit 111 is connected to the clock signal to receive the clock signal.
The control unit 140 controls the output end of the nth delay unit 111 as the initial output end (START OUT) of the delay chain 110, and outputs a delay signal, where the length from the input end to the initial output end of the first delay unit is the initial length. And adjusts the length of the delay chain 110 starting from the initial output. When the output terminal of the nth delay unit 111 is used as the initial output terminal, the delay time matches half of the estimated clock period, so as to facilitate the fast adjustment of the access length of the delay chain 110, thereby fast and accurately synchronizing the clock signals. Matching includes equaling or differing within a certain range.
Since the estimated clock period is based on the estimated value, inaccurate value, of the current operating clock frequency. Therefore, half of the estimated clock period is used as the initial adjustment position, so that the delay time can be prevented from exceeding the current working clock period, and the power consumption waste caused by the redundancy of the delay unit 111 can be avoided.
Further, the comparison result signal includes an increase signal, a decrease signal, and an alignment signal.
The control unit 140 is configured to receive an increasing signal to control the delay chain 110 to increase the number of delay units 111 connected to the delay chain 110 along the initial output end. The control unit 140 is configured to receive a reduction signal to control the delay chain 110 to reduce the number of delay units 111 connected to the delay chain 110 along the initial output. The control unit 140 is configured to receive an alignment signal to maintain the number of delay units 111 accessing the delay chain 110. Thus, starting from the initial output of the delay chain 110, the number of delay units 111 accessing the delay chain 110 can be adjusted quickly.
In this embodiment, the current working clock cycle of the clock signal is estimated by setting codes in different working clock frequencies by the register 120, so as to set the initial output end of the delay chain 110, and further adjust the length of the delay chain 110 along the initial output end according to the delay time until the phases of the delay signal and the clock signal are the same, so as to quickly synchronize the clock signal and ensure the reliability and accuracy of the circuit.
In a second aspect, an embodiment of the present invention provides a method for synchronizing a clock signal in a delay locked loop circuit. Referring to fig. 3, a method for synchronizing clock signals by a delay locked loop circuit may include:
step S100: the clock signal is input to the delay chain 110, and a delayed signal of the clock signal is output according to the length of the delay chain 110. When the access length of the delay chain 110 is adjusted, the delay time of the clock signal by the delay chain 110 is changed, so as to generate delay signals with different phases.
Step S200: the setting code reflecting the high-speed clock frequency in the register 120 is read to obtain the estimated clock period of the clock signal, wherein the estimated clock period includes the clock period at the high-speed clock frequency.
Step S300: the initial length of the delay chain 110 is set according to the estimated clock period to adjust the delay time of the pair of delay signals.
Step S400: and generating a copy delay signal according to the delay information from the output clock end of the delay phase-locked loop to the clock end of the fixed trigger. The delay information includes a fixed delay of the path.
Step S500: the phases of the clock signal and the replica delay signal are compared, and a comparison result signal is output.
Step S600: the length of the access delay chain 110 is adjusted along the initial length based on the comparison result signal.
In one possible embodiment, the delay chain 110 may include a plurality of delay units 111 connected in series;
referring to fig. 4, the step of setting the initial length of the delay chain 110 according to the predicted clock period in step S300 may include:
step S310: the input of the first delay cell 111 is selected to receive the clock signal.
Step S320: according to the estimated clock period, the output end of the nth delay unit 111 is selected as the initial output end of the delay chain 110, and the length from the input end of the first delay unit to the initial output end is taken as the initial length.
When the output end of the nth delay unit 111 is used as the initial output end, the delay time matches half of the estimated clock period.
In one possible implementation, referring to fig. 3, the method for delaying the synchronization of the clock signal by the pll circuit may further include:
in one possible embodiment, comparing the signals includes increasing the signal, decreasing the signal, and aligning the signal;
referring to fig. 5, the step S600 of continuing to adjust the length of the access delay chain 110 along the initial length according to the comparison result signal includes:
step S610: when receiving the increase signal, the delay chain 110 is controlled to increase the number of delay units 111 connected to the delay chain 110 along the initial output terminal.
Step S620: when receiving the reduction signal, the delay chain 110 is controlled to reduce the number of delay units 111 connected to the delay chain 110 along the initial output.
Step S630: the number of delay elements 111 that are coupled into the delay chain 110 is maintained when the alignment signal is received.
A third aspect of the present invention provides a semiconductor memory. The semiconductor memory includes the delay locked loop circuit as in the above embodiment.
When the frequency of the working clock of the semiconductor memory is changed at will, the delay phase-locked loop circuit can always quickly and accurately adjust the length of the delay chain so as to lock the clock, thereby ensuring the reliability and the accuracy of the semiconductor memory circuit.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive various changes or substitutions within the technical scope of the present invention, and these should be covered by the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; the connection can be mechanical connection, electrical connection or communication; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly above and obliquely above the second feature, or simply meaning that the first feature is at a lesser level than the second feature.
The above disclosure provides many different embodiments, or examples, for implementing different features of the invention. The components and arrangements of the specific examples are described above to simplify the present disclosure. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.
Claims (10)
1. A time delay phase locked loop circuit, comprising:
the delay chain is used for delaying an input clock signal and outputting a delay signal of the clock signal according to the length of the delay chain;
a register including a setting code reflecting a clock frequency of a high-frequency operation of the memory;
the decoder is connected with the register and is used for reading the setting codes in the register so as to obtain the estimated clock period of the clock signal, wherein the estimated clock period comprises the clock period under the high-speed clock frequency;
the control unit is connected between the decoder and the delay chain and used for setting the initial length of the delay chain according to the pre-estimated clock period so as to adjust the delay time of the delay signal to the clock signal;
the copying delay unit is connected to the output end of the delay chain and used for simulating the fixed delay of a section of path to generate a copying delay signal, and the fixed delay of the path is from the output clock end of the delay phase-locked loop to the clock end of the fixed trigger;
the two input ends of the phase discriminator are respectively connected with the output end of the replica delay unit and the clock signal, and the phase discriminator is used for comparing the phases of the clock signal and the replica delay signal and outputting a comparison result signal;
and the control unit is connected to the output end of the phase discriminator and used for continuously adjusting the length of the access delay chain along the initial length according to the comparison result signal.
2. The delay locked loop circuit of claim 1, wherein the register comprises an MR2 mode register.
3. The delay locked loop circuit of claim 1, wherein said delay chain comprises a plurality of delay cells connected in series, wherein an input of a first of said delay cells is connected to said clock signal, and wherein said control unit controls an output of an nth of said delay cells as an initial output of said delay chain, and wherein a length between an input of a first of said delay cells and said initial output is an initial length.
4. The delay locked loop circuit of claim 3, wherein said delay time matches one half of said estimated clock period when the output of the Nth of said delay cells is said initial output.
5. The delay locked loop circuit of claim 3, wherein the comparison result signal comprises an increase signal, a decrease signal, and an alignment signal;
the control unit is used for: when the increasing signal is received, controlling the delay chain to increase the number of the delay units connected to the delay chain along the initial output end; when the reduction signal is received, controlling the delay chain to reduce the number of the delay units connected to the delay chain along the initial output end; maintaining the number of delay elements that are accessed into the delay chain when receiving the alignment signal.
6. The delay locked loop circuit of any one of claims 1 to 5, wherein the high speed clock frequency comprises a frequency between 1333Mb/s and 3200 Mb/s.
7. A method for synchronizing clock signals in a delay locked loop circuit, comprising:
inputting a clock signal into a delay chain, and outputting a delay signal of the clock signal according to the length of the delay chain;
reading a setting code reflecting a high-speed clock frequency range in a register to obtain an estimated clock period of the clock signal, wherein the estimated clock period comprises an estimated clock period under the high-speed clock frequency; and
setting the initial length of the delay chain according to the pre-estimated clock period so as to adjust the delay time of the delay signal to the clock signal;
generating a copy delay signal according to delay information from an output clock end of the delay phase-locked loop to a clock end of the fixed trigger;
comparing the phases of the clock signal and the replica delay signal and outputting a comparison result signal;
and according to the comparison result signal, continuously adjusting the length of the access delay chain along the initial length.
8. The method of claim 7, wherein the delay chain comprises a plurality of delay cells connected in series;
the step of setting the initial length of the delay chain according to the pre-estimated clock period comprises:
selecting an input end of a first delay unit to receive the clock signal;
selecting the output end of the Nth delay unit as the initial output end of the delay chain according to the estimated clock period, and taking the length from the input end of the first delay unit to the initial output end as the initial length;
when the output end of the Nth delay unit is used as the initial output end, the delay time is matched with half of the pre-estimated clock period.
9. The method of claim 8, wherein the comparison result signal includes an increase signal, a decrease signal, and an alignment signal;
the step of continuing to adjust the length of the access delay chain along the initial length according to the comparison result signal comprises:
when the increasing signal is received, controlling the delay chain to increase the number of the delay units connected to the delay chain along the initial output end;
when the reduction signal is received, controlling the delay chain to reduce the number of the delay units connected to the delay chain along the initial output end;
maintaining the number of delay elements that are accessed into the delay chain when receiving the alignment signal.
10. A semiconductor memory comprising a delay locked loop circuit as claimed in any one of claims 1 to 6.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113312864A (en) * | 2021-04-29 | 2021-08-27 | 飞腾信息技术有限公司 | S-shaped configurable delay line, clock structure and clock delay adjusting method |
| CN117095713A (en) * | 2023-08-23 | 2023-11-21 | 上海奎芯集成电路设计有限公司 | Signal phase conversion circuit based on transmission rate |
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| CN113312864A (en) * | 2021-04-29 | 2021-08-27 | 飞腾信息技术有限公司 | S-shaped configurable delay line, clock structure and clock delay adjusting method |
| CN113312864B (en) * | 2021-04-29 | 2023-03-21 | 飞腾信息技术有限公司 | S-shaped configurable delay line, clock structure and clock delay adjusting method |
| CN117095713A (en) * | 2023-08-23 | 2023-11-21 | 上海奎芯集成电路设计有限公司 | Signal phase conversion circuit based on transmission rate |
| CN117095713B (en) * | 2023-08-23 | 2024-03-19 | 上海奎芯集成电路设计有限公司 | Signal phase conversion circuit based on transmission rate |
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