CN111192878A - Preparation method of three-dimensional memory and three-dimensional memory - Google Patents
Preparation method of three-dimensional memory and three-dimensional memory Download PDFInfo
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Abstract
本申请提供一种三维存储器的制备方法及三维存储器。所述制备方法包括：提供半导体结构，所述半导体结构包括衬底、设于所述衬底上的堆叠结构和设于所述堆叠结构上的蚀刻阻挡层；所述半导体结构具有贯穿所述蚀刻阻挡层和所述堆叠结构的栅极隔槽，并在所述栅极隔槽内形成有导电结构；在所述蚀刻阻挡层背向所述堆叠结构的一侧形成连接层；提供蚀刻剂蚀刻所述连接层以形成第一连接孔，所述第一连接孔露出与所述第一连接孔对应的所述导电结构。本申请提供的制备方法解决了三维存储器中的连接孔与其靠近的栅极之间容易短路的问题。
The present application provides a method for preparing a three-dimensional memory and a three-dimensional memory. The manufacturing method includes: providing a semiconductor structure, the semiconductor structure including a substrate, a stack structure provided on the substrate, and an etch stop layer provided on the stack structure; the semiconductor structure has a through-etching structure a barrier layer and a gate separation groove of the stacked structure, and a conductive structure is formed in the gate separation groove; a connection layer is formed on the side of the etching barrier layer facing away from the stacked structure; an etchant etching is provided The connection layer is formed to form a first connection hole, and the first connection hole exposes the conductive structure corresponding to the first connection hole. The preparation method provided by the present application solves the problem of easy short circuit between the connection hole in the three-dimensional memory and its adjacent gate.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a three-dimensional memory and a three-dimensional memory.
Background
The three-dimensional memory is a memory which realizes the storage and the transmission of data in a three-dimensional space and greatly improves the storage capacity of the storage device. The problem of local stress mutation is obvious along with the increase of the number of stacked layers of the conventional three-dimensional memory, so that the connection hole cannot be aligned with the channel hole, and short circuit between the connection hole and a grid electrode close to the connection hole is easily caused in the process.
Disclosure of Invention
The application provides a preparation method of a three-dimensional memory and the three-dimensional memory, and solves the problem that a connecting hole in the three-dimensional memory is easy to be short-circuited with a grid electrode close to the connecting hole.
The embodiment of the application provides a preparation method of a three-dimensional memory, which comprises the following steps:
providing a semiconductor structure, wherein the semiconductor structure comprises a substrate, a stacked structure arranged on the substrate and an etching barrier layer arranged on the stacked structure; the semiconductor structure is provided with a grid electrode separation groove penetrating through the etching barrier layer and the stacking structure, and a conductive structure is formed in the grid electrode separation groove;
forming a connecting layer on one side of the etching barrier layer, which faces away from the stacked structure;
and providing an etchant to etch the connecting layer to form a first connecting hole, wherein the first connecting hole exposes the conductive structure corresponding to the first connecting hole.
Wherein said providing a semiconductor structure comprises:
providing a substrate;
sequentially forming a stacked structure and an etching barrier layer on the substrate;
forming grid isolation grooves on the semiconductor structure, wherein the grid isolation grooves expose the substrate;
and forming a conductive structure in the grid separation groove.
Wherein the "sequentially forming a stack structure and an etch stopper layer on the substrate" includes:
forming an overlapping layer of an insulating layer and a sacrificial layer on the substrate;
an etch stop layer is formed on the overlap layer.
Wherein the semiconductor structure further comprises a protective layer, and the step of forming an etching barrier layer on the overlapping layer comprises the following steps:
and forming a protective layer on the etching barrier layer.
Wherein, between the step of forming gate isolation grooves on the semiconductor structure to expose the substrate and the step of forming conductive structures in the gate isolation grooves, the preparation method comprises the following steps:
forming a protective layer on the part of the grid separation groove, which is exposed out of the etching barrier layer, so as to cover the etching barrier layer;
and replacing the sacrificial layer in the stacked structure with a conductor layer.
Wherein the forming of the protective layer at the portion of the gate spacer where the etch stop layer is exposed so as to cover the etch stop layer comprises:
forming a protective layer on the groove wall of the grid spacer groove, wherein the thickness of the protective layer on the groove wall of the grid spacer groove close to the opening of the grid spacer groove is larger than that of the protective layer on the groove wall far away from the opening of the grid spacer groove;
and removing the protective layer on the groove wall far away from the gate separation groove opening.
Wherein the semiconductor structure further has a channel hole penetrating the etch stop layer and the stack structure, the channel hole having a NAND string formed therein.
Wherein the preparation method comprises the following steps:
simultaneously with the providing an etchant to etch the connection layer to form a first connection hole exposing the conductive structure corresponding to the first connection hole,
and providing an etchant to etch the connection layer to form a second connection hole exposing the NAND string corresponding to the second connection hole, wherein the etch barrier layer is used for blocking the etchant.
Wherein after the first connection hole is formed, a conductive material is filled in the first connection hole.
The application further provides a three-dimensional memory, three-dimensional memory includes substrate, stacked structure, etching barrier layer and articulamentum, stacked structure locates on the substrate, the etching barrier layer with the articulamentum is located in proper order stacked structure dorsad the surface of substrate, three-dimensional memory has and runs through the etching barrier layer with stacked structure's grid separates the groove, be formed with electrically conductive structure in the grid separates the groove, the articulamentum includes the connecting hole, be formed with in the connecting hole and lead electrical pillar, it is connected rather than the electrically conductive structure electricity that corresponds to lead electrical pillar.
Wherein the conductive post is partially located on the etch stop layer.
The three-dimensional memory further comprises a protective layer, wherein the protective layer is arranged between the etching barrier layer and the connecting layer.
The three-dimensional memory further comprises a channel hole penetrating through the etching barrier layer and the stacked structure, a NAND string is formed in the channel hole, the connecting layer comprises a NAND connecting hole, a NAND conductive column is formed in the NAND connecting hole, and the NAND conductive column is electrically connected with the corresponding NAND string and is partially located on the etching barrier layer.
According to the preparation method, the etching barrier layer is arranged between the stacked structure and the connecting layer, so that when the connecting layer is etched by an etchant to form the first connecting hole, the etching barrier layer can effectively prevent the etchant from continuously etching downwards, namely, the etching barrier layer can prevent the first connecting hole from penetrating through the stacked structure, so that a conductive material formed in the first connecting hole is prevented from being electrically connected with a grid electrode in the stacked structure to cause short circuit, the failure of the three-dimensional memory is effectively avoided, and the preparation yield of the three-dimensional memory is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of a partial structure of a conventional three-dimensional memory.
Fig. 2 is a schematic flowchart of a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure.
Fig. 3 is a schematic flow chart of a method for manufacturing the three-dimensional memory provided in fig. 2.
Fig. 4 to 14 are process diagrams of a method for manufacturing the three-dimensional memory provided in fig. 2.
Fig. 15 is a schematic structural diagram of a three-dimensional memory according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic diagram illustrating a partial structure of a conventional three-dimensional memory. As the number of stacked layers of the three-dimensional memory increases, the problem of sudden stress change in the local region of the three-dimensional memory is highlighted, and the connection hole 31 and the gate spacer 14 or the channel hole cannot be aligned. If the deviation of the connection hole 31 from the gate spacer 14 or the trench hole is too large, the etchant may easily etch the surrounding insulating layer 131 in the gate spacer 14 or the trench hole when etching the connection hole 31, thereby exposing the gate layer 132, resulting in the conductive material 33 subsequently filled in the connection hole 31 being electrically connected to the gate layer 132, such that the conductive material 33 is shorted with the gate layer 132, thereby causing the failure of the three-dimensional memory and reducing the yield of the memory.
In view of this, the embodiments of the present application provide a method for manufacturing a three-dimensional memory. Firstly, providing a semiconductor structure, wherein the semiconductor structure comprises a substrate, a stacked structure arranged on the substrate and an etching barrier layer arranged on the stacked structure; the semiconductor structure is provided with a grid electrode separation groove penetrating through the etching barrier layer and the stacking structure, and a conductive structure is formed in the grid electrode separation groove. Then, a connection layer is formed on the side of the etching barrier layer facing away from the stacked structure. Finally, providing an etchant to etch the connection layer to form a first connection hole, wherein the first connection hole exposes the conductive structure corresponding to the first connection hole. The preparation method provided by the application can effectively solve the problem of low quality yield of the three-dimensional memory caused by short circuit in the preparation process.
Referring to fig. 2, fig. 2 is a schematic flow chart illustrating a method for fabricating a three-dimensional memory according to an embodiment of the present disclosure. As shown in fig. 2, the method for manufacturing the three-dimensional memory includes the following steps S110 to S130.
S110: providing a semiconductor structure 10, wherein the semiconductor structure 10 comprises a substrate 11, a stacked structure 12 arranged on the substrate 11 and an etching barrier layer 13 arranged on the stacked structure 12; the semiconductor structure 10 has gate spacers 14 penetrating the etch barrier layer 13 and the stack structure 12, and a conductive structure 15 is formed within the gate spacers 14.
In one possible example, referring to fig. 3, the step S110 of providing the semiconductor structure 10 may include the following steps S111 to S114.
S111: a substrate 11 is provided.
Specifically, referring to fig. 4, the material of the substrate 11 is, for example, Silicon, but it may also be other Silicon-containing substrates 11, such as Silicon-on-insulator (SOI), Silicon germanium (SiGe), Silicon carbide (SiC), etc., and p-type/n-type or deep or shallow various potential wells required by the three-dimensional memory device may be formed in the substrate 11 through ion implantation, etc.
S112: a stack structure 12 and an etch stopper layer 13 are sequentially formed on the substrate 11.
Specifically, referring to fig. 4, an alternating layer of an insulating layer 121 and a sacrificial layer 122 is formed on the substrate 11, and then an etch stop layer 13 is formed on the alternating layer. Specifically, a side of the overlapping layer away from the substrate 11 is a surface of the insulating layer 121 facing away from the substrate 11, and the etch stop layer 13 is formed on the surface. The etch barrier layer 13 is used to block the etching solution from continuing to etch downwards in the subsequent etching process, so as to prevent the short circuit problem caused by over-etching. The insulating layer 121 and the sacrificial layer 122 may be alternately deposited on the surface of the substrate 11 in sequence by chemical vapor deposition, atomic layer deposition, or other suitable deposition method. The etch stop layer 13 may also be formed on the overlap layer using one of the deposition methods described above. In the present embodiment, the insulating layer 121 is made of, for example, silicon oxide, the sacrificial layer 122 is made of, for example, silicon nitride, the etch stop layer 13 is made of silicon nitride, and the etch stop layer 13 may be formed after the stacked layers by a deposition process used for the stacked layers. Of course, in other embodiments, the insulating layer 121 may be made of silicon oxynitride or other materials, the sacrificial layer 122 may be made of amorphous silicon, polysilicon, or aluminum oxide, or other materials may be used for the etch stop layer 13.
In this embodiment, the semiconductor structure 10 further includes a protection layer 16, and the protection layer 16 is formed on the etching stop layer 13. Specifically, the protective layer 16 is formed on a surface of the etch stop layer 13 opposite to the overlap layer. The protective layer 16 serves to protect the etch barrier layer 13 from being damaged during a subsequent process. The material of the protection layer 16 is the same as that of the insulating layer 121, that is, the etch stop layer 13 and the protection layer 16 in this embodiment are the same as those of the sacrificial layer 122 and the insulating layer 121, respectively, and the process for forming the semiconductor structure 10 only needs to continue to alternately deposit two layers on the basis of the original overlapping layers, which saves more process time compared with other materials. Of course, in other embodiments, the material of the protective layer 16 and the material of the insulating layer 121 may be different, and the materials of the etch stop layer 13 and the sacrificial layer 122 may also be different.
S113: gate spacers 14 are formed on the semiconductor structure 10, the gate spacers 14 exposing the substrate 11.
Specifically, referring to fig. 5, the semiconductor structure 10 further has a channel hole 17 penetrating through the etch stop layer 13 and the stack structure 12, the channel hole 17 is formed before the gate spacer 14 is formed, and a NAND string 18 is formed in the channel hole 17.
Referring to fig. 5-7, a gate spacer 14 is then formed on the semiconductor structure 10, wherein the gate spacer 14 penetrates the protective layer 16, the etch stop layer 13 and the overlapping layer and exposes the substrate 11. After the gate spacer 14 is formed, a protective layer 20 is formed on the gate spacer 14 at a portion where the etch barrier layer 13 is exposed to cover the etch barrier layer 13. Specifically, first, the protective layer 20 is formed on the groove wall of the gate isolation groove 14, wherein the thickness of the protective layer 20 on the groove wall of the gate isolation groove 14 close to the opening of the gate isolation groove 14 is greater than the thickness of the protective layer 20 on the groove wall far from the opening of the gate isolation groove 14. The protective layer 20 on the walls of the trenches that are open away from the gate spacers 14 is then removed. Specifically, the isotropic characteristic of wet etching is utilized to remove the protective layer 20 on the trench wall far away from the opening of the gate isolation trench 14, so as to retain the protective layer 20 covering the etching stop layer 13. In this embodiment, the protection layer 20 is silicon dioxide, and the thickness of the protection layer 20 deposited at the position corresponding to the etching barrier layer 13 by the deposition process with poor deposition uniformity is greater than the thickness of the other positions, that is, the thickness of the protection layer 20 deposited at the top corner of the trench wall of the gate isolation trench 14 is greater than the thickness of the other portions, so that when the protection layer 20 of the other portions is removed, the protection layer 20 at the top corner of the trench wall can still remain to partially cover the etching barrier layer 13, so as to protect the etching barrier layer 13 in the subsequent process and prevent the etching barrier layer 13 from being damaged. Of course, in other embodiments, the protective layer 20 may be other materials.
Next, referring to fig. 8-10, before replacing the sacrificial layer 122 in the stacked structure 12 with the conductive layer 123, the exposed portion of the substrate 11 of the gate isolation trench 14 is doped to form a doped region 151. The doped region 151 may be formed using ion implantation or diffusion of a dopant into the substrate 11. The dopant may include any p-type dopant (e.g., boron) or any n-type dopant (e.g., phosphorus). Then, the sacrificial layer 122 in the stacked structure 12 is replaced with a conductor layer 123 to form a stacked structure 12 of alternating insulating layers 121 and conductor layers 123. Sacrificial layer 122 may be removed by a suitable etch process, such as isotropic dry or wet etching. The etch process may have a sufficiently high etch selectivity to the material of sacrificial layer 122 relative to the material of other portions of semiconductor structure 10 to enable the etch process to have a minimal impact on other portions of semiconductor structure 10. While the etch barrier layer 13 is not affected by the etching process in this step, under the protection of the protective layer 20. In some embodiments, the insulating layer 121 may be removed such that there is an empty space (vacuum) between the conductor layers 123. The vacuum space between the conductor layers 123 acts as an insulating layer 121 and can help reduce parasitic capacitance. In this embodiment, the conductor layer 123 may include a conductor material including, but not limited to, W, Co, Cu, Al, doped silicon, silicide, or any combination thereof.
Finally, the protective layer 20 is removed to facilitate the subsequent filling of the gate spacer 14 with the relevant material.
S114: conductive structures 15 are formed in the gate spacers 14.
Specifically, referring to fig. 11, the conductive structure 15 includes a barrier layer 152, a conductive material layer 153, an insulating pillar 154 and a conductive pillar 155. A barrier layer 152 is first formed on the peripheral wall of the gate spacer 14, the barrier layer 152 being made of oxide or any other electrically insulating material, such as silicon oxide. Then, a layer 153 of conductive material is formed on the barrier layer 152 and on the surface of the doped region 151 facing the opening of the gate spacer 14, the layer 153 of conductive material being formed of titanium, a metallic material, or another conductive material. A layer 153 of conductive material is formed by physical vapor deposition on the barrier layer 152 layer and on the surface of the doped region 151 facing the opening of the gate spacer 14. Of course, in other embodiments, the conductive material layer 153 may be formed on the surface of the barrier layer 152 and the doped region 151 facing the opening of the gate spacer 14 by other deposition methods. Finally, an insulating pillar 154 is formed in the gate isolation trench 14, the insulating pillar 154 is disposed in the space surrounded by the conductive material layer 153, a portion of the insulating pillar 154 located in the top of the gate isolation trench 14 is removed, and a conductive pillar 155 is formed in the gate isolation trench 14 where the insulating pillar 154 is removed, and the conductive pillar 155 is flush with the surface of the protection layer 16 facing away from the substrate 11. The insulating posts 154 may be comprised of polysilicon or other insulating material. The conductive pillars 155 may be composed of a metal such as tungsten, or any other conductive material such as Co, Cu, Al, doped silicon, silicide, or any combination thereof. Any suitable electroplating or electroless plating technique may be used to fill the insulating posts 154 and conductive posts 155.
S120: a connection layer 30 is formed on the side of the etch stop layer 13 facing away from the stack 12.
Specifically, referring to fig. 12, the connection layer 30 is formed on the surface of the protection layer 16 opposite to the etching stop layer 13. In this embodiment, the connection layer 30 is made of silicon oxide. That is, the material of the tie layer 30 is the same as the material of the protective layer 16. Of course, in other embodiments, the connecting layer 30 may be formed of other materials.
S130: providing an etchant to etch the connection layer 30 to form a first connection hole 31, the first connection hole 31 exposing the conductive structure 15 corresponding to the first connection hole 31.
Specifically, referring to fig. 13 and 14, the connection layer 30 is dry etched, the connection layer 30 and the protection layer 16 are etched to align with the conductive structure 15, so as to form a first connection hole 31, and the first connection hole 31 exposes the conductive structure 15. Simultaneously with the formation of the first connection hole 31, an etchant is provided to etch the connection layer 30 to form a second connection hole 32, the second connection hole 32 exposing the NAND string 18 corresponding to the second connection hole 32, i.e., the second connection hole 32 also penetrates through the connection layer 30 and the overcoat layer 16. Wherein the etch barrier layer 13 is used to block the etchant. In other words, the first connection hole 31 and the second connection hole 32 are simultaneously formed to simplify the process and improve the production efficiency. After the first and second connection holes 31 and 32 are formed, the first and second connection holes 31 and 32 are filled with a conductive material 33 such that the conductive material 33 in the first connection hole 31 is electrically connected to the conductive structure 15 and the conductive material 33 in the second connection hole 32 is electrically connected to the NAND string 18.
In an ideal state, the first connection hole 31 faces the conductive structure 15, and the second connection hole 32 faces the NAND string 18, however, in an actual situation, due to the fact that the number of layers of the stacked structure 12 in the semiconductor structure 10 is too many, the problem of sudden internal stress change of the semiconductor structure 10 is prominent, so that the first connection hole 31 cannot be aligned well with the conductive structure 15, the second connection hole 32 and the NAND string 18, the first connection hole 31 and the second connection hole 32 can be misaligned in the etching process, the etchant can corrode the insulating layer 121 in the stacked structure 12 around the conductive structure 15 and the NAND string 18, and the conductor layer 123 is exposed, so that after the conductive material 33 is filled into the first connection hole 31 and the second connection hole 32 in a subsequent process, the conductive material 33 and the conductor layer 123 can be electrically connected to cause a short circuit, and the three-dimensional memory part fails. This application is through setting up etch stop layer 13 on stacked structure 12, even first connecting hole 31 and second connecting hole 32 respectively can't aim at with conducting structure 15 and NAND string 18 completely, etch stop layer 13 also can separate the etchant and continue etching downwards to effectively prevent because the circuit short circuit problem that first connecting hole 31 and second connecting hole 32 off normal lead to, effectively improve three-dimensional memory's production yield. Due to the arrangement of the etching barrier layer 13, the alignment error range between the first connection hole 31 and the conductive structure 15 and between the second connection hole 32 and the NAND string 18 is enlarged, in other words, the alignment condition between the first connection hole 31 and the conductive structure 15 and between the second connection hole 32 and the NAND string 18 is not required to be excessively demanding, the production quality of the three-dimensional memory can be achieved, the production efficiency is improved, the production yield of the three-dimensional memory is ensured, and the production cost is effectively reduced.
According to the preparation method, the etching barrier layer 13 is arranged between the stacked structure 12 and the connecting layer 30, so that when the connecting layer 30 is etched by an etchant to form the first connecting hole 31 and the second connecting hole 32, the etching barrier layer 13 can effectively prevent the etchant from continuously etching downwards, that is, the etching barrier layer 13 can prevent the first connecting hole 31 and the second connecting hole 32 from penetrating through the stacked structure 12, so that the conductive material 33 formed in the first connecting hole 31 and the second connecting hole 32 is prevented from being electrically connected with the conductor layer 123 in the stacked structure 12 to cause short circuit, further, the failure of the three-dimensional memory is effectively avoided, and the preparation yield of the three-dimensional memory is improved.
Referring to fig. 15, fig. 15 is a schematic structural diagram of a three-dimensional memory 100 according to an embodiment of the present disclosure. The three-dimensional memory 100 comprises a substrate 11, a stacked structure 12, an etching barrier layer 13 and a connecting layer 30, wherein the stacked structure 12 is arranged on the substrate 11, the etching barrier layer 13 and the connecting layer 30 are sequentially arranged on the surface, opposite to the substrate 11, of the stacked structure 12, the three-dimensional memory 100 is provided with a channel hole 17 and a gate separation groove 14, the channel hole 17 penetrates through the etching barrier layer 13 and the stacked structure 12, a NAND string 18 is formed in the channel hole 17, and a conductive structure 15 is formed in the gate separation groove 14. The connection layer 30 includes a connection hole 31 and a NAND connection hole 32, a conductive pillar 331 is formed in the connection hole 31, and the conductive pillar 331 is electrically connected to its corresponding conductive structure 15 and partially located on the etch stop layer 13. A NAND conductive pillar 332 is formed in the NAND connection hole 32, and the NAND conductive pillar 332 is electrically connected to the corresponding NAND string 18 and partially located on the etch stop layer 13.
In the embodiment, the etching barrier layer 13 is disposed between the stacked structure 12 and the connection layer 30, so that when the connection layer 30 is etched by an etchant to form the connection hole 31 and the NAND connection hole 32, the etching barrier layer 13 can effectively prevent the etchant from continuously etching downwards, that is, the etching barrier layer 13 can prevent the connection hole 31 and the NAND connection hole 32 from penetrating through the stacked structure 12, so that the conductive pillar 331 and the NAND conductive pillar 332 formed in the connection hole 31 and the NAND connection hole 32 are prevented from being electrically connected with the gate in the stacked structure 12 to cause short circuit, thereby effectively preventing the failure of the three-dimensional memory 100 and improving the yield of the three-dimensional memory 100.
In this embodiment, the conductive pillars 331 and the NAND conductive pillars 332 are partially located on the etch stop layer 13. The three-dimensional memory 100 further comprises a protective layer 16, the protective layer 16 is arranged between the etching barrier layer 13 and the connection layer 30, the connection hole 31 and the NAND connection hole 32 penetrate through the connection layer 30 and the protective layer 16, and the protective layer 16 is used for protecting the etching barrier layer 13 so as to prevent the etching barrier layer 13 from being damaged in the preparation process of the three-dimensional memory 100.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims (13)
1. A method for preparing a three-dimensional memory, the method comprising:
providing a semiconductor structure, wherein the semiconductor structure comprises a substrate, a stacked structure arranged on the substrate and an etching barrier layer arranged on the stacked structure; the semiconductor structure is provided with a grid electrode separation groove penetrating through the etching barrier layer and the stacking structure, and a conductive structure is formed in the grid electrode separation groove;
forming a connecting layer on one side of the etching barrier layer, which faces away from the stacked structure;
and providing an etchant to etch the connecting layer to form a first connecting hole, wherein the first connecting hole exposes the conductive structure corresponding to the first connecting hole.
2. The method of manufacturing of claim 1, wherein said providing a semiconductor structure comprises:
providing a substrate;
sequentially forming a stacked structure and an etching barrier layer on the substrate;
forming grid isolation grooves on the semiconductor structure, wherein the grid isolation grooves expose the substrate;
and forming a conductive structure in the grid separation groove.
3. The method of claim 2, wherein the sequentially forming a stack structure and an etch stop layer on the substrate comprises:
forming an overlapping layer of an insulating layer and a sacrificial layer on the substrate;
an etch stop layer is formed on the overlap layer.
4. The method of claim 3, wherein the semiconductor structure further comprises a protective layer, and wherein the forming an etch stop layer over the stack layer comprises:
and forming a protective layer on the etching barrier layer.
5. The method of manufacturing according to claim 4, wherein between said "forming gate spacer grooves on the semiconductor structure, the gate spacer grooves exposing the substrate" and said "forming conductive structures in the gate spacer grooves", the method of manufacturing comprises:
forming a protective layer on the part of the grid separation groove, which is exposed out of the etching barrier layer, so as to cover the etching barrier layer;
and replacing the sacrificial layer in the stacked structure with a conductor layer.
6. The method of claim 5, wherein the forming a protective layer on the portion of the gate spacer exposed by the etch stop layer to cover the etch stop layer comprises:
forming a protective layer on the groove wall of the grid spacer groove, wherein the thickness of the protective layer on the groove wall of the grid spacer groove close to the opening of the grid spacer groove is larger than that of the protective layer on the groove wall far away from the opening of the grid spacer groove;
and removing the protective layer on the groove wall far away from the gate separation groove opening.
7. The method of any one of claims 1-6, wherein the semiconductor structure further has a channel hole through the etch stop layer and the stack structure, the channel hole having a NAND string formed therein.
8. The method of claim 7, comprising:
simultaneously with the providing an etchant to etch the connection layer to form a first connection hole exposing the conductive structure corresponding to the first connection hole,
and providing an etchant to etch the connection layer to form a second connection hole exposing the NAND string corresponding to the second connection hole, wherein the etch barrier layer is used for blocking the etchant.
9. The method of manufacturing according to claim 8, wherein after the first connection hole is formed, a conductive material is filled in the first connection hole.
10. The three-dimensional memory is characterized by comprising a substrate, a stacked structure, an etching barrier layer and a connecting layer, wherein the stacked structure is arranged on the substrate, the etching barrier layer and the connecting layer are sequentially arranged on the surface, back to the substrate, of the stacked structure, the three-dimensional memory is provided with a grid isolating groove penetrating through the etching barrier layer and the stacked structure, a conductive structure is formed in the grid isolating groove, the connecting layer comprises a connecting hole, a conductive column is formed in the connecting hole, and the conductive column is electrically connected with the corresponding conductive structure.
11. The three-dimensional memory according to claim 10, wherein the conductive pillar portion is located on the etch stop layer.
12. The three-dimensional memory of claim 11, further comprising a protective layer disposed between the etch stop layer and the connection layer.
13. The three-dimensional memory according to claim 12, further comprising a channel hole penetrating the etch stop layer and the stack structure, the channel hole having a NAND string formed therein, the connection layer including a NAND connection hole having a NAND conductive pillar formed therein, the NAND conductive pillar being electrically connected to its corresponding NAND string and partially on the etch stop layer.
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