CN111199954A - Manufacturing method of metal layer-insulation layer-metal layer capacitor and memory unit - Google Patents
Manufacturing method of metal layer-insulation layer-metal layer capacitor and memory unit Download PDFInfo
- Publication number
- CN111199954A CN111199954A CN201811365421.9A CN201811365421A CN111199954A CN 111199954 A CN111199954 A CN 111199954A CN 201811365421 A CN201811365421 A CN 201811365421A CN 111199954 A CN111199954 A CN 111199954A
- Authority
- CN
- China
- Prior art keywords
- capacitor
- metal layer
- layer
- dielectric layer
- electrode plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 163
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 123
- 239000002184 metal Substances 0.000 title claims abstract description 123
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 238000009413 insulation Methods 0.000 title description 2
- 238000000034 method Methods 0.000 claims abstract description 43
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000003860 storage Methods 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims description 38
- 238000000576 coating method Methods 0.000 claims description 34
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 32
- 229920002120 photoresistant polymer Polymers 0.000 claims description 32
- 239000011248 coating agent Substances 0.000 claims description 31
- 238000005530 etching Methods 0.000 claims description 15
- 230000008569 process Effects 0.000 claims description 15
- 230000005669 field effect Effects 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- 239000010937 tungsten Substances 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 6
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 claims description 6
- 229910017052 cobalt Inorganic materials 0.000 claims description 6
- 239000010941 cobalt Substances 0.000 claims description 6
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 6
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims description 6
- 239000011733 molybdenum Substances 0.000 claims description 6
- 238000000206 photolithography Methods 0.000 claims description 6
- 229910052707 ruthenium Inorganic materials 0.000 claims description 6
- 229910052715 tantalum Inorganic materials 0.000 claims description 6
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 6
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 230000007704 transition Effects 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- UONOETXJSWQNOL-UHFFFAOYSA-N tungsten carbide Chemical compound [W+]#[C-] UONOETXJSWQNOL-UHFFFAOYSA-N 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- 239000007788 liquid Substances 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 3
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical group [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 3
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 3
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 3
- -1 tungsten nitride Chemical class 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 13
- 238000001259 photo etching Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000003980 solgel method Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/01—Manufacture or treatment
- H10D1/041—Manufacture or treatment of capacitors having no potential barriers
- H10D1/042—Manufacture or treatment of capacitors having no potential barriers using deposition processes to form electrode extensions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
- H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
- H10D1/716—Electrodes having non-planar surfaces, e.g. formed by texturisation having vertical extensions
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
本发明提供一种金属层‑绝缘层‑金属层电容器的制作方法，适于应用于集成电路的片内电容，包括：提供半导体衬底及位于半导体衬底表面的第一介质层；定义电容的下极板区域，刻蚀下极板区域的第一介质层形成若干通孔或沟槽，暴露出半导体衬底表面；定义电容的上极板区域，上极板区域位于下极板区域向外延伸区域，刻蚀上极板区域的第一介质层至某一深度；于下极板区域形成电容下极板；于电容下极板、上极板区域依次形成电容介质层、电容上极板。本发明还提供一种存储单元。本发明形成立体结构的MIM电容器，兼容现有半导体工艺，大大提高了电容器的单位电容，而且避免了量产中的尺寸变化或者对准漂移引起的上下极板之间的潜在短路风险，提高了可靠性。
The present invention provides a method for manufacturing a metal layer-insulating layer-metal layer capacitor, which is suitable for an on-chip capacitor applied to an integrated circuit, including: providing a semiconductor substrate and a first dielectric layer on the surface of the semiconductor substrate; defining a capacitor In the lower plate area, the first dielectric layer of the lower plate area is etched to form a number of through holes or grooves, exposing the surface of the semiconductor substrate; the upper plate area of the capacitor is defined, and the upper plate area is located outside the lower plate area. In the extension area, the first dielectric layer of the upper plate area is etched to a certain depth; the lower electrode plate of the capacitor is formed in the lower electrode plate area; the capacitor dielectric layer and the upper electrode plate of the capacitor are sequentially formed in the area of the lower electrode plate and the upper electrode plate of the capacitor. . The present invention also provides a storage unit. The invention forms a MIM capacitor with a three-dimensional structure, which is compatible with the existing semiconductor technology, greatly improves the unit capacitance of the capacitor, and avoids the potential short circuit risk between the upper and lower plates caused by the dimensional change or alignment drift in mass production, and improves the reliability.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a manufacturing method of a metal layer-insulating layer-metal layer capacitor and a memory unit.
Background
With the increasing demand of the industry for display, the display resolution is continuously improved, but the display driving chip needs to have both high performance and low cost, wherein the power consumption problem is an important key index. After the RAM is integrated, the power consumption can be greatly improved, and the display performance is also improved. Similarly, other analog hybrid integrated circuits have performance requirements for chip speed, data throughput, and the like, and therefore need to incorporate a large-capacity RAM.
The traditional RAM is a 6T/7T SRAM formed by six to seven transistors per unit, but for a high-resolution chip, the cost is greatly increased due to the addition of the 6T/7T SRAM as the storage capacity reaches tens of millions of units, and the customer acceptance is poor. For this reason, various new types of RAMs have been proposed, such as reducing the number of transistors per cell to one or two. Here, referring to the similar technology of DRAM, we can use 1T, 2T SRAM as a new scheme, i.e. each cell only needs one or two transistors plus a large capacitor to achieve the same effect, and accordingly the unit area is only one third of the original area, which brings obvious area advantage. This scheme needs a large-capacity capacitor for support, but the large capacitance value often increases the chip area, offsets the advantages of the transistor reduction, and increases the manufacturing cost. Therefore, how to increase the capacitance (i.e., the capacitance density) per chip area is the key to the success of 1T and 2T SRAMs.
Existing capacitors can be roughly classified into front-end capacitors such as MOS capacitors and PN junction capacitors, and rear-end capacitors such as MIM (metal-insulator-metal) capacitors and MOM (metal-oxide-metal) capacitors. MIM capacitors can provide better frequency and temperature dependent characteristics, and can be formed in inter-level metal interconnect processes to reduce integration difficulty and complexity with CMOS front-end processes, and thus are widely used in various integrated circuits such as analog-logic, analog-digital, mixed-signal, and rf circuits. The conventional MIM capacitor is generally a planar structure, and includes a capacitor bottom plate, a capacitor dielectric layer, and a capacitor top plate, forming a sandwich structure in which an insulating dielectric layer is sandwiched between two metal electrodes.
However, the unit capacitance density of the planar MIM capacitor can only reach 2 fF/mum at most2Since the requirement for high-density capacitance of 1T or 2T SRAM cannot be satisfied, a capacitor having a three-dimensional structure has been proposed. Compared with the traditional flat-plate capacitor, the capacitor unit capacitor with the three-dimensional structure is large, and the requirements of high-density capacitors of 1T and 2T SRAMs cannot be met. However, the structural design and fabrication process of the large capacitor is critical ifBy adopting the traditional flat MIM capacitor manufacturing mode, namely the upper and lower polar plates are etched together, the yield problem and the long-term reliability problem caused by the short circuit of the upper and lower polar plates can be caused, and meanwhile, the existence of the MIM capacitor module in production causes the height difference of a dielectric layer, reduces the photoetching process window and also causes the serious yield problem. The invention reforms the manufacturing process method, thereby eliminating the reliability problem and improving the yield.
Disclosure of Invention
The invention provides a metal layer-insulating layer-metal layer capacitor structure and a manufacturing method thereof, which are suitable for being used as the internal capacitor of a novel random access memory and meet the requirements of high-density capacitors of 1T and 2T SRAMs.
In order to achieve the above object, the present invention provides a method for manufacturing a metal layer-insulator-metal layer capacitor, which is suitable for an on-chip capacitor of an integrated circuit, and comprises the following steps:
providing a semiconductor substrate and a first dielectric layer positioned on the surface of the semiconductor substrate;
defining a lower electrode plate area of the capacitor, etching the first medium layer of the lower electrode plate area to form a plurality of through holes or grooves, and exposing the surface of the semiconductor substrate;
defining an upper electrode plate area of the capacitor, wherein the upper electrode plate area is positioned in an outward extending area of the lower electrode plate area, and etching the first dielectric layer of the upper electrode plate area to a certain depth;
forming a capacitor lower plate in the through hole or the groove of the lower plate area;
and sequentially forming a capacitor dielectric layer and a capacitor upper electrode plate in the capacitor lower electrode plate region and the capacitor upper electrode plate region.
Preferably, the step of forming the capacitor bottom plate in the bottom plate region includes: and depositing a first metal layer on the surface of the first dielectric layer, the side wall and the bottom of the through hole or the groove, filling amorphous carbon or photoresist coating materials in the through hole or the groove, and etching back the first metal layer to form the lower electrode plate of the capacitor.
Preferably, the filling height of the amorphous carbon or photoresist coating material is lower than the surface of the first dielectric layer, so that the edge of the capacitor dielectric layer extends over the edge of the capacitor lower plate to electrically isolate the capacitor upper plate from the capacitor lower plate.
Preferably, the step of defining the lower plate area of the capacitor comprises: and forming a patterned non-shaped carbon or photoresist coating material on the surface of the first dielectric layer, and defining a lower plate area of the capacitor by a photoetching process.
Preferably, the step of defining the upper plate area of the capacitor comprises: and forming a patterned non-shaped carbon or photoresist coating material on the surface of the first dielectric layer, and defining an upper plate area of the capacitor by a photoetching process.
Preferably, the step of defining the upper plate area of the capacitor comprises: and etching the amorphous carbon or photoresist coating material on the first dielectric layer in an oxygen-containing atmosphere by adopting a dry etching mode to transversely enlarge an opening of the amorphous carbon or photoresist coating material and define an upper plate area of the capacitor.
Preferably, the amorphous carbon is prepared by chemical vapor deposition or sol-gel method, and the main component is amorphous carbon.
Preferably, the photoresist coating material comprises photoresist and SOC, is in a liquid state at room temperature, and is prepared by a coating method.
Preferably, the step of defining the upper plate area of the capacitor comprises: and etching the first dielectric layer by adopting an isotropic dry etching mode or a wet etching mode to transversely expand the lower plate area and define the upper plate area of the capacitor.
Preferably, when the first dielectric layer of the upper electrode plate region is etched to a certain depth, the first dielectric layer of the upper electrode plate region is etched to form an L shape or an arc shape.
Preferably, the first dielectric layer of the upper plate region is etched to a certain depth, and the depth does not exceed the depth of the first dielectric layer in the cross section direction.
Preferably, the cross-sectional shape of the through hole or the groove is any one or combination of a triangle, a rectangle, a polygon, a circle and an ellipse.
Preferably, the step of forming the capacitor dielectric layer and the capacitor upper plate comprises:
depositing a second dielectric layer and a second metal layer on the lower electrode plate of the capacitor and the first dielectric layer in sequence;
defining a contact hole or a contact groove area, sequentially etching the second metal layer, the second dielectric layer and the first dielectric layer in the area, exposing the surface of the semiconductor substrate, and forming the contact hole or the contact groove;
filling a third metal layer and a fourth metal layer in the contact hole or the contact groove, the lower electrode plate area and the upper electrode plate area in sequence;
removing the contact hole or the contact groove, the second dielectric layer, the second metal layer, the third metal layer and the fourth metal layer outside the lower polar plate area and the upper polar plate area; the rest second dielectric layer is used as a capacitor dielectric layer, and the rest second metal layer, the rest third metal layer and the rest fourth metal layer in the lower pole plate area and the upper pole plate area form a capacitor upper pole plate.
Preferably, the material of the second dielectric layer is any one or combination of a plurality of high dielectric constant films with the dielectric constant K value larger than 3.9.
Preferably, the high dielectric constant thin film includes any one of zirconium oxide, aluminum oxide, silicon nitride, hafnium oxide, yttrium oxide, silicon oxide, tantalum oxide, lanthanum oxide, and titanium oxide.
Preferably, the first metal layer, the second metal layer, the third metal layer and the fourth metal layer are made of any one or a combination of more of aluminum, aluminum copper alloy, titanium nitride, tantalum nitride, tungsten carbide, copper, titanium, tantalum, cobalt, tungsten, ruthenium, molybdenum and transition element metals.
Preferably, the contact hole or the contact groove, the second dielectric layer, the second metal layer, the third metal layer and the fourth metal layer outside the lower electrode plate area and the upper electrode plate area are removed by adopting back etching or chemical mechanical polishing, and the process is stopped at the first dielectric layer.
Accordingly, the present invention also provides a memory cell comprising: the capacitor comprises a storage capacitor and two field effect transistors or a field effect transistor connected in parallel, wherein the storage capacitor is a capacitor manufactured in any one of the above steps.
Compared with the prior art, the invention has the following technical effects:
according to the manufacturing method of the MIM capacitor with the three-dimensional structure, the yield problem and the long-term reliability problem caused by the short circuit of the upper and lower polar plates due to the adoption of the conventional flat MIM capacitor manufacturing method are avoided, the height difference of the dielectric layer due to the conventional MIM capacitor is eliminated, the photoetching process window is reduced, and the yield is improved. The requirements of large capacitance in 1T and 2T SRAMs such as LCD driving circuits, analog hybrid circuits and the like are met.
Drawings
FIG. 1 is a schematic view of a semiconductor substrate according to a first embodiment of the present invention;
FIG. 2 is a diagram illustrating a lower plate region defined according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating a definition of an upper substrate region according to one embodiment of the present invention;
FIG. 4 is a diagram illustrating the formation of a first metal layer according to one embodiment of the present invention;
FIG. 5 is a schematic view illustrating an amorphous carbon or photoresist coating material filled in a via or a trench according to an embodiment of the present invention;
FIG. 6 is a diagram illustrating a lower plate of a capacitor according to an embodiment of the present invention;
FIG. 7 is a diagram illustrating a second dielectric layer and a second metal layer according to a first embodiment of the present invention;
FIG. 8 is a schematic view of a contact hole or a contact trench according to an embodiment of the present invention;
FIG. 9 is a diagram illustrating the formation of a third metal layer and a fourth metal layer according to a first embodiment of the present invention;
FIG. 10 is a schematic diagram illustrating the formation of a capacitor dielectric layer and a capacitor top plate according to an embodiment of the invention;
FIG. 11 is a diagram illustrating a definition of a bottom plate region according to a second embodiment of the present invention;
FIG. 12 is a diagram illustrating a top plate region defined according to a second embodiment of the present invention;
FIG. 13 is a diagram illustrating a third embodiment of the present invention in which an upper plate region is defined;
FIG. 14 is a diagram illustrating a memory cell according to a fourth embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, but rather construed as limited to the embodiments set forth herein.
Next, the present invention is described in detail by using schematic diagrams, and when the embodiments of the present invention are described in detail, the schematic diagrams are only examples for convenience of description, and the scope of the present invention should not be limited herein.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Example one
The invention provides a method for manufacturing a metal layer-insulating layer-metal layer capacitor, which is suitable for being applied to an on-chip capacitor of an integrated circuit and comprises the following steps:
referring to fig. 1, first, a semiconductor substrate 100, a shallow trench isolation structure 110 located in the semiconductor substrate 100, a first dielectric layer 120 located on the surface of the semiconductor substrate, and a field effect transistor 130 located in the first dielectric layer 120 are provided.
Next, referring to fig. 2, the step of defining the lower plate area of the capacitor includes: a patterned amorphous carbon or photoresist coating (not shown) is formed on the surface of the first dielectric layer 120, and a lower plate region of the capacitor is defined by a photolithography process. And etching the first dielectric layer 120 in the lower plate region by using the patterned amorphous carbon or photoresist coating material as a mask to form a plurality of through holes or trenches 200 exposing the surface of the semiconductor substrate 100. The patterned amorphous carbon or photoresist-like coating material is then removed.
The cross section of the through hole or the groove is in any one or combination of a plurality of shapes of triangle, rectangle, polygon, circle and ellipse, and a plurality of through holes or grooves are placed in a limited space as much as possible, so that the side wall area of the through hole is maximized, the effective electrode area corresponding to the upper electrode plate and the lower electrode plate of the capacitor is increased, and the maximized capacitor density is realized.
Referring again to fig. 3, the step of defining the upper plate area of the capacitor, where the upper plate area is located in the outward extending area of the lower plate area, includes: a patterned amorphous carbon or photoresist coating (not shown) is formed on the surface of the first dielectric layer 120, and a top plate region of the capacitor is defined by a photolithography process. And etching the first dielectric layer 120 of the upper plate region to a certain depth by using the patterned amorphous carbon or photoresist coating material as a mask, and forming an L shape by etching the first dielectric layer 120 of the upper plate region to a certain depth, wherein the depth does not exceed the depth of the first dielectric layer 120 in the cross section direction. The patterned amorphous carbon or photoresist-like coating material is then removed.
Then, forming a capacitor lower plate in the lower plate area; the step of forming the capacitor lower plate in the lower plate area comprises: referring to fig. 4, a first metal layer 210 is deposited on the surface of the first dielectric layer 120, the sidewall of the via hole or trench 200, and the bottom of the via hole or trench 200, referring to fig. 5, an amorphous carbon or photoresist coating material 220 is filled in the via hole or trench 200, the first metal layer 210 is etched back to form a capacitor bottom plate 210, and the amorphous carbon or photoresist coating material 220 is removed. The filling height of the amorphous carbon or photoresist coating material 220 is lower than the surface of the first dielectric layer 120, so that the upper surface of the etched-back first metal layer is lower than the surface of the first dielectric layer, and the edge of the capacitor dielectric layer extends over the edge of the capacitor lower plate to electrically isolate the capacitor upper plate from the capacitor lower plate.
The amorphous carbon is prepared by adopting a chemical vapor deposition or sol method, and the main component is amorphous carbon.
Preferably, the photoresist coating material comprises photoresist and SOC, is in a liquid state at room temperature, and is prepared by a coating method.
Preferably, the material of the first metal layer 210 is any one or more combinations of aluminum, aluminum copper alloy, titanium nitride, tantalum nitride, tungsten carbide, copper, titanium, tantalum, cobalt, tungsten, ruthenium, molybdenum, and transition element metal.
And thirdly, sequentially forming a capacitor dielectric layer and a capacitor upper electrode plate in the capacitor lower electrode plate region and the capacitor upper electrode plate region. The specific steps for forming the capacitor dielectric layer and the capacitor upper plate comprise:
referring to fig. 7, a second dielectric layer 230 and a second metal layer 240 are sequentially deposited on the capacitor bottom plate 210 and the first dielectric layer 120.
Preferably, the material of the second dielectric layer 230 is a high dielectric constant film with a dielectric constant K value greater than 3.9, such as any one or more of zirconium oxide, aluminum oxide, silicon nitride, hafnium oxide, yttrium oxide, silicon oxide, tantalum oxide, lanthanum oxide, and titanium oxide. In a preferred embodiment of the invention, the ZrO is deposited alternately by atomic layer deposition2/Al2O3The hybrid film, as the second dielectric layer 230, can increase the breakdown voltage while ensuring a large K value.
Preferably, the material of the second metal layer is any one or combination of aluminum, aluminum copper alloy, titanium nitride, tantalum nitride, tungsten carbide, copper, titanium, tantalum, cobalt, tungsten, ruthenium, molybdenum and transition element metal.
Referring to fig. 8, a contact hole or contact groove area is defined, and the second metal layer 240, the second dielectric layer 230 and the first dielectric layer 120 in the area are sequentially etched to expose the surface of the semiconductor substrate 100, thereby forming a contact hole or contact groove 300.
Referring to fig. 9, the contact hole or contact groove 300, the lower plate region and the upper plate region are sequentially filled with a third metal layer 310 and a fourth metal layer 320.
Preferably, the material of the third metal layer 310 and the fourth metal layer 320 is any one or more combinations of aluminum, aluminum copper alloy, titanium nitride, tantalum nitride, tungsten carbide, copper, titanium, tantalum, cobalt, tungsten, ruthenium, molybdenum, and transition element metal.
Referring to fig. 10, the contact hole or the contact groove, the second dielectric layer 230 outside the lower plate region and the upper plate region, the second metal layer 240, the third metal layer 310, and the fourth metal layer 320 are removed. Preferably, the contact hole or the contact groove 300, the second dielectric layer 230, the second metal layer 240, the third metal layer 310, and the fourth metal layer 320 outside the lower plate region and the upper plate region are removed by etching back or chemical mechanical polishing, and stop at the first dielectric layer 120.
The remaining second dielectric layer 230 is used as a capacitor dielectric layer, the remaining second metal layer 240, the third metal layer 310 and the fourth metal layer 320 in the lower plate region and the upper plate region form a capacitor upper plate, and the third metal layer and the fourth metal layer in the contact hole or the contact groove are used as conductive plugs. Preferably, the capacitor upper electrode plate and the capacitor lower electrode plate are made of any one or more combinations of aluminum, aluminum-copper alloy, titanium nitride, tantalum nitride, tungsten carbide, copper, titanium, tantalum, cobalt, tungsten, ruthenium, molybdenum and transition element metal.
Example two
Referring to fig. 11, a patterned amorphous carbon or photoresist coating material 400 is formed on the surface of the first dielectric layer 120, a lower plate region of the capacitor is defined, after the first dielectric layer 120 is etched to form a via hole or a trench, the amorphous carbon or photoresist coating material 400 on the first dielectric layer 120 is etched by dry etching in an oxygen-containing atmosphere, so that an opening of the amorphous carbon or photoresist coating material 400 is laterally enlarged to define an upper plate region of the capacitor, as shown in fig. 12.
In the first embodiment, the patterned amorphous carbon or photoresist coating material and the photolithography process need to be formed twice in the lower plate region for defining the capacitor and the upper plate region for defining the capacitor, while in the second embodiment, the patterned amorphous carbon or photoresist coating material and the photolithography process need to be formed only once in the lower plate region and the upper plate region, which can simplify the process and reduce the cost.
EXAMPLE III
Referring to fig. 13, a patterned amorphous carbon or photoresist coating material 400 is formed on the surface of the first dielectric layer 120, a lower plate region of the capacitor is defined, and after the first dielectric layer 120 is etched to form a through hole or a trench, the first dielectric layer 120 is etched by an isotropic dry etching method or a wet etching method, so that the lower plate region is laterally enlarged, and an upper plate region of the capacitor is defined.
In the third embodiment, when the first dielectric layer 120 of the upper plate region is etched to a certain depth, the first dielectric layer 120 of the upper plate region is etched to form an arc shape,
example four
The present invention also provides a memory cell, as shown in fig. 14, including: a storage capacitor C and two field effect transistors (shown in fig. 14 (a)) or a field effect transistor (shown in fig. 14 (b)) connected in parallel, wherein the storage capacitor C is a capacitor manufactured by the method.
The MIM capacitor with the three-dimensional structure is adopted, so that the effective electrode areas corresponding to the upper electrode plate and the lower electrode plate of the capacitor are increased, the capacitance density is improved (the capacitance density of the MIM capacitor with the three-dimensional structure can reach 10-200 times that of the MIM capacitor with the conventional planar structure by adopting different capacitance dielectric layer sizes and materials), a larger capacitance value can be realized on a limited chip area, the requirements of large-capacitance integrated circuits such as an LCD (liquid crystal display) driving circuit, an RFCMOS (radio frequency complementary metal oxide semiconductor) circuit and the like are met, and the MIM capacitor with the three-dimensional structure is suitable.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (18)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811365421.9A CN111199954A (en) | 2018-11-16 | 2018-11-16 | Manufacturing method of metal layer-insulation layer-metal layer capacitor and memory unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811365421.9A CN111199954A (en) | 2018-11-16 | 2018-11-16 | Manufacturing method of metal layer-insulation layer-metal layer capacitor and memory unit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111199954A true CN111199954A (en) | 2020-05-26 |
Family
ID=70746029
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811365421.9A Pending CN111199954A (en) | 2018-11-16 | 2018-11-16 | Manufacturing method of metal layer-insulation layer-metal layer capacitor and memory unit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111199954A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111864063A (en) * | 2020-07-09 | 2020-10-30 | 复旦大学 | Three-dimensional capacitor preparation method |
| CN112382633A (en) * | 2020-11-11 | 2021-02-19 | 无锡拍字节科技有限公司 | Three-dimensional ferroelectric memory and method of manufacturing the same |
| CN114171679A (en) * | 2021-11-30 | 2022-03-11 | 华虹半导体(无锡)有限公司 | Semiconductor device and method of making the same |
| CN114582836A (en) * | 2021-02-12 | 2022-06-03 | 台湾积体电路制造股份有限公司 | Package and method of forming the same |
| CN117059621A (en) * | 2023-10-08 | 2023-11-14 | 荣耀终端有限公司 | Chip and preparation method thereof, electronic equipment |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102142393A (en) * | 2010-01-28 | 2011-08-03 | 中芯国际集成电路制造(上海)有限公司 | Forming method of interconnection structure |
| CN102683176A (en) * | 2012-05-04 | 2012-09-19 | 上海华力微电子有限公司 | Method for improving metal-insulator-metal capacitor reliability and process structure thereof |
| CN102779729A (en) * | 2012-05-04 | 2012-11-14 | 上海华力微电子有限公司 | Process route forming multi-layer step structure |
| CN104681403A (en) * | 2013-11-26 | 2015-06-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor and forming method thereof |
| CN105226046A (en) * | 2015-10-13 | 2016-01-06 | 格科微电子（上海）有限公司 | Metal-insulator-metal capacitor and preparation method thereof |
-
2018
- 2018-11-16 CN CN201811365421.9A patent/CN111199954A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102142393A (en) * | 2010-01-28 | 2011-08-03 | 中芯国际集成电路制造(上海)有限公司 | Forming method of interconnection structure |
| CN102683176A (en) * | 2012-05-04 | 2012-09-19 | 上海华力微电子有限公司 | Method for improving metal-insulator-metal capacitor reliability and process structure thereof |
| CN102779729A (en) * | 2012-05-04 | 2012-11-14 | 上海华力微电子有限公司 | Process route forming multi-layer step structure |
| CN104681403A (en) * | 2013-11-26 | 2015-06-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor and forming method thereof |
| CN105226046A (en) * | 2015-10-13 | 2016-01-06 | 格科微电子（上海）有限公司 | Metal-insulator-metal capacitor and preparation method thereof |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111864063A (en) * | 2020-07-09 | 2020-10-30 | 复旦大学 | Three-dimensional capacitor preparation method |
| CN112382633A (en) * | 2020-11-11 | 2021-02-19 | 无锡拍字节科技有限公司 | Three-dimensional ferroelectric memory and method of manufacturing the same |
| CN114582836A (en) * | 2021-02-12 | 2022-06-03 | 台湾积体电路制造股份有限公司 | Package and method of forming the same |
| US20220262778A1 (en) * | 2021-02-12 | 2022-08-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Deep Partition Power Delivery with Deep Trench Capacitor |
| US11784172B2 (en) * | 2021-02-12 | 2023-10-10 | Taiwan Semiconductor Manufacturing Hsinchu, Co., Ltd. | Deep partition power delivery with deep trench capacitor |
| US12068295B2 (en) | 2021-02-12 | 2024-08-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Deep partition power delivery with deep trench capacitor |
| CN114171679A (en) * | 2021-11-30 | 2022-03-11 | 华虹半导体(无锡)有限公司 | Semiconductor device and method of making the same |
| CN117059621A (en) * | 2023-10-08 | 2023-11-14 | 荣耀终端有限公司 | Chip and preparation method thereof, electronic equipment |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI553885B (en) | Capacitor and manufacturing method thereof | |
| CN111199954A (en) | Manufacturing method of metal layer-insulation layer-metal layer capacitor and memory unit | |
| TWI408798B (en) | Integrated circuit structure | |
| CN111199955A (en) | Manufacturing method of metal layer-insulation layer-metal layer capacitor and memory unit | |
| TWI440140B (en) | Memory capacitor structure and manufacturing method thereof | |
| CN113284898A (en) | Semiconductor device and method of forming the same | |
| US20090078981A1 (en) | Semiconductor memory device and manufacturing method therefor | |
| US20250338514A1 (en) | Deep trench capacitor and method for manufacturing the same | |
| US20100052098A1 (en) | Semiconductor device having storage electrode and manufacturing method thereof | |
| CN110957303A (en) | Capacitor and forming method thereof, semiconductor device and forming method thereof | |
| US11393897B2 (en) | Capacitor structures for memory and method of manufacturing the same | |
| US6432794B1 (en) | Process for fabricating capacitor | |
| KR20040006743A (en) | method for fabricating storage capacitor in semiconductor memory device and structure therefore | |
| US10056448B2 (en) | Coplanar metal-insulator-metal capacitive structure | |
| KR100521988B1 (en) | Semiconductor device having a capacitor formed using nano structures and Method for manufacturing the same | |
| CN100338759C (en) | Method for forming capacitor and capacitor | |
| WO2021254064A1 (en) | Multilayer capacitor and manufacturing method therefor | |
| TW546776B (en) | Method of forming contact | |
| CN105304609B (en) | Metal layer-insulating layer-metal layer capacitor and manufacturing method thereof | |
| US6646299B2 (en) | Integrated circuit configuration having at least two capacitors and method for manufacturing an integrated circuit configuration | |
| US5783848A (en) | Memory cell | |
| CN115643751B (en) | Semiconductor structure and preparation method thereof | |
| CN113299651B (en) | Semiconductor structure preparation method and semiconductor structure | |
| KR20060092643A (en) | Semiconductor memory device and manufacturing method thereof | |
| CN115458682A (en) | Semiconductor device and method for manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200526 |