CN111198316A - Through silicon via detection circuit and method, integrated circuit - Google Patents
Through silicon via detection circuit and method, integrated circuit Download PDFInfo
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- CN111198316A CN111198316A CN201811367326.2A CN201811367326A CN111198316A CN 111198316 A CN111198316 A CN 111198316A CN 201811367326 A CN201811367326 A CN 201811367326A CN 111198316 A CN111198316 A CN 111198316A
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Abstract
本公开是关于一种硅通孔检测电路及检测方法、集成电路，所述硅通孔检测电路包括：输入模块和比较模块，输入模块包括第一开关单元，控制端连接第一检测控制信号，第一端连接第一电源端，第二端连接硅通孔的第一端，用于响应第一检测控制信号而导通将第一电源信号传输至硅通孔的第一端；比较模块第一输入端连接硅通孔的第二端，第二输入端连接参考信号，用于比较硅通孔第二端的信号和参考信号。通过第一检测控制信号控制第一开关单元导通，将第一开关单元第一端的第一电源信号经过和第一开关单元第二端连接的硅通孔传输至比较模块的第一输入端，比较模块的第二输入端输入参考信号实现了硅通孔连通性的检测，结构简单，适用于大规模集成电路。
The present disclosure relates to a TSV detection circuit, a detection method, and an integrated circuit. The TSV detection circuit includes an input module and a comparison module, the input module includes a first switch unit, and a control terminal is connected to a first detection control signal, The first end is connected to the first power supply end, and the second end is connected to the first end of the TSV, and is used to turn on and transmit the first power signal to the first end of the TSV in response to the first detection control signal; An input terminal is connected to the second terminal of the TSV, and the second input terminal is connected to the reference signal, and is used for comparing the signal at the second terminal of the TSV with the reference signal. The first switch unit is controlled to be turned on by the first detection control signal, and the first power supply signal at the first end of the first switch unit is transmitted to the first input end of the comparison module through the through silicon via connected to the second end of the first switch unit , the second input terminal of the comparison module inputs the reference signal to realize the detection of the connectivity of the through silicon hole, the structure is simple, and it is suitable for large-scale integrated circuits.
Description
Technical Field
The disclosure relates to the technical field of integrated circuits, in particular to a through silicon via detection circuit and method and an integrated circuit.
Background
With the development and progress of the technology, the 3D chip is more and more widely used, and the 3D chip realizes the connection of the multilayer Silicon chip Through a Through-Silicon via (TSV). TSV is prone to failure in the manufacturing and binding processes, and TSV failure can affect the performance of the 3D chip.
At present, for a 3D integrated circuit with a small number of TSVs, an interposer is not usually disposed in a stack layer thereof, and for a 3D integrated circuit with a large number of TSVs, an interposer is usually disposed in a stack structure. The multilayer stack communicates through the TSV interconnections, but the TSVs are prone to failure during the manufacturing and binding processes, and therefore the connectivity of the TSVs needs to be detected.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The invention aims to provide a through silicon via detection circuit, a through silicon via detection method and an integrated circuit, and further detect connectivity of a through silicon via in a 3D integrated circuit.
According to a first aspect of the present disclosure, there is provided a through silicon via detection circuit, comprising:
the input module comprises a first switch unit, a control end is connected with a first detection control signal, a first end is connected with a first power end, a second end is connected with a first end of the through silicon via, and the input module is used for responding to the first detection control signal and conducting transmission of the first power signal to the first end of the through silicon via;
and the first input end of the comparison module is connected with the second end of the through silicon via, and the second input end of the comparison module is connected with the reference signal and is used for comparing the signal of the second end of the through silicon via with the reference signal.
According to an embodiment of the present disclosure, the input module is disposed on a first chip layer, the comparison module is disposed on a second chip layer, and the first chip layer and the second chip layer are connected through a through-silicon via.
According to an embodiment of the present disclosure, N input modules are disposed on the first chip layer, each of the N input modules is correspondingly connected to a first end of a tsv string, a second end of the tsv string is connected to a first input end of the comparison module, and the tsv string includes a plurality of serial tsv's.
According to an embodiment of the present disclosure, the comparing module includes:
and the first input end of each of the N comparison units is respectively connected with the second end of a through silicon via string, and the second input ends of the N comparison units are connected with the reference signal.
According to an embodiment of the present disclosure, the through silicon via detection circuit further includes:
an output module, comprising:
the trigger is connected with an output control signal, a clock signal end and a first node and used for responding to a clock signal and transmitting the output control signal to the first node;
the second switch unit is connected with the second end of the silicon through hole string, the first node and the first input end of the comparison module and used for responding to the signal output by the trigger to conduct so as to transmit the signal of the second end of the silicon through hole string to the first input end of the comparison module;
according to an embodiment of the present disclosure, the through silicon via detection circuit includes:
the first end of the second switch unit of each output module in the N output modules is respectively connected with the second end of a silicon through hole string, the second end of the second switch unit of each output module in the N output modules is connected with the first input end of the comparison module, the N output modules are arranged according to the sequence of the silicon through hole strings correspondingly connected with the N output modules, and the output end of the trigger in the previous output module is connected with the input end of the trigger in the next output module;
the comparison module comprises:
and the second ends of the N second switch units are connected to the first input end of the comparison unit, and the second input end of the comparison unit is connected to the reference signal.
According to an embodiment of the present disclosure, the through silicon via detection circuit includes:
the first end of the second switch unit of each output module in the N output modules is respectively connected with the second end of a silicon through hole string, the second end of the second switch unit of each output module in the N output modules is connected with the first input end of the comparison module, and the input ends of the triggers in the N output modules are all connected with output control signals;
the comparison module comprises:
the second ends of the N second switch units are respectively connected with the first input ends of the corresponding comparison units, and the second ends of the N comparison units are connected with the reference signal.
According to an embodiment of the present disclosure, the input module further includes:
and the third switch unit is connected with a second detection control signal at a control end, connected with the second end of the first switch unit at a first end, and connected with the first end of the through silicon via at a second end, and used for responding to the second detection control signal to conduct and transmit the signal of the second end of the first switch unit to the first end of the through silicon via.
According to an embodiment of the present disclosure, the through silicon via detection circuit includes:
m' N input modules, wherein each input module is connected with the first end of one through silicon via;
m' N through silicon vias form N through silicon via strings, each through silicon via string is provided with M through silicon vias connected in series, and the second end of each through silicon via string is connected with an output module;
the signal input end of the silicon through hole string is a first end, and the signal output end of the silicon through hole string is a second end.
According to an embodiment of the present disclosure, the through silicon via detection circuit further includes:
and the selection module is used for transmitting the first detection control signal to the control end of the first switch unit on one of the M chip layers according to the selection control signal and transmitting the second detection control signal to the control end of the third switch unit corresponding to one of the N through silicon via strings.
According to an embodiment of the present disclosure, the through silicon via detection circuit further includes:
one end of the first detection silicon through hole is connected with the first detection control signal output end of the selection module, and the other end of the first detection silicon through hole is connected with the control end of the first switch unit;
and one end of the second detection silicon through hole is connected with the second detection control signal output end of the selection module, and the other end of the second detection silicon through hole is connected with the control end of the third switch unit.
According to an embodiment of the present disclosure, the through silicon via detection circuit includes:
the first ends of the M first detection through silicon vias are connected with the control ends of the first switch units in a chip layer;
the selection module transmits a first detection control signal to the second end of the first detection through silicon via according to a selection control signal.
According to an embodiment of the present disclosure, the through silicon via detection circuit includes:
the first end of each second detection through silicon via is connected with the control ends of the plurality of third switch units corresponding to one through silicon via string;
and the selection module transmits the second detection control signal to a second end of the second detection through silicon via according to a selection control signal.
According to an embodiment of the present disclosure, the comparing module and the output module are disposed on a substrate chip layer of an integrated circuit.
According to an embodiment of the present disclosure, the comparing module and the output module are disposed on a top chip layer of the integrated circuit, and the top chip layer is a layer of the plurality of chip layers that is farthest from the base chip layer.
According to a second aspect of the present disclosure, there is provided a through silicon via detection method, including:
the first switch unit is conducted by utilizing the first detection control signal, and the first power supply signal is transmitted to the first input end of the comparison module through the first switch unit and the through silicon via;
transmitting a reference signal to a second input of the comparison module;
and comparing the signals input by the first input end and the second input end through the comparison module to judge whether the through silicon via has a fault.
According to a third aspect of the present disclosure, an integrated circuit is provided, which includes the through silicon via detection circuit described above.
The utility model provides a through-silicon-via detection circuitry, through the first switch unit of first detection control signal control switch on, the first power signal of the first end of first switch unit transmits the first input of comparison module through the through-silicon-via who is connected with first switch unit second end, reference signal is input to the second input of comparison module, input signal through the first input of comparison module and second input, if the signal of the first input of comparison module and the input of second input is different then this through-silicon-via is the trouble through-silicon-via, the detection of through-silicon-via connectivity has been realized, and simple structure is applicable to large-scale integrated circuit.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The above and other features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.
FIG. 1a is a schematic diagram of a non-faulty TSV;
FIG. 1b is a schematic diagram of a failed TSV of a hole;
FIG. 1c is a schematic diagram of a leakage failure TSV;
fig. 2 is a schematic diagram of a first through-silicon-via detection circuit provided in an exemplary embodiment of the present disclosure;
fig. 3 is a schematic diagram of a second through-silicon-via detection circuit provided in an exemplary embodiment of the present disclosure;
fig. 4 is a schematic diagram of a third through silicon via detection circuit provided in an exemplary embodiment of the present disclosure;
fig. 5 is a schematic diagram of a fourth through silicon via detection circuit provided in an exemplary embodiment of the present disclosure;
fig. 6 is a schematic diagram of a fifth through silicon via detection circuit provided in an exemplary embodiment of the present disclosure;
fig. 7 is a schematic diagram of a sixth through silicon via detection circuit provided in an exemplary embodiment of the present disclosure;
fig. 8 is a schematic diagram of a seventh through silicon via detection circuit provided in an exemplary embodiment of the present disclosure;
fig. 9 is a schematic diagram of an eighth through silicon via detection circuit provided in an exemplary embodiment of the present disclosure;
fig. 10 is a schematic diagram of a ninth through silicon via detection circuit provided in an exemplary embodiment of the present disclosure;
FIG. 11 is a schematic diagram of an input module provided in an exemplary embodiment of the present disclosure;
FIG. 12 is a schematic diagram of an output module provided in an exemplary embodiment of the present disclosure;
FIG. 13 is a schematic diagram of a selection module provided in an exemplary embodiment of the present disclosure;
fig. 14 is a flowchart of a through silicon via detection method according to an exemplary embodiment of the present disclosure.
In the figure:
100. an input module; 110. a first switch unit; 120. a third switching unit; 200. a comparison module; 300. a through silicon via; 400. an output module; 410. a trigger; 420. a second switching unit; 500. a selection module; 600. a first detection through silicon via; 700. and a second detecting through silicon via.
VDD, a first power supply signal; vref, reference signal; DCS1, a first detection control signal; DCS2, a second detection control signal; CLK, a clock signal; and the OCS outputs a control signal.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals denote the same or similar parts in the drawings, and thus, a repetitive description thereof will be omitted.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the embodiments of the disclosure can be practiced without one or more of the specific details, or with other methods, components, materials, devices, steps, and so forth. In other instances, well-known structures, methods, devices, implementations, materials, or operations are not shown or described in detail to avoid obscuring aspects of the disclosure.
The block diagrams shown in the figures are functional entities only and do not necessarily correspond to physically separate entities. That is, these functional entities may be implemented in the form of software, or in one or more software-hardened modules, or in different networks and/or processor devices and/or microcontroller devices.
In the related art, a non-failed TSV is shown in fig. 1a, and typically, a TSV may have a hole failure as shown in fig. 1b or a leakage failure as shown in fig. 1 c. The signal passing through the TSV changes back when the TSV has a hole or a leakage fault.
The exemplary embodiment of the present disclosure first provides a through silicon via detection circuit, as shown in fig. 2, the through silicon via detection circuit includes an input module 100 and a comparison module 200; the input module 100 includes a first switch unit 110 having a control terminal connected to a first detection control signal DCS1 terminal, a first terminal connected to a first power terminal, and a second terminal connected to a first terminal of the through-silicon via, for turning on transmission of a first power signal VDD to the first terminal of the through-silicon via in response to a first detection control signal DCS 1; the first input terminal of the comparing module 200 is connected to the second terminal of the tsv, and the second input terminal is connected to the reference signal for comparing the signal at the second terminal of the tsv with the reference signal Vref.
The comparing module 200 is used to compare the reference signal Vref with the signal flowing through the through silicon via, and in practical applications, the voltage of the first power signal VDD and the parameter of the first switch unit 110 may be adjusted so that the signal input into the through silicon via is the same as the reference signal Vref. After passing through the through-silicon via, the signal input to the through-silicon via is input to the first input terminal of the comparison module 200, and the second input module 100 of the comparison module 200 is input to the second input terminal of the comparison module 200. The comparison module 200 compares signals input by the first input terminal and the second input terminal, and if the signals are the same, the through silicon via does not have a fault, and if the signals are different, the through silicon via has a fault. Wherein, when the difference between the signals input by the first input terminal and the second input terminal of the comparing module 200 is within the preset range, the signals input by the first input terminal and the second input terminal of the comparing module 200 can be considered to be the same.
The through-silicon vias described in the embodiments of the present disclosure may be through-silicon vias that communicate with adjacent chip layers, or may be serial through-silicon via strings that connect chip layers that are not adjacent to each other, which is not specifically limited in the embodiments of the present disclosure.
The through silicon via detection circuit provided by the disclosure controls the conduction of the first switch unit 110 through the first detection control signal DCS1, the first power supply signal VDD of the first end of the first switch unit 110 is transmitted to the first input end of the comparison module 200 through the through silicon via connected with the second end of the first switch unit 110, the reference signal Vref is input at the second input end of the comparison module 200, the input signals are input through the first input end and the second input end of the comparison module 200, if the signals input by the first input end and the second input end of the comparison module 200 are different, the through silicon via is a fault through silicon via, the detection of the connectivity of the through silicon via is realized, the structure is simple, and the through silicon via detection circuit is suitable for a large-scale integrated circuit.
Since the through-silicon vias are used to connect different chip layers, the input module 100 is disposed on a first chip layer, the comparison module 200 is disposed on a second chip layer, and the first chip layer and the second chip layer are connected through the through-silicon vias.
As shown in fig. 3, when N through silicon vias are disposed on a chip layer, N input modules 100 may be disposed on the chip layer, each input module 100 in the N input modules 100 is correspondingly connected to a first end of a through silicon via string, a second end of the through silicon via string is connected to a first input end of the comparison module 200, and the through silicon via string includes a plurality of through silicon vias connected in series.
Accordingly, the comparing module 200 may include: and the first input end of each of the N comparison units is respectively connected with the second end of a silicon through hole string, and the second input ends of the N comparison units are connected with a reference signal.
Further, as shown in fig. 4, the through silicon via detection circuit further includes: an output module 400, wherein the output module 400 is disposed between the tsv and the comparison module 200, as shown in fig. 12, the output module 400 may include a flip-flop 410 and a second switch unit 420; the flip-flop 410 is connected to the output control signal OCS terminal, the clock signal CLK terminal, and the first node, and configured to transmit the output control signal OCS to the first node in response to the clock signal CLK; the second switch unit 420 is connected to the second end of the tsv string, the output end of the flip-flop 410, and the first input end of the comparison module 200, and is turned on in response to the signal output by the flip-flop 410 to transmit the signal of the second end of the tsv string to the first input end of the comparison module 200.
The comparison module 200 and the output module 400 are arranged on a substrate chip layer of the integrated circuit; or, the comparing module 200 and the output module 400 are disposed on a top chip layer of the integrated circuit, where the top chip layer is a layer of a plurality of chip layers that is farthest from the substrate chip layer. That is, the second chip layer may be a base layer or a top layer of the 3D integrated circuit. When the second chip layer is a substrate layer of the 3D integrated circuit, that is, the comparison module 200 is located on the substrate layer, the through-silicon via detection is supported from bottom to top. When the second chip layer is the top layer of the 3D integrated circuit, that is, the comparison module 200 is located on the top layer, the top-down detection of the through silicon vias is supported.
The flip-flop 410 transmits the output control signal OCS to the control terminal of the second switching unit 420 under the control of the clock signal CLK to turn on the second switching unit 420. The second switch unit 420 transmits the signal of the second end of the tsv to the first input terminal of the comparison module 200. The input terminal of the flip-flop 410 may be connected to an and gate, two input terminals of the and gate respectively input the output control signal OCS and the detection enable signal EN, and when signals are input at two ends of the and gate, the output control signal OCS is input to the flip-flop 410.
Further, as shown in fig. 5, when the tsv detection circuit includes N input modules 100, the tsv detection circuit may further include N output modules 400, a first end of the second switch unit 420 of each output module 400 of the N output modules 400 is respectively connected to a second end of a tsv string, and a second end of the second switch unit 420 of each output module 400 of the N output modules 400 is connected to a first input end of the comparison module 200.
In a possible implementation manner provided by the embodiment of the present disclosure, as shown in fig. 6 and fig. 9, the comparing module 200 may include a comparing unit, where second terminals of the N second switching units 420 are connected to a first input terminal of the comparing unit, and a second input terminal of the comparing unit is connected to the reference signal. At this time, the second end of the second switch unit of each of the N output modules in the through silicon via is connected to the first input end of the comparison module, the N output modules are arranged according to the sequence of the through silicon via strings to which the N output modules are correspondingly connected, the output end of the trigger in the previous output module is connected to the input end of the trigger in the next output module, and the input end of the trigger of the first output module in the output module sequence is connected to the output control signal. Through the scan chain formed by the flip-flops 410 in the plurality of output modules, the scan chain is controlled by the clock signal CLK to sequentially output the output control signal OCS to control the conduction of a second switch unit 420, the signal of the through silicon via corresponding to the second switch unit 420 is transmitted to the first input end of the comparison module 200, and the connectivity of the through silicon via is sequentially detected. The number of comparison units in the circuit is reduced, the circuit structure is simplified, and the cost is saved.
In a possible implementation manner provided by the embodiment of the present disclosure, as shown in fig. 5 and 7, the comparing module 200 includes: the second ends of the N second switch units 420 are respectively connected to the first input end of a comparison unit, the second ends of the N comparison units are connected to the reference signal, and the input ends of the flip-flops in the N output modules are all connected to the output control signal. Each output module is correspondingly connected with a comparison unit, so that the detection result is visual, the follow-up analysis is facilitated, and the control is simple.
Further, as shown in fig. 11, the input module 100 further includes: and a third switching unit 120 having a control terminal connected to the second detection control signal DSC2 terminal, a first terminal connected to the second terminal of the first switching unit 110, and a second terminal connected to the first terminal of the through-silicon via, for turning on the signal transmission from the second terminal of the first switching unit 110 to the first terminal of the through-silicon via in response to the second detection control signal. When the first switching unit 110 and the third switching unit 120 are simultaneously turned on, the first power signal VDD is input to the through silicon via.
In practical applications, a 3D integrated circuit usually includes multiple stacked layers, and the adjacent stacked layers need to communicate with each other through a plurality of through-silicon vias. As shown in fig. 7, in order to test a test integrated circuit including M stacked layers each including N through-silicon vias, the through-silicon via test circuit may include: m' N input modules 100, each input module 100 connected to a first end of a through-silicon-via; the M' N through silicon holes form N through silicon hole strings, each through silicon hole string is provided with M through silicon holes connected in series, and the second end of each through silicon hole string is connected with an output module; the signal input end of the silicon through hole string is a first end, and the signal output end of the silicon through hole string is a second end.
The comparison module 200 may be disposed on a base layer or a top layer of the 3D integrated circuit. One or more of the strings of through silicon vias may be detected by controlling the supply of the first detection control signal DCS1 to the first switch cell 110 in one or more of the M stacked layers, the supply of the second detection control signal DSC2 to one or more corresponding third switch cells 120 in the N strings of through silicon vias, and thus, a part of the through silicon vias in the one string of through silicon vias may be selected for detection.
For example, for a 3D integrated circuit having a four-layer stacked structure, four through-silicon vias are formed in adjacent stacked layers, the input module 100 is connected to the upper end of each through-silicon via, the output module 400 and the comparison module 200 are located on the base layer, and the first detection control signal DCS1 can be output to the control end of the first switch unit 110 in the third stacked layer, and the second detection control signal DSC2 can be transmitted to the third switch unit 120 corresponding to the second row of through-silicon vias, where the through-silicon vias between the third layer and the fourth layer in the second row of through-silicon via strings are detected.
Further, as shown in fig. 8, the comparison modules 200 may be disposed on the substrate chip layer and the top chip layer of the integrated circuit, that is, the comparison modules 200 are connected to both ends of the tsv string, a first input end of the comparison module on the substrate chip layer is connected to one end of the tsv string through the output module 400, a first input end of the comparison module 200 on the top chip layer is connected to the other end of the tsv string through the fourth switching unit, the fourth switching unit responds to the control signal to transmit a signal on the tsv string to the comparison module 200, and second input ends of all the comparison modules 200 are connected to the reference signal. At this time, the test from top to bottom or the test from bottom to top can be selected according to the test requirement, the comparison module 200 on the substrate chip layer is used for the test from top to bottom, and the comparison module 200 on the top chip layer is used for the test from bottom to top.
To transmit the first detection control signal DCS1 to the control terminal of the first switching unit 110 to be corresponded, and the second detection control signal DSC2 to the control terminal of the corresponding third switching unit 120. As shown in fig. 10 and 13, the through silicon via detection circuit further includes: a selection module 500 for transmitting the first detection control signal DCS1 to a control terminal of the first switch cell 110 on one of the M stacked layers and transmitting the second detection control signal DSC2 to a control terminal of the third switch cell 120 corresponding to one of the N tsv strings according to a selection control signal.
The selection module 500 may include a first selection unit and a second selection unit, the first selection unit being configured to select a control end of the first selection unit transmitting the first detection control signal DCS1 to one of the plurality of stacked layers; the second selection unit is configured to select to transmit the second detection control signal DSC2 to the control terminal of the third switching unit 120 corresponding to one of the plurality of tsv strings.
The first selection unit and the second selection unit may be selectors, the input signal is transmitted to one of the plurality of output terminals by selecting the control signal, each output terminal of the selector in the first selection unit may be connected to an and gate, and the other input terminal of the and gate is connected to the detection enable signal EN.
For example, the through silicon vias in the 3D integrated circuit may be numbered according to the stack layers where the through silicon vias are located and the positions of the through silicon vias in each layer, for example, the through silicon vias may be numbered as shown in table 1, and then the selection module 500 may select, through the corresponding numbers, to transmit the first detection control signal DCS1 and the second detection control signal DSC2 to the first switch unit 110 and the third switch unit 120 connected to the through silicon vias corresponding to the numbers.
TABLE 1
| 11 | 12 | 13 | 14 | … | 1N |
| 21 | 22 | 23 | 24 | … | 2N |
| 31 | 32 | 33 | 34 | … | 3N |
| … | … | … | … | … | … |
| M1 | M2 | M3 | M4 | … | MN |
Further, the through silicon via detection circuit further includes a first detection through silicon via 600 and a second detection through silicon via 700, where one end of the first detection through silicon via is connected to the output end of the first detection control signal DCS1 of the selection module 500, and the other end of the first detection through silicon via is connected to the control end of the first switch unit 110; one end of the second detection tsv 700 is connected to the output end of the second detection control signal DSC2 of the selection module 500, and the other end is connected to the control end of the third switch unit 120. The first sensing through-silicon via 600 is used to transmit the first sensing control signal DCS1 to the control terminal of the corresponding first switching cell 110, and the second sensing through-silicon via 700 is used to transmit the second sensing control signal DSC2 to the control terminal of the corresponding third switching cell 120.
Wherein the through silicon via detection circuit may include: m first inspection through silicon vias 600, wherein a first end of each first inspection through silicon via 600 is connected to control ends of the plurality of first switch units 110 in the chip layer; the selection module 500 transmits the first detection control signal DCS1 to the second end of the first detection through silicon via 600 according to the selection control signal. Each of the M first through silicon vias 600 is connected to a stack layer, and the control terminals of the first switch units 110 of all the input modules 100 in the stack layer are connected to the first through silicon vias 600.
The through silicon via detection circuit may include: the N second detection through silicon vias 700, wherein a first end of each second detection through silicon via 700 is connected to control ends of a plurality of third switching units 120 corresponding to a through silicon via string; the selection module 500 transmits the second detection control signal DSC2 to the second end of a second detection through-silicon via 700 according to the selection control signal. Each second detecting through-silicon via 700 in the N second detecting through-silicon vias 700 is connected to a through-silicon via string, and the control ends of the second switch units 420 of the corresponding input modules 100 in the through-silicon vias are all connected to the second detecting through-silicon via 700.
It should be noted that the first and second inspection through silicon vias 600 and 700 according to the embodiments of the present disclosure are also through silicon vias and are inspected non-faulty through silicon vias. The first switch unit 110, the second switch unit 420, and the third switch unit 120 described in the embodiments of the present disclosure may be transistors, or may be elements such as transmission gates. The first end and the second end of the through silicon via in the embodiment of the present disclosure refer to two ends of the through silicon via, respectively, and the first end may be an upper end or a lower end, which is not specifically limited in the embodiment of the present disclosure. In the embodiment of the present disclosure, M and N are both positive integers greater than or equal to 1.
The through silicon via detection circuit provided by the embodiment of the disclosure can be matched with a repair circuit to increase the reliability of the through silicon via, find the fault through silicon via through the through silicon via detection circuit for the disclosure, and then replace the fault through silicon via through the repair circuit in the related technology, particularly the through silicon via provided by a redundancy mechanism.
In an exemplary embodiment of the present disclosure, there is also provided a through silicon via detection method, as shown in fig. 14, the through silicon via detection method includes:
step S1, turning on the first switch unit 110 by the first detection control signal DCS1, and the first power signal VDD is transmitted to the first input terminal of the comparison module 200 via the first switch unit 110 and the through silicon via;
step S2, transmitting a reference signal Vref to a second input terminal of the comparison module 200;
step S3, the comparing module 200 compares the signals input by the first input terminal and the second input terminal, and determines whether there is a fault in the tsv.
In an exemplary embodiment of the present disclosure, an integrated circuit is further provided, which includes the through silicon via detection circuit according to an embodiment of the present disclosure. Certainly, in practical application, the integrated circuit may further include components such as a PCB, a resistor, a capacitor, and the like, which are all the prior art, and this is not specifically limited in the embodiment of the present disclosure.
It should be noted that although the various steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that these steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc.
Furthermore, the above-described figures are merely schematic illustrations of processes involved in methods according to exemplary embodiments of the invention, and are not intended to be limiting. It will be readily understood that the processes shown in the above figures are not intended to indicate or limit the chronological order of the processes. In addition, it is also readily understood that these processes may be performed synchronously or asynchronously, e.g., in multiple modules.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is to be limited only by the terms of the appended claims.
Claims (17)
1. A through silicon via detection circuit, comprising:
the input module comprises a first switch unit, a control end is connected with a first detection control signal, a first end is connected with a first power end, a second end is connected with a first end of the through silicon via, and the input module is used for responding to the first detection control signal and conducting transmission of the first power signal to the first end of the through silicon via;
and the first input end of the comparison module is connected with the second end of the through silicon via, and the second input end of the comparison module is connected with the reference signal and is used for comparing the signal of the second end of the through silicon via with the reference signal.
2. The through-silicon-via detection circuit of claim 1, wherein the input module is disposed on a first chip layer, the comparison module is disposed on a second chip layer, and the first chip layer and the second chip layer are connected by a through-silicon-via.
3. The tsv detection circuit according to claim 2, wherein N input modules are disposed on the first chip layer, each of the N input modules is correspondingly connected to a first end of a tsv string, a second end of the tsv string is connected to a first input end of the comparison module, and the tsv string comprises a plurality of serial tsv's.
4. The through silicon via detection circuit of claim 3, wherein the comparison module comprises:
and the first input end of each of the N comparison units is respectively connected with the second end of a through silicon via string, and the second input ends of the N comparison units are connected with the reference signal.
5. The through silicon via detection circuit of claim 3, further comprising:
an output module, comprising:
the trigger is connected with an output control signal, a clock signal end and a first node and used for responding to a clock signal and transmitting the output control signal to the first node;
and the second switch unit is connected with the second end of the silicon through hole string, the first node and the first input end of the comparison module and is used for responding to the signal output by the trigger to be conducted so as to transmit the signal of the second end of the silicon through hole string to the first input end of the comparison module.
6. The through silicon via detection circuit of claim 5, wherein the through silicon via detection circuit comprises:
the first end of the second switch unit of each output module in the N output modules is respectively connected with the second end of a silicon through hole string, the second end of the second switch unit of each output module in the N output modules is connected with the first input end of the comparison module, the N output modules are arranged according to the sequence of the silicon through hole strings correspondingly connected with the N output modules, and the output end of the trigger in the previous output module is connected with the input end of the trigger in the next output module;
the comparison module comprises:
and the second ends of the N second switch units are connected to the first input end of the comparison unit, and the second input end of the comparison unit is connected to the reference signal.
7. The through silicon via detection circuit of claim 5, wherein the through silicon via detection circuit comprises:
the first end of the second switch unit of each output module in the N output modules is respectively connected with the second end of a silicon through hole string, the second end of the second switch unit of each output module in the N output modules is connected with the first input end of the comparison module, and the input ends of the triggers in the N output modules are all connected with output control signals;
the comparison module comprises:
the second ends of the N second switch units are respectively connected with the first input ends of the corresponding comparison units, and the second ends of the N comparison units are connected with the reference signal.
8. The through-silicon-via detection circuit of claim 6 or 7, wherein the input module further comprises:
and the third switch unit is connected with a second detection control signal at a control end, connected with the second end of the first switch unit at a first end, and connected with the first end of the through silicon via at a second end, and used for responding to the second detection control signal to conduct and transmit the signal of the second end of the first switch unit to the first end of the through silicon via.
9. The through silicon via detection circuit of claim 8, for an integrated circuit comprising M chip layers and each chip layer comprising N through silicon vias, the through silicon via detection circuit comprising:
m' N input modules, wherein each input module is connected with the first end of one through silicon via;
m' N through silicon vias form N through silicon via strings, each through silicon via string is provided with M through silicon vias connected in series, and the second end of each through silicon via string is connected with an output module;
the signal input end of the silicon through hole string is a first end, and the signal output end of the silicon through hole string is a second end.
10. The through silicon via detection circuit of claim 9, further comprising:
and the selection module is used for transmitting the first detection control signal to the control end of the first switch unit on one of the M chip layers according to the selection control signal and transmitting the second detection control signal to the control end of the third switch unit corresponding to one of the N through silicon via strings.
11. The through silicon via detection circuit of claim 10, further comprising:
one end of the first detection silicon through hole is connected with the first detection control signal output end of the selection module, and the other end of the first detection silicon through hole is connected with the control end of the first switch unit;
and one end of the second detection silicon through hole is connected with the second detection control signal output end of the selection module, and the other end of the second detection silicon through hole is connected with the control end of the third switch unit.
12. The through silicon via detection circuit of claim 11, wherein the through silicon via detection circuit comprises:
the first ends of the M first detection through silicon vias are connected with the control ends of the first switch units in a chip layer;
the selection module transmits a first detection control signal to the second end of the first detection through silicon via according to a selection control signal.
13. The through silicon via detection circuit of claim 11, wherein the through silicon via detection circuit comprises:
the first end of each second detection through silicon via is connected with the control ends of the plurality of third switch units corresponding to one through silicon via string;
and the selection module transmits the second detection control signal to a second end of the second detection through silicon via according to a selection control signal.
14. The through silicon via detection circuit of claim 5, wherein the comparison module and the output module are disposed on a substrate chip layer of an integrated circuit.
15. The through silicon via detection circuit of claim 5, wherein the comparison module and the output module are disposed on a top chip layer of the integrated circuit, the top chip layer being a layer of the plurality of chip layers that is farthest from the base chip layer.
16. A through silicon via detection method for the through silicon via detection circuit according to any one of claims 1 to 15, the through silicon via detection method comprising:
the first switch unit is conducted by utilizing the first detection control signal, and the first power supply signal is transmitted to the first input end of the comparison module through the first switch unit and the through silicon via;
transmitting a reference signal to a second input of the comparison module;
and comparing the signals input by the first input end and the second input end through the comparison module to judge whether the through silicon via has a fault.
17. An integrated circuit comprising the through silicon via detection circuit of any of claims 1-15.
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| CN201811367326.2A CN111198316B (en) | 2018-11-16 | 2018-11-16 | Through silicon via detection circuit and method, integrated circuit |
| PCT/CN2019/118464 WO2020098740A1 (en) | 2018-11-16 | 2019-11-14 | Through-silicon via detecting circuit, method and integrated circuit having the same |
| US17/215,386 US11408929B2 (en) | 2018-11-16 | 2021-03-29 | Through-silicon via detecting circuit, method and integrated circuit having the same |
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| CN201811367326.2A CN111198316B (en) | 2018-11-16 | 2018-11-16 | Through silicon via detection circuit and method, integrated circuit |
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