CN111179837B - Shift register, driving method, driving circuit and display device - Google Patents

Abstract

The invention discloses a shift register, a driving method, a driving circuit and a display device. By setting a node control circuit, not only the signal of the pull-down node can be adjusted by the control circuit, but also the signal of the pull-down node can be adjusted through the node control circuit, thereby The signal change of the pull-down node can be accelerated, for example, the rate at which the pull-down node can be pulled up can be increased. Therefore, the node noise reduction capability of the shift register can be improved, thereby improving the output stability.

Description

Shift register, driving method, driving circuit and display device

technical field

The present invention relates to the field of display technology, and in particular, to a shift register, a driving method, a driving circuit and a display device.

Background technique

With the rapid development of display technology, display devices are increasingly developing towards a direction of high integration and low cost. Among them, the GOA (Gate Driver on Array, array substrate row drive) technology integrates a TFT (Thin Film Transistor, thin film transistor) gate drive circuit on an array substrate of a display device to form a scan drive for the display device. However, the stability of the node signal of the shift register is poor, which in turn leads to reduced output stability.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide a shift register, a driving method, a driving circuit and a display device, which can improve output stability.

Therefore, an embodiment of the present invention provides a shift register, including:

an input circuit configured to provide the signal at the input signal terminal to the pull-up node in response to the signal at the input signal terminal;

a reset circuit, configured to provide the signal of the first reference voltage signal terminal to the pull-up node in response to the signal of the reset signal terminal;

a control circuit configured to adjust the signals of the pull-up node and the pull-down node;

a node control circuit configured to adjust the signal of the pull-down node in response to the signal at the reset signal terminal;

The output circuit is configured to cause the output signal terminal to output a signal according to the signals of the pull-up node and the pull-down node.

Optionally, the pull-down node includes M pull-down nodes; the control circuit includes M sub-control circuits; wherein, the m-th sub-control circuit in the M sub-control circuits corresponds to the m-th sub-control circuit in the M pull-down nodes pull-down nodes; M is an integer and M≥1, m is an integer and 1≤m≤M;

the mth sub-control circuit is configured to adjust the signals of the mth pull-down node and the pull-up node;

the node control circuit is configured to adjust the signals of the M pull-down nodes in response to the signal of the reset signal terminal;

The output circuit is configured to cause the output signal terminal to output a signal according to the signal of the pull-up node and the signals of the M pull-down nodes.

Optionally, the node control circuit includes: M first switch transistors; wherein, the mth first switch transistor in the M first switch transistors corresponds to the mth pull-down node;

The first terminal of the mth first switch transistor is electrically connected to the mth selection control signal terminal, the control terminal of the mth first switch transistor is electrically connected to the reset signal terminal, and the mth first switch transistor is electrically connected to the reset signal terminal. The second end of the first switching transistor is electrically connected to the mth pull-down node.

Optionally, the mth sub-control circuit corresponds to the mth selection control signal terminal;

The mth sub-control circuit includes: the mth second switch transistor, the mth third switch transistor, the mth fourth switch transistor, the mth fifth switch transistor, and the mth sixth switch transistor;

The control terminal and the first terminal of the mth second switch transistor are both electrically connected to the mth selection control signal terminal, and the second terminal of the mth second switch transistor is electrically connected to the mth selection control signal terminal. The control terminals of the three-switch transistors are electrically connected;

The first terminal of the mth third switch transistor is electrically connected to the mth selection control signal terminal, and the second terminal of the mth third switch transistor is electrically connected to the mth pull-down node;

The first terminal of the mth fourth switch transistor is electrically connected to the first reference signal terminal, the control terminal of the mth fourth switch transistor is electrically connected to the mth pull-down node, and the mth fourth switch transistor is electrically connected to the mth pull-down node. Second ends of the m fourth switching transistors are electrically connected to the pull-up node;

The first terminal of the mth fifth switch transistor is electrically connected to the first reference signal terminal, the control terminal of the mth fifth switch transistor is electrically connected to the pull-up node, and the mth fifth switch transistor is electrically connected to the pull-up node. The second end of the fifth switch transistor is electrically connected to the control end of the mth third switch transistor;

The first terminal of the mth sixth switch transistor is electrically connected to the first reference signal terminal, the control terminal of the mth sixth switch transistor is electrically connected to the pull-up node, and the mth sixth switch transistor is electrically connected to the pull-up node. The second end of the sixth switch transistor is electrically connected to the mth pull-down node.

Optionally, the input circuit includes a seventh switch transistor, a first terminal and a control terminal of the seventh switch transistor are both electrically connected to the input signal terminal, and a second terminal of the seventh switch transistor is electrically connected to the input signal terminal. The pull-up node is electrically connected.

Optionally, the reset circuit includes: an eighth switch transistor;

The first terminal of the eighth switch transistor is electrically connected to the first reference signal terminal, the control terminal of the eighth switch transistor is electrically connected to the reset signal terminal, and the second terminal of the eighth switch transistor is electrically connected to the reset signal terminal. The pull-up nodes are electrically connected.

Optionally, the output circuit includes: a ninth switch transistor, M tenth switch transistors, and a storage capacitor; wherein,

The first terminal of the ninth switch transistor is electrically connected to the clock signal terminal, the control terminal of the ninth switch transistor is electrically connected to the pull-up node, and the second terminal of the ninth switch transistor is electrically connected to the output signal terminal electrical connection;

The first terminal of the mth tenth switch transistor among the M tenth switch transistors is electrically connected to the first reference signal terminal, and the control terminal of the mth tenth switch transistor is electrically connected to the mth tenth switch transistor. the pull-down node is electrically connected, and the second terminal of the mth tenth switch transistor is electrically connected to the output signal terminal;

The first terminal of the storage capacitor is electrically connected to the pull-up node, and the second terminal of the storage capacitor is electrically connected to the output signal terminal.

Optionally, an eleventh switch transistor is further included, a first end of the eleventh switch transistor is electrically connected to the first reference signal terminal, and a control terminal of the eleventh switch transistor is connected to the frame reset signal The terminal is electrically connected, and the second terminal of the eleventh switch transistor is electrically connected to the pull-up node.

Optionally, it also includes a twelfth switch transistor, the first terminal of the twelfth switch transistor is electrically connected to the first reference signal terminal, and the control terminal of the twelfth switch transistor is electrically connected to the frame reset signal terminal. connected, and the second end of the twelfth switch transistor is electrically connected to the output signal end.

Correspondingly, an embodiment of the present invention also provides a driving circuit, comprising a plurality of the above-mentioned shift registers in cascade;

The input signal terminal of the first-stage shift register is electrically connected to the frame trigger signal terminal;

In each adjacent two-stage shift register, the input signal terminal of the next-stage shift register is electrically connected to the output signal terminal of the previous-stage shift register;

In each adjacent two-stage shift register, the output signal terminal of the next-stage shift register is electrically connected to the reset signal terminal of the previous-stage shift register.

Correspondingly, an embodiment of the present invention also provides a display device including the above-mentioned driving circuit.

Correspondingly, an embodiment of the present invention also provides a method for driving the above-mentioned shift register, including:

In the input stage, the input signal terminal is loaded with a first level signal, the reset signal terminal is loaded with a second level signal, and the clock signal terminal is loaded with a second level signal;

In the output stage, the input signal terminal is loaded with the second level signal, the reset signal terminal is loaded with the second level signal, and the clock signal terminal is loaded with the first level signal;

In the reset stage, the input signal terminal is loaded with a second level signal, the reset signal terminal is loaded with a first level signal, and the clock signal terminal is loaded with a second level signal.

The beneficial effects of the present invention are as follows:

In the shift register, driving method, driving circuit and display device provided by the embodiments of the present invention, by setting the node control circuit, not only the signal of the pull-down node can be adjusted by the control circuit, but also the signal of the pull-down node can be adjusted by the node control circuit, thereby The signal change of the pull-down node can be accelerated, for example, the rate at which the pull-down node can be pulled up can be increased. Therefore, the node noise reduction capability of the shift register can be improved, thereby improving the output stability.

Description of drawings

1 is a schematic structural diagram of a shift register provided by the related art;

Fig. 2 is the signal timing diagram of the shift register shown in Fig. 1;

3 is a schematic structural diagram of a shift register provided by an embodiment of the present invention;

4 is a schematic structural diagram of another shift register provided by an embodiment of the present invention;

5a is a schematic diagram of a specific structure of a shift register provided by an embodiment of the present invention;

5b is a schematic diagram of a specific structure of another shift register provided by an embodiment of the present invention;

6 is a signal timing diagram according to an embodiment of the present invention;

7 is a flowchart of a driving method provided by an embodiment of the present invention;

FIG. 8 is a schematic structural diagram of a driving circuit provided by an embodiment of the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are some, but not all, embodiments of the present invention. Also, the embodiments of the present invention and the features of the embodiments may be combined with each other without conflict. Based on the described embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present invention.

Unless otherwise defined, technical or scientific terms used in the present invention should have the ordinary meaning as understood by one of ordinary skill in the art to which the present invention belongs. The terms "first," "second," and similar terms used herein do not denote any order, quantity, or importance, but are merely used to distinguish different components. "Comprises" or "comprising" and similar words mean that the elements or things appearing before the word encompass the elements or things recited after the word and their equivalents, but do not exclude other elements or things. Words like "connected" or "electrically connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect the actual scale, and are only intended to illustrate the content of the present invention. And the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout.

As shown in FIG. 1 , the shift register generally includes transistors M01 to M011 and a capacitor CST. The signal timing diagram corresponding to the shift register shown in FIG. 1 is shown in FIG. 2 . Moreover, the working process may be substantially the same as the working process in the related art, which will not be repeated here. Among them, it can be known from FIG. 2 that in the t02 stage, the output terminal COUT outputs a high-level signal. In the remaining stages except the t02 stage, the output terminal COUT outputs a low-level signal. In practical applications, it is necessary to cooperate with each other of the transistors M01 to M011, so that the output terminal COUT outputs a corresponding signal.

In practical applications, the size of the transistors may be prepared differently, so that the discharge capacity of the transistors is also different. During phase t03, node PU is generally discharged through transistor M02. However, node PU discharges slower due to transistor size issues. In addition, the size of transistors M06 and M05 is generally larger than that of transistors M03 and M04, which leads to a slower pull-up of node PD, resulting in poor node noise reduction capability of the shift register, which in turn leads to output stability. reduce.

A shift register provided by an embodiment of the present invention, as shown in FIG. 3 , may include:

The input circuit 10 is configured to provide the signal of the input signal terminal Input to the pull-up node N1 in response to the signal of the input signal terminal Input;

The reset circuit 20 is configured to provide the signal of the first reference voltage signal terminal VSS to the pull-up node N1 in response to the signal of the reset signal terminal Reset;

The control circuit 30 is configured to adjust the signals of the pull-up node N1 and the pull-down node P;

The node control circuit 40 is configured to adjust the signal of the pull-down node P in response to the signal of the reset signal terminal Reset;

The output circuit 50 is configured to make the output signal terminal Output output a signal according to the signals of the pull-up node N1 and the pull-down node P.

In the shift register provided by the embodiment of the present invention, by setting a node control circuit, not only the signal of the pull-down node can be adjusted by the control circuit, but also the signal of the pull-down node can be adjusted by the node control circuit, so that the signal change of the pull-down node can be accelerated, for example It can increase the rate of pulling up and pulling down nodes. Therefore, the node noise reduction capability of the shift register can be improved, thereby improving the output stability.

During specific implementation, in this embodiment of the present invention, the pull-down node P may include M pull-down nodes; the control circuit 30 may include M sub-control circuits; wherein, the m-th sub-control circuit 30-m in the M sub-control circuits corresponds to M The mth pull-down node Pm among the pull-down nodes; M is an integer and M≥1, m is an integer and 1≤m≤M;

The mth sub-control circuit 30-m is configured to adjust the signals of the mth pull-down node Pm and the pull-up node N1;

The node control circuit 40 is configured to adjust the signals of the M pull-down nodes in response to the signal of the reset signal terminal Reset;

The output circuit 50 is configured to cause the output signal terminal Output to output a signal according to the signal of the pull-up node N1 and the signals of the M pull-down nodes.

Exemplarily, as shown in FIG. 4 , M=2 can be set. Then the pull-down nodes may include the first pull-down node P1 and the second pull-down node P2. The control circuit 30 may include: a first sub-control circuit 30-1 corresponding to the first pull-down node P1 and a second sub-control circuit 30-2 corresponding to the second pull-down node P2; wherein, the first sub-control circuit 30- 1 is configured to adjust the signal of the first pull-down node P1 and the pull-up node N1. The second sub-control circuit 30-2 is configured to adjust the signals of the second pull-down node P2 and the pull-up node N1. The node control circuit 40 is configured to adjust the signals of the first pull-down node P1 and the second pull-down node P2 in response to the signal of the reset signal terminal Reset. The output circuit 50 is configured to make the output signal terminal Output output a signal according to the signal of the pull-up node N1, the signals of the first pull-down node P1 and the second pull-down node P2. In specific implementation, M may be 1, or M=3, M=4, M=5, etc. The specific value of M can be determined according to the actual application environment design, which is not limited here. The following description takes M=2 as an example.

During specific implementation, in this embodiment of the present invention, the node control circuit 40 may include: M first switch transistors M1; wherein, the mth first switch transistor M1-m in the M first switch transistors corresponds to the mth first switch transistor M1-m a drop-down node Pm;

The first terminal of the m-th first switching transistor M1-m is electrically connected to the m-th selection control signal terminal VDD-m, the control terminal of the m-th first switching transistor M1-m is electrically connected to the reset signal terminal Reset, and the The second terminals of the m first switching transistors M1-m are electrically connected to the m-th pull-down node Pm.

Exemplarily, as shown in FIG. 4 , M=2, then the node control circuit 40 may include two first switch transistors M1 ; the first one of the two first switch transistors M1-1 The first terminal is electrically connected to the first selection control signal terminal VDD-1, the first terminal of the second first switching transistor M1-2 is electrically connected to the second selection control signal terminal VDD-2; The control terminals of the switch transistor M1-1 and the second first switch transistor M1-2 are both electrically connected to the reset signal terminal Reset, and the second terminal of the first first switch transistor M1-1 is electrically connected to the first pull-down node P1. connected, and the second end of the second first switching transistor M1-2 is electrically connected to the second pull-down node P2.

During specific implementation, in this embodiment of the present invention, the mth sub-control circuit 30-m may correspond to the mth selection control signal terminal VDD-m;

The mth sub-control circuit 30-m may include: the mth second switch transistor M2-m, the mth third switch transistor M3-m, the mth fourth switch transistor M4-m, and the mth fifth switch the transistor M5-m and the mth sixth switch transistor M6-m;

The control terminal and the first terminal of the m-th second switch transistor M2-m are both electrically connected to the m-th selection control signal terminal VDD-m, and the second terminal of the m-th second switch transistor M2-m is electrically connected to the m-th selection control signal terminal VDD-m. The control terminals of the third switching transistors M3-m are electrically connected;

The first terminal of the mth third switch transistor M3-m is electrically connected to the mth selection control signal terminal VDD-m, and the second terminal of the mth third switch transistor M3-m is electrically connected to the mth pull-down node Pm connect;

The first terminal of the mth fourth switch transistor M4-m is electrically connected to the first reference signal terminal VSS, the control terminal of the mth fourth switch transistor M4-m is electrically connected to the mth pull-down node Pm, and the mth fourth switch transistor M4-m is electrically connected to the mth pull-down node Pm. The second end of the fourth switching transistor M4-m is electrically connected to the pull-up node N1;

The first terminal of the mth fifth switch transistor M5-m is electrically connected to the first reference signal terminal VSS, the control terminal of the mth fifth switch transistor M5-m is electrically connected to the pull-up node N1, and the mth fifth switch transistor M5-m is electrically connected to the pull-up node N1. The second end of the switch transistor M5-m is electrically connected to the control end of the mth third switch transistor M3-m;

The first terminal of the mth sixth switch transistor M6-m is electrically connected to the first reference signal terminal VSS, the control terminal of the mth sixth switch transistor M6-m is electrically connected to the pull-up node N1, and the mth sixth switch transistor M6-m is electrically connected to the pull-up node N1. The second end of the switching transistor M6-m is electrically connected to the m-th pull-down node Pm.

Exemplarily, as shown in FIG. 5a and FIG. 5b, M=2 can be set, then the first sub-control circuit 30-1 corresponds to the first selection control signal terminal VDD-1, and the second sub-control circuit 30-2 corresponds to the first selection control signal terminal VDD-1. 2 selection control signal terminals VDD-2;

The first sub-control circuit 30-1 includes: the first second switch transistor M2-1, the first third switch transistor M3-1, the first fourth switch transistor M4-1, and the first fifth switch transistor M5-1 and the first sixth switch transistor M6-1; the second sub-control circuit 30-2 includes: the second second switch transistor M2-2, the second third switch transistor M3-2, the second the fourth switch transistor M4-2, the second fifth switch transistor M5-2, and the second sixth switch transistor M6-2;

Both the control terminal and the first terminal of the first second switching transistor M2-1 are electrically connected to the first selection control signal terminal VDD-1, and the second terminal and the first selection control signal terminal VDD-1 of the first second switching transistor M2-1 The control terminal of the third switch transistor M3-1 is electrically connected; the control terminal and the first terminal of the second second switch transistor M2-2 are both electrically connected to the second selection control signal terminal VDD-2, and the second second switch transistor M2-2 is electrically connected to the second selection control signal terminal VDD-2. The second end of the switch transistor M2-2 is electrically connected to the control end of the second third switch transistor M3-2;

The first terminal of the first third switch transistor M3-1 is electrically connected to the first selection control signal terminal VDD-1, and the second terminal of the first third switch transistor M3-1 is electrically connected to the first pull-down node P1 connection; the first end of the second third switch transistor M3-2 is electrically connected to the second selection control signal end VDD-2, and the second end of the second third switch transistor M3-2 is electrically connected to the second pull-down node P2 electrical connection;

The first terminal of the first fourth switch transistor M4-1 is electrically connected to the first reference signal terminal, the control terminal of the first fourth switch transistor M4-1 is electrically connected to the first pull-down node P1, and the first The second terminal of the four-switch transistor M4-1 is electrically connected to the pull-up node N1; the first terminal of the second fourth switch transistor M4-2 is electrically connected to the first reference signal terminal VSS, and the second fourth switch transistor M4 is electrically connected to the first reference signal terminal VSS. The control terminal of -2 is electrically connected to the second pull-down node P2, and the second terminal of the second fourth switch transistor M4-2 is electrically connected to the pull-up node N1;

The first terminal of the first fifth switch transistor M5-1 is electrically connected to the first reference signal terminal VSS, the control terminal of the first fifth switch transistor M5-1 is electrically connected to the pull-up node N1, and the first fifth switch transistor M5-1 is electrically connected to the pull-up node N1. The second terminal of the switch transistor M5-1 is electrically connected to the control terminal of the first third switch transistor M3-1; the first terminal of the second fifth switch transistor M5-2 is electrically connected to the first reference signal terminal VSS, The control terminal of the second fifth switch transistor M5-2 is electrically connected to the pull-up node N1, and the second terminal of the second fifth switch transistor M5-2 is electrically connected to the control terminal of the second third switch transistor M3-2 connect;

The first terminal of the first sixth switch transistor M6-1 is electrically connected to the first reference signal terminal VSS, the control terminal of the first sixth switch transistor M6-1 is electrically connected to the pull-up node N1, and the first sixth switch transistor M6-1 is electrically connected to the pull-up node N1. The second terminal of the switch transistor M6-1 is electrically connected to the first pull-down node P1; the first terminal of the second sixth switch transistor M6-2 is electrically connected to the first reference signal terminal VSS, and the second sixth switch transistor M6-2 is electrically connected to the first reference signal terminal VSS. The control terminal of M6-2 is electrically connected to the pull-up node N1, and the second terminal of the second sixth switching transistor M6-2 is electrically connected to the second pull-down node P2.

During specific implementation, in this embodiment of the present invention, as shown in FIGS. 5 a and 5 b , the input circuit 10 may include a seventh switch transistor M7 , and the first end and the control end of the seventh switch transistor M7 are both connected to the input signal end Input Electrically connected, the second end of the seventh switch transistor M7 is electrically connected to the pull-up node N1.

During specific implementation, in this embodiment of the present invention, as shown in FIG. 5a and FIG. 5b, the reset circuit 20 may include: an eighth switch transistor M8;

The first terminal of the eighth switch transistor M8 is electrically connected to the first reference signal terminal VSS, the control terminal of the eighth switch transistor M8 is electrically connected to the reset signal terminal Reset, and the second terminal of the eighth switch transistor M8 is electrically connected to the pull-up node N1. connect.

During specific implementation, in this embodiment of the present invention, as shown in FIGS. 5 a and 5 b , the output circuit 50 may include: a ninth switch transistor M9 , two tenth switch transistors M10 - 1 , M10 - 2 , and a storage capacitor C ;in,

The first terminal of the ninth switch transistor M9 is electrically connected to the clock signal terminal CLK, the control terminal of the ninth switch transistor M9 is electrically connected to the pull-up node N1, and the second terminal of the ninth switch transistor M9 is electrically connected to the output signal terminal Output;

The first terminal of the first tenth switch transistor M10-1 and the second tenth switch transistor M10-2 of the two tenth switch transistors are electrically connected to the first reference signal terminal VSS, and the first tenth switch transistor M10-2 is electrically connected to the first reference signal terminal VSS. The control terminal of M10-1 is electrically connected to the first pull-down node P1, the control terminal of the second tenth switch transistor M10-2 is electrically connected to the second pull-down node P2, and the first tenth switch transistor M10-1 and The second end of the second tenth switch transistor M10-2 is electrically connected to the output signal end Output;

The first terminal of the storage capacitor C is electrically connected to the pull-up node N1, and the second terminal of the storage capacitor C is electrically connected to the output signal terminal Output.

During specific implementation, in this embodiment of the present invention, as shown in FIG. 5b, the shift register may further include an eleventh switch transistor M11, and a first end of the eleventh switch transistor M11 is electrically connected to the first reference signal terminal VSS , the control terminal of the eleventh switch transistor M11 is electrically connected to the frame reset signal terminal STV, and the second terminal of the eleventh switch transistor M11 is electrically connected to the pull-up node N1.

During specific implementation, in this embodiment of the present invention, as shown in FIG. 5b, the shift register may further include a twelfth switch transistor M12, and a first end of the twelfth switch transistor M12 is electrically connected to the first reference signal terminal VSS , the control terminal of the twelfth switch transistor M12 is connected to the frame reset signal terminal STV, and the second terminal of the twelfth switch transistor M12 is electrically connected to the output signal terminal Output.

The above is only an example to illustrate the specific structure of the shift register provided by the embodiment of the present invention. During the specific implementation, the specific structure of the above-mentioned circuits is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may be other structures known to those skilled in the art. The structure is not limited here.

Specifically, in order to unify the manufacturing process, in the shift register provided by the embodiment of the present invention, as shown in FIG. 5a and FIG. 5b, all switch transistors may be N-type transistors, and the signal of the first reference signal terminal VSS may be is a low level signal. Of course, all switch transistors may also be P-type transistors, which are not limited herein.

Specifically, in the shift register provided by the embodiment of the present invention, the P-type transistor is turned on under the action of a low-level signal, and is turned off under the action of a high-level signal; the N-type transistor is turned on under the action of a high-level signal, Cut off under the action of low level signal.

Specifically, in the shift register provided by the embodiment of the present invention, the above-mentioned switching transistors may be thin film transistors (TFT, Thin Film Transistor) or metal oxide semiconductor field effect transistors (MOS, Metal Oxide Scmiconductor). Not limited. In specific implementation, the control terminal of each switching transistor can be used as the gate, and according to the different types of the switching transistors and the different input signals, the first terminal of the switching transistor can be used as the source, and the second terminal can be used as the source. The drain, or the first end of the switching transistor is used as the drain, and the second end is used as the source, and no specific distinction is made here.

In a specific implementation, the signal of the first selection control signal terminal VDD-1 and the signal of the second selection control signal terminal VDD-2 can be pulse signals switched between high level and low level respectively, and the first selection control signal terminal VDD-2 The level of the signal at the control signal terminal VDD-1 is opposite to the level of the signal at the second selection control signal terminal VDD-2. For example, as shown in FIG. 6 , in the T10 stage, the first selection control signal terminal VDD-1 is a high-level signal, and the second selection control signal terminal VDD-2 is a low-level signal. In the T20 stage, the first selection control signal terminal VDD-1 is a low-level signal, and the second selection control signal terminal VDD-2 is a high-level signal. Exemplarily, the maintenance duration of the T10 phase can be made the same as the maintenance duration of the T20 phase. For example, the maintenance duration of the T10 stage and the maintenance duration of the T20 stage are respectively set to the duration of one display frame, the duration of multiple display frames, 2s, 1h, or 24h, etc., which are not limited here.

Among them, the sequence of the T10 stage and the T20 stage can be determined according to the actual application. For example, the work process in the T10 stage may be executed first, and then the work process in the T20 stage may be executed. Alternatively, the work process in the T20 stage can also be executed first, and then the work process in the T10 stage is executed. The present invention will be described in detail below with reference to specific embodiments. It should be noted that this embodiment is for better explanation of the present invention, but does not limit the present invention.

Taking the structure of the shift register shown in FIG. 5 a as an example, the working process of the above-mentioned shift register provided by the embodiment of the present invention will be described in combination with the signal timing diagram shown in FIG. 6 . In the following description, 1 represents a high voltage level, 0 means low level. It should be noted that, 1 and 0 are logic levels, which are only to better explain the specific working process of the embodiment of the present invention, rather than specific voltage values.

Specifically, the T10 stage and the T20 stage in the signal timing diagram shown in FIG. 6 are selected. In addition, among the T10 stages, the input stage T11, the reset stage T12, and the output stage T13 are selected. And select the input stage T21, the reset stage T22, and the output stage T23 in the T20 stage.

In the T10 stage, since the second selection control signal terminal VDD-2 is a low level signal, the second second switching transistor M2-2 is turned off.

In the input stage T11, Input=1, CLK=0, Reset=0.

Since Reset=0, the first first switching transistor M1-1 is turned off, the second first switching transistor M1-2 is turned off, and the eighth switching transistor M8 is turned off. Since Input=1, the seventh switch transistor M7 is turned on, and provides a high-level signal to the pull-up node N1, so that the pull-up node N1 is at a high level. The pull-up node N1 is at a high level, the first fifth switch transistor M5-1, the second fifth switch transistor M5-2, the first sixth switch transistor M6-1, and the second sixth switch transistor M6 -2. The ninth switching transistors M9 are all turned on.

The first fifth switch transistor M5-1 is turned on, and the low level signal of the first reference signal terminal VSS is provided to the gate of the first third switch transistor M3-1, so that the first third switch transistor M3 -1 deadline. The second fifth switching transistor M5-2 is turned on, and the low level signal of the first reference signal terminal VSS is provided to the gate of the second third switching transistor M3-2, so that the second third switching transistor M3 -2 deadline.

The first sixth switch transistor M6-1 is turned on, and provides the low level signal of the first reference signal terminal VSS to the first pull-down node P1, so that the first pull-down node P1 is at a low level, so that the first pull-down node P1 is at a low level. The fourth switching transistor M4-1 and the first tenth switching transistor M10-1 are both turned off. The second sixth switch transistor M6-2 is turned on, and provides the low level signal of the first reference signal terminal VSS to the second pull-down node P2, so that the second pull-down node P2 is at a low level, so that the second pull-down node P2 is at a low level. The fourth switching transistor M4-2 and the second tenth switching transistor M10-2 are both turned off.

The ninth switch transistor M9 is turned on, and provides the low-level signal of the clock signal terminal CLK to the output signal terminal Output, so that the output signal terminal Output outputs a low-level signal.

In the output stage T12, Input=0, CLK=1, Reset=0.

Since Reset=0, the first first switching transistor M1-1 is turned off, the second first switching transistor M1-2 is turned off, and the eighth switching transistor M8 is turned off. Since Input=0, the seventh switching transistor M7 is turned off. Therefore, the pull-up node N1 is in a floating state, and due to the bootstrapping effect of the storage capacitor C, the pull-up node N1 is kept at a high level, so that the first fifth switch transistor M5-1 and the second fifth switch transistor M5-1 M5-2, the first sixth switch transistor M6-1, the second sixth switch transistor M6-2, and the ninth switch transistor M9 are all turned on. Therefore, the first pull-down node P1 and the second pull-down node P2 are kept at a low level, so that the first fourth switch transistor M4-1, the second fourth switch transistor M4-2, and the first tenth switch The transistor M10-1 and the second tenth switch transistor M10-2 are both turned off.

The ninth switch transistor M9 is turned on, and provides the high-level signal of the clock signal terminal CLK to the output signal terminal Output, so that the output signal terminal Output outputs a high-level signal. Since the storage capacitor C keeps the voltage difference between its two ends unchanged, so that The signal level of the pull-up node N1 is further increased, so that the ninth switch transistor M9 is turned on more completely, so that the high-level signal of the clock signal terminal CLK can be output to the output signal terminal Output as much as possible without voltage loss .

In the reset phase T13, Input=0, CLK=0, Reset=1.

Since Reset=1, the first first switch transistor M1-1 is turned on, the second first switch transistor M1-2 is turned on, and the eighth switch transistor M8 is turned on. Since Input=0, the seventh switching transistor M7 is turned off.

Since the first selection control signal terminal VDD-1 is a high-level signal, the first second switching transistor M2-1 is turned on, and since the second selection control signal terminal VDD-2 is a low-level signal, the second switch transistor M2-1 is turned on. The second switching transistor M2-2 is turned off.

The first first switching transistor M1-1 is turned on, and the high level signal of the first selection control signal terminal VDD-1 is provided to the first pull-down node P1, so that the first pull-down node P1 is at a high level, Thus, the first fourth switching transistor M4-1 and the first tenth switching transistor M10-1 are turned on. The second and fourth switching transistor M4-2 is turned on, and provides the low-level signal of the first reference signal terminal VSS to the pull-up node N1. The first tenth switch transistor M10-1 is turned on, and provides the low-level signal of the first reference signal terminal VSS to the output signal terminal Output, so that the output signal terminal Output outputs a low-level signal.

The second first switch transistor M1-2 is turned on, and the low level signal of the second selection control signal terminal VDD-2 is provided to the second pull-down node P2, so that the second pull-down node P2 is at a low level, Therefore, the second fourth switching transistor M4-2 and the second tenth switching transistor M10-2 are turned off.

The eighth switch transistor M8 provides the low level signal of the first reference signal terminal VSS to the pull-up node N1, so that the pull-up node N1 is at a low level, the ninth switch transistor M9 is turned off, and the first fifth switch transistor M5 -1 is turned off, the first sixth switching transistor M6-1 is turned off, the second fifth switching transistor M5-2 is turned off, and the second sixth switching transistor M6-2 is turned off.

The first fifth switch transistor M5-1 is turned off, the first second switch transistor M2-1 is turned on, and the high level signal of the first selection control signal terminal VDD-1 is provided to the first third switch transistor The gate of M3-1 turns on the first third switching transistor M3-1. The high level signal of the first selection control signal terminal VDD-1 is provided to the first pull-down node P1 through the first third switching transistor M3-1.

The second fifth switching transistor M5-2 is turned off, and the second second switching transistor M2-2 is turned off, so the gate of the second third switching transistor M3-2 remains a low level signal, and the second third switching transistor M3-2 is turned off. The switching transistor M3-2 is turned off.

In the stage T20, since the first selection control signal terminal VDD-1 is a low level signal, the first second switching transistor M2-1 is turned off.

In the input stage T21, Input=1, CLK=0, Reset=0.

Since Reset=0, the first first switching transistor M1-1 is turned off, the second first switching transistor M1-2 is turned off, and the eighth switching transistor M8 is turned off. Since Input=1, the seventh switch transistor M7 is turned on, and provides a high-level signal to the pull-up node N1, so that the pull-up node N1 is at a high level. The pull-up node N1 is at a high level, the first fifth switch transistor M5-1, the second fifth switch transistor M5-2, the first sixth switch transistor M6-1, and the second sixth switch transistor M6 -2. The ninth switching transistors M9 are all turned on.

The first fifth switch transistor M5-1 is turned on, and the low level signal of the first reference signal terminal VSS is provided to the gate of the first third switch transistor M3-1, so that the first third switch transistor M3 -1 deadline. The second fifth switching transistor M5-2 is turned on, and the low level signal of the first reference signal terminal VSS is provided to the gate of the second third switching transistor M3-2, so that the second third switching transistor M3 -2 deadline.

The first sixth switch transistor M6-1 is turned on, and provides the low level signal of the first reference signal terminal VSS to the first pull-down node P1, so that the first pull-down node P1 is at a low level, so that the first pull-down node P1 is at a low level. The fourth switching transistor M4-1 and the first tenth switching transistor M10-1 are both turned off. The second sixth switch transistor M6-2 is turned on, and provides the low level signal of the first reference signal terminal VSS to the second pull-down node P2, so that the second pull-down node P2 is at a low level, so that the second pull-down node P2 is at a low level. The fourth switching transistor M4-2 and the second tenth switching transistor M10-2 are both turned off.

The ninth switch transistor M9 is turned on, and provides the low-level signal of the clock signal terminal CLK to the output signal terminal Output, so that the output signal terminal Output outputs a low-level signal.

In the output stage T22, Input=0, CLK=1, Reset=0.

Since Reset=0, the first first switching transistor M1-1 is turned off, the second first switching transistor M1-2 is turned off, and the eighth switching transistor M8 and the eleventh switching transistor M11 are turned off. Since Input=0, the seventh switching transistor M7 is turned off. Therefore, the pull-up node N1 is in a floating state, and due to the bootstrapping effect of the storage capacitor C, the pull-up node N1 is kept at a high level, so that the first fifth switch transistor M5-1 and the second fifth switch transistor M5-1 M5-2, the first sixth switch transistor M6-1, the second sixth switch transistor M6-2, and the ninth switch transistor M9 are all turned on. Therefore, the first pull-down node P1 and the second pull-down node P2 are kept at a low level, so that the first fourth switch transistor M4-1, the second fourth switch transistor M4-2, and the first tenth switch The transistor M10-1 and the second tenth switch transistor M10-2 are both turned off.

The ninth switch transistor M9 is turned on, and provides the high-level signal of the clock signal terminal CLK to the output signal terminal Output, so that the output signal terminal Output outputs a high-level signal. Since the storage capacitor C keeps the voltage difference between its two ends unchanged, so that The signal level of the pull-up node N1 is further raised.

In the reset phase T23, Input=0, CLK=0, Reset=1.

Since Reset=1, the first first switch transistor M1-1 is turned on, the second first switch transistor M1-2 is turned on, and the eighth switch transistor M8 and the eleventh switch transistor M11 are turned on. Since Input=0, the seventh switching transistor M7 is turned off.

Since the first selection control signal terminal VDD-1 is a low-level signal, the first second switching transistor M2-1 is turned off, and since the second selection control signal terminal VDD-2 is a high-level signal, the second The two switching transistors M2-2 are turned on.

The second first switch transistor M1-2 is turned on, and provides the high level signal of the second selection control signal terminal VDD-2 to the second pull-down node P2, so that the second pull-down node P2 is at a high level, Thus, the second fourth switching transistor M4-2 and the second tenth switching transistor M10-2 are turned on. The first fourth switch transistor M4-1 is turned on, and provides the low level signal of the first reference signal terminal VSS to the pull-up node N2. The second tenth switch transistor M10-2 is turned on, and provides the low-level signal of the first reference signal terminal VSS to the output signal terminal Output, so that the output signal terminal Output outputs a low-level signal.

The first first switching transistor M1-1 is turned on, and the low level signal of the first selection control signal terminal VDD-1 is provided to the first pull-down node P1, so that the first pull-down node P1 is at a low level, Therefore, the first fourth switching transistor M4-1 and the first tenth switching transistor M10-1 are turned off.

The eighth switch transistor M8 and the eleventh switch transistor M11 are turned on, and the low-level signal of the first reference signal terminal VSS is provided to the pull-up node N1, so that the pull-up node N1 is at a low level, and the ninth switch transistor M9 is turned off , the first fifth switching transistor M5-1 is turned off, the first sixth switching transistor M6-1 is turned off, the second fifth switching transistor M5-2 is turned off, and the second sixth switching transistor M6-2 is turned off.

The second fifth switch transistor M5-2 is turned off, the second second switch transistor M2-2 is turned on, and the high level signal of the second selection control signal terminal VDD-2 is provided to the second third switch transistor The gate of M3-2 turns on the second third switching transistor M3-2. The high level signal of the second selection control signal terminal VDD-2 is provided to the second pull-down node P2 through the second third switching transistor M3-2.

The first fifth switching transistor M5-1 is turned off, and the first second switching transistor M2-1 is turned off, so the gate of the first third switching transistor M3-1 remains a low-level signal, and the first third switching transistor M3-1 is at a low level. The switching transistor M3-1 is turned off. In the reset stage T13, by setting the first first switching transistor M1-1, when the signal of the reset signal terminal Reset changes from a low level to a high level, the first selection control signal terminal VDD-1 A high level signal is provided to the first pull-down node P1, so that the signal of the first pull-down node P1 can be changed to a high level quickly. In the reset phase T23, by setting the second first switch transistor M1-2, when the signal of the reset signal terminal Reset changes from a low level to a high level, the second selection control signal terminal VDD-2 A high level signal is provided to the second pull-down node P2, so that the signal of the second pull-down node P2 can be changed to a high level quickly. By changing the signal of the pull-down node faster, the signal change of the pull-up node is accelerated, thereby improving the noise reduction level of the shift register.

The working process of the shift register shown in FIG. 5b is substantially the same as the above working process. The difference is that in each frame, before the input stage T11, it may further include: the eleventh switch transistor M11 is turned on under the control of the high level of the frame reset signal terminal STV, so as to switch the first reference signal The low level signal of the terminal VSS is supplied to the pull-up node N1 to reset the pull-up node N1. And, the twelfth switch transistor M12 is turned on under the control of the high level of the frame reset signal terminal STV, so as to provide the low level signal of the first reference signal terminal VSS to the output signal terminal Output, so as to provide the output signal terminal Output with a low level signal. Perform a reset. The other specific processes are not repeated here.

Based on the same inventive concept, an embodiment of the present invention also provides a method for driving a shift register, as shown in FIG. 7 , which may include the following steps:

S10. In the input stage, the input signal terminal is loaded with the first level signal, the reset signal terminal is loaded with the second level signal, and the clock signal terminal is loaded with the second level signal;

S20. In the output stage, the input signal terminal is loaded with the second level signal, the reset signal terminal is loaded with the second level signal, and the clock signal terminal is loaded with the first level signal;

S30. In the reset stage, the input signal terminal is loaded with the second level signal, the reset signal terminal is loaded with the first level signal, and the clock signal terminal is loaded with the second level signal.

The above driving method provided by the embodiment of the present invention can make the shift register output a signal stably. During specific implementation, in the above driving method provided by the embodiment of the present invention, the first level may be a high level, and correspondingly, the second level may be a low level; or conversely, the first level may be a low level level, correspondingly, the second level is a high level, which specifically needs to be determined according to whether the transistor in the shift register is an N-type transistor or a P-type transistor. Specifically, FIG. 6 shows a signal timing diagram in which the transistors in the shift register are N-type transistors, and the first level is a high level and the second level is a low level.

Based on the same inventive concept, an embodiment of the present invention also provides a gate drive circuit, as shown in FIG. 8 , which includes a plurality of cascaded shift registers provided by the embodiment of the present invention: SR(1), SR(2) ...SR(n-1), SR(n)...SR(N-1), SR(N) (N shift registers in total, 1≤n≤N, n and N are positive integers), where,

The input signal terminal Input of the first-stage shift register SR(1) is electrically connected to the frame trigger signal terminal VS;

In each adjacent two-stage shift register, the input signal terminal Input of the next-stage shift register SR(n) is electrically connected to the output signal terminal Output of the previous-stage shift register SR(n-1);

In each adjacent two-stage shift register, the output signal terminal Output of the next-stage shift register SR(n) is electrically connected to the reset signal terminal Reset of the previous-stage shift register SR(n-1).

Specifically, each shift register in the gate driving circuit described above is the same in function and structure as the shift register provided by the embodiment of the present invention, and repeated details are not repeated here.

In specific implementation, in the gate drive circuit provided by the embodiment of the present invention, as shown in FIG. 8 , the clock signal terminals CLK of the odd-numbered stage shift registers are all electrically connected to the same clock terminal clk1, and the even-numbered stage shift registers are electrically connected to the same clock terminal clk1. The clock signal terminals CLK are all electrically connected to the same clock terminal clk2.

During specific implementation, in the gate driving circuit provided by the embodiment of the present invention, the first reference signal terminal VSS of each stage of the shift register is electrically connected to the same first reference terminal.

Based on the same inventive concept, an embodiment of the present invention further provides a display device including the above-mentioned driving circuit provided by the present invention. The specific implementation can refer to the above-mentioned implementation process of the shift register, and the similarities will not be repeated.

During specific implementation, the above-mentioned display device provided in the embodiment of the present invention may be an organic light-emitting display device, or may also be a liquid crystal display device, which is not limited herein.

In an organic light emitting display device, a plurality of organic light emitting diodes and a pixel circuit connected to each organic light emitting diode are generally provided. Generally, a pixel circuit is provided with a light-emitting control transistor for controlling the light emission of the organic light-emitting diode and a scan control transistor for controlling the input of a data signal. In specific implementation, when the above-mentioned display device provided by the embodiment of the present invention is an organic light-emitting display device, the organic light-emitting display device may include the above-mentioned driving circuit provided by the embodiment of the present invention. It is used to provide the light-emitting control signal of the light-emitting control transistor; or, the driving circuit can also be used as a gate driving circuit to provide the gate scanning signal of the scanning control transistor. Of course, the organic light-emitting display device may also include two of the above-mentioned drive control circuits provided in the embodiments of the present invention, and one of the drive circuits may be used as a light-emitting drive circuit to provide a light-emitting control signal of the light-emitting control transistor; the other drive circuit may be used as a light-emitting control signal. The gate driving circuit is applied to provide the gate scan signal of the scan control transistor, which is not limited here.

In a liquid crystal display device, a plurality of pixel electrodes and switching transistors connected to each pixel electrode are generally provided. In specific implementation, when the above-mentioned display device provided by the embodiment of the present invention is a liquid crystal display device, the above-mentioned driving circuit provided by the embodiment of the present invention can be used as a gate driving circuit to provide a gate scanning signal of a switching transistor.

The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, a navigator, and the like. Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should it be regarded as a limitation of the present invention.

In the shift register, driving method, driving circuit and display device provided by the embodiments of the present invention, by setting the node control circuit, not only the signal of the pull-down node can be adjusted by the control circuit, but also the signal of the pull-down node can be adjusted by the node control circuit, thereby The signal change of the pull-down node can be accelerated, for example, the rate at which the pull-down node can be pulled up can be increased. Therefore, the node noise reduction capability of the shift register can be improved, thereby improving the output stability.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention. Thus, provided that these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims (8)

1. a shift register, is characterized in that, comprises: an input circuit configured to provide the signal at the input signal terminal to the pull-up node in response to the signal at the input signal terminal; a reset circuit configured to provide a signal at the first reference signal terminal to the pull-up node in response to a signal at the reset signal terminal; a control circuit configured to adjust the signals of the pull-up node and the pull-down node; a node control circuit configured to adjust the signal of the pull-down node in response to the signal at the reset signal terminal; an output circuit, configured to make the output signal terminal output a signal according to the signals of the pull-up node and the pull-down node; The pull-down node includes M pull-down nodes; the control circuit includes M sub-control circuits; wherein, the m-th sub-control circuit in the M sub-control circuits corresponds to the m-th pull-down node in the M pull-down nodes; M is an integer and M≥1, m is an integer and 1≤m≤M; the mth sub-control circuit is configured to adjust the signals of the mth pull-down node and the pull-up node; the node control circuit is configured to adjust the signals of the M pull-down nodes in response to the signal of the reset signal terminal; The output circuit is configured to cause the output signal terminal to output a signal according to the signal of the pull-up node and the signals of the M pull-down nodes; The mth sub-control circuit corresponds to the mth selection control signal terminal; The mth sub-control circuit includes: the mth second switch transistor, the mth third switch transistor, the mth fourth switch transistor, the mth fifth switch transistor, and the mth sixth switch transistor; The control terminal and the first terminal of the mth second switch transistor are both electrically connected to the mth selection control signal terminal, and the second terminal of the mth second switch transistor is electrically connected to the mth selection control signal terminal. The control terminals of the three-switch transistors are electrically connected; The first terminal of the mth third switch transistor is electrically connected to the mth selection control signal terminal, and the second terminal of the mth third switch transistor is electrically connected to the mth pull-down node; The first terminal of the mth fourth switch transistor is electrically connected to the first reference signal terminal, the control terminal of the mth fourth switch transistor is electrically connected to the mth pull-down node, and the mth fourth switch transistor is electrically connected to the mth pull-down node. Second ends of the m fourth switching transistors are electrically connected to the pull-up node; The first terminal of the mth fifth switch transistor is electrically connected to the first reference signal terminal, the control terminal of the mth fifth switch transistor is electrically connected to the pull-up node, and the mth fifth switch transistor is electrically connected to the pull-up node. The second end of the fifth switch transistor is electrically connected to the control end of the mth third switch transistor; The first terminal of the mth sixth switch transistor is electrically connected to the first reference signal terminal, the control terminal of the mth sixth switch transistor is electrically connected to the pull-up node, and the mth sixth switch transistor is electrically connected to the pull-up node. the second end of the sixth switch transistor is electrically connected to the mth pull-down node; The size of the mth fifth switch transistor and the mth sixth switch transistor is larger than the size of the mth second switch transistor and the mth third switch transistor; The node control circuit includes: M first switch transistors; wherein, the mth first switch transistor in the M first switch transistors corresponds to the mth pull-down node; The first terminal of the mth first switch transistor is electrically connected to the mth selection control signal terminal, the control terminal of the mth first switch transistor is electrically connected to the reset signal terminal, and the mth first switch transistor is electrically connected to the reset signal terminal. the second end of the first switch transistor is electrically connected to the mth pull-down node; The shift register further includes: an eleventh switch transistor, a first terminal of the eleventh switch transistor is electrically connected to the first reference signal terminal, and a control terminal of the eleventh switch transistor is connected to a frame reset signal The terminal is electrically connected, and the second terminal of the eleventh switch transistor is electrically connected to the pull-up node. 2 . The shift register according to claim 1 , wherein the input circuit comprises a seventh switch transistor, and the first terminal and the control terminal of the seventh switch transistor are both electrically connected to the input signal terminal, 3 . The second end of the seventh switch transistor is electrically connected to the pull-up node. 3. The shift register of claim 1, wherein the reset circuit comprises: an eighth switch transistor; The first terminal of the eighth switch transistor is electrically connected to the first reference signal terminal, the control terminal of the eighth switch transistor is electrically connected to the reset signal terminal, and the second terminal of the eighth switch transistor is electrically connected to the reset signal terminal. The pull-up nodes are electrically connected. 4. The shift register of claim 1, wherein the output circuit comprises: a ninth switch transistor, M tenth switch transistors, and a storage capacitor; wherein, The first terminal of the ninth switch transistor is electrically connected to the clock signal terminal, the control terminal of the ninth switch transistor is electrically connected to the pull-up node, and the second terminal of the ninth switch transistor is electrically connected to the output signal terminal electrical connection; The first terminal of the mth tenth switch transistor among the M tenth switch transistors is electrically connected to the first reference signal terminal, and the control terminal of the mth tenth switch transistor is electrically connected to the mth tenth switch transistor. the pull-down node is electrically connected, and the second terminal of the mth tenth switch transistor is electrically connected to the output signal terminal; The first terminal of the storage capacitor is electrically connected to the pull-up node, and the second terminal of the storage capacitor is electrically connected to the output signal terminal. 5 . The shift register of claim 1 , further comprising a twelfth switch transistor, a first end of the twelfth switch transistor is electrically connected to the first reference signal terminal, and the first end of the twelfth switch transistor is electrically connected to the first reference signal terminal. The control terminal of the twelve switch transistors is electrically connected to the frame reset signal terminal, and the second terminal of the twelfth switch transistor is electrically connected to the output signal terminal. 6. A drive circuit, characterized in that it comprises a plurality of cascaded shift registers as claimed in any one of claims 1-5; The input signal terminal of the first-stage shift register is electrically connected to the frame trigger signal terminal; In each adjacent two-stage shift register, the input signal terminal of the next-stage shift register is electrically connected to the output signal terminal of the previous-stage shift register; In each adjacent two-stage shift register, the output signal terminal of the next-stage shift register is electrically connected to the reset signal terminal of the previous-stage shift register. 7. A display device, comprising the drive circuit according to claim 6. 8. A method for driving a shift register as claimed in any one of claims 1 to 5, wherein the output circuit of the shift register is electrically connected to a clock signal terminal, wherein the method comprises: In the input stage, the input signal terminal is loaded with a first level signal, the reset signal terminal is loaded with a second level signal, and the clock signal terminal is loaded with a second level signal; In the output stage, the input signal terminal is loaded with the second level signal, the reset signal terminal is loaded with the second level signal, and the clock signal terminal is loaded with the first level signal; In the reset stage, the input signal terminal is loaded with a second level signal, the reset signal terminal is loaded with a first level signal, and the clock signal terminal is loaded with a second level signal.

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