CN111177054B

CN111177054B - Data transmission method, device, equipment and storage medium

Info

Publication number: CN111177054B
Application number: CN201911399205.0A
Authority: CN
Inventors: 杨子; 刘永钦; 梅超
Original assignee: Comba Network Systems Co Ltd
Current assignee: Comba Network Systems Co Ltd
Priority date: 2019-12-30
Filing date: 2019-12-30
Publication date: 2021-09-03
Anticipated expiration: 2039-12-30
Also published as: WO2021136099A1; CN111177054A

Abstract

The present application discloses a data transmission method, device, device and storage medium, which belong to the technical field of computers. The method includes: when transferring the first data to the upper computer, generating a first direct memory access instruction, wherein the first direct memory access instruction is used to indicate a source address and a first target address, and the first target address is in the main memory. The address of the first storage space of operation; wherein, the first direct memory access operation includes acquiring the first data from the storage space corresponding to the source address, and transferring the first data to the first storage space according to the first target address. The technical solutions provided by the embodiments of the present application can improve the efficiency of data transmission between the upper computer and the lower computer to a certain extent, and reduce the data transmission delay.

Description

Data transmission method, device, equipment and storage medium

Technical Field

The present application relates to the field of computer technologies, and in particular, to a data transmission method, apparatus, device, and storage medium.

Background

PCIe is a high-speed serial computer expansion bus standard. A typical PCIe bus architecture includes an upper computer, a lower computer (endpoint), a main memory (main memory), a root component (root complex), a switch (switch), and the like.

Data transmission can be carried out between the upper computer and the lower computer, and currently, how to improve the efficiency of data transmission between the upper computer and the lower computer and reduce the data transmission time delay becomes a problem to be solved urgently.

Disclosure of Invention

Based on this, it is necessary to provide a data transmission method, an apparatus, a device, and a storage medium for the problem of improving the efficiency of data transmission between an upper computer and a lower computer and reducing the data transmission delay.

In a first aspect, a data transmission method is provided, which is used in a lower computer of a PCIe bus architecture, where the PCIe bus architecture includes an upper computer, a main memory, and the lower computer, and the data transmission method includes:

generating a first direct memory access instruction when first data are transmitted to the upper computer, wherein the first direct memory access instruction is used for indicating a source address and a first target address, the source address is a storage address of the first data in the lower computer, the first target address is an address of a first storage space in the main memory, and the first storage space is a preset storage space for storing data mutually transmitted by the upper computer and the lower computer through direct memory access operation; executing a first direct memory access operation according to the first direct memory access instruction; the first direct memory access operation includes obtaining the first data from the storage space corresponding to the source address, and transferring the first data to the first storage space according to the first target address.

In one embodiment, the data transmission method further includes:

receiving data downlink indication information sent by the upper computer; generating a second direct memory access instruction according to the indication of the data downlink indication information, wherein the second direct memory access instruction is used for indicating the first target address; executing a second direct memory access operation according to the second direct memory access instruction; the second direct memory access operation comprises acquiring second data from the first storage space and storing the second data into the lower computer.

In one embodiment, the data transmission method further includes:

after the first direct memory access operation or the second direct memory access operation is executed, executing finish information is generated, and the executing finish information is transmitted to a second storage space in the main memory according to a second target address; the second target address is an address of the second storage space, and the second storage space is a preset storage space for storing the execution completion information transmitted by the lower computer.

In one embodiment, before generating the first direct memory access instruction, the data transmission method further includes:

receiving the first target address and the second target address transmitted by the upper computer; the first target address and the second target address are sent by the upper computer after the upper computer sets the first storage space and the second storage space, and the first storage space and the second storage space are set by the upper computer after the upper computer finishes the drive loading of the lower computer.

In one embodiment, the lower computer includes a main controller, a control state adapter and a PCIe HIP element, and receiving the first target address and the second target address transferred by the upper computer includes:

receiving a first bar address write instruction transmitted by the upper computer through the PCIe HIP element, and transmitting the first bar address write instruction to the control state adapter, wherein the first bar address write instruction carries the first target address and the second target address; and converting the first bar address writing instruction into first main controller control information through the control state adapter, and transmitting the first main controller control information to the main controller, wherein the first main controller control information carries the first target address and the second target address.

In one embodiment, generating the first direct memory access instruction includes: generating, by the host controller, the first direct memory access command.

In one embodiment, the lower computer further comprises a user data interface adapter, an uplink data cache and a cache monitoring element; before the generating, by the host controller, the first direct memory access instruction, the data transmission method further includes:

receiving the first data generated by an application layer through the user data interface adapter, and storing the first data to the uplink data cache; and monitoring the uplink data cache through the cache monitoring element, obtaining the storage address of the first data in the uplink data cache through monitoring, taking the storage address of the first data in the uplink data cache as the source address, and transmitting the source address to the main controller.

In one embodiment, performing a first direct memory access operation according to the first direct memory access instruction includes:

transmitting the first direct memory access instruction to the control state adapter through the host controller; converting the first direct memory access instruction into a first PCIe HIP control instruction through the control state adapter; passing the first PCIe HIP control instruction to the PCIe HIP component through the control state adapter; executing, by the PCIe HIP component, the first direct memory access operation according to the first PCIe HIP control instruction.

In one embodiment, the lower computer includes a main controller, a control state adaptor and a PCIe HIP element, and receives the data downlink indication information sent by the upper computer, including:

receiving a second bar address write command transmitted by the upper computer through the PCIe HIP element, and transmitting the second bar address write command to the control state adapter; converting the second bar address write instruction into second host controller control information through the control state adapter, and transferring the second host controller control information to the host controller.

In one embodiment, generating a second dma instruction according to the indication of the data downlink indication information includes: generating, by the host controller, the second direct memory access command.

In one embodiment, executing a second direct memory access operation according to the second direct memory access instruction includes:

transmitting the second DMA command to the control state adapter through the host controller; converting the second direct memory access instruction into a second PCIe HIP control instruction through the control state adapter; passing the second PCIe HIP control instruction to the PCIe HIP component through the control state adapter; executing, by the PCIe HIP component, the second direct memory access operation according to the second PCIe HIP control instruction.

In one embodiment, the lower computer includes a main controller, a control state adaptor and a PCIe HIP element, generates execution completion information, and transfers the execution completion information to a second storage space in the main memory according to a second target address, including:

generating an execution finishing instruction through the PCIe HIP element, and transmitting the execution finishing instruction to the control state adapter; converting the execution finishing instruction into third main controller control information through the control state adapter, and transmitting the third main controller control information to the main controller; generating intermediate execution completion information according to the third main controller control information through the main controller, and transmitting the intermediate execution completion information to the control state adapter; converting the intermediate execution completion information into the execution completion information through the control state adapter, and transmitting the execution completion information to the PCIe HIP component; and transmitting the execution completion information to the second storage space according to the second target address through the PCIe HIP component.

In a second aspect, a data transmission device is provided, and is used in a lower computer of a PCIe bus architecture, where the PCIe bus architecture includes an upper computer, a main memory, and the lower computer, and the data transmission device includes:

the first generation module is used for generating a first direct memory access instruction when first data are transmitted to the upper computer, wherein the first direct memory access instruction is used for indicating a source address and a first target address, the source address is a storage address of the first data in the lower computer, the first target address is an address of a first storage space in the main memory, and the first storage space is a preset storage space used for storing data mutually transmitted by the upper computer and the lower computer through direct memory access operation;

a first execution module, configured to execute a first direct memory access operation according to the first direct memory access instruction; the first direct memory access operation includes obtaining the first data from the storage space corresponding to the source address, and transferring the first data to the first storage space according to the first target address.

In one embodiment, the data transmission apparatus further includes:

the first receiving module is used for receiving the data downlink indication information sent by the upper computer;

a second generating module, configured to generate a second direct memory access instruction according to an indication of the data downlink indication information, where the second direct memory access instruction is used to indicate the first target address;

a second execution module, configured to execute a second direct memory access operation according to the second direct memory access instruction; the second direct memory access operation comprises acquiring second data from the first storage space and storing the second data into the lower computer.

In one embodiment, the data transmission apparatus further includes:

a sending module, configured to generate execution completion information after the first direct memory access operation or the second direct memory access operation is completed, and transmit the execution completion information to a second storage space in the main memory according to a second target address; the second target address is an address of the second storage space, and the second storage space is a preset storage space for storing the execution completion information transmitted by the lower computer.

In one embodiment, the data transmission apparatus further includes:

the second receiving module is used for receiving the first target address and the second target address transmitted by the upper computer; the first target address and the second target address are sent by the upper computer after the upper computer sets the first storage space and the second storage space, and the first storage space and the second storage space are set by the upper computer after the upper computer finishes the drive loading of the lower computer.

In one embodiment, the lower computer includes a main controller, a control state adaptor and a PCIe HIP element, and the second receiving module is specifically configured to:

In one embodiment, the first generating module is specifically configured to: generating, by the host controller, the first direct memory access command.

In one embodiment, the lower computer further comprises a user data interface adapter, an uplink data cache and a cache monitoring element; the data transmission device further includes:

a third receiving module, configured to receive the first data generated by the application layer through the user data interface adapter, and store the first data in the uplink data cache;

and the monitoring module is used for monitoring the uplink data cache through the cache monitoring element, obtaining the storage address of the first data in the uplink data cache through monitoring, taking the storage address of the first data in the uplink data cache as the source address, and transmitting the source address to the main controller.

In one embodiment, the first execution module is specifically configured to: transmitting the first direct memory access instruction to the control state adapter through the host controller; converting the first direct memory access instruction into a first PCIe HIP control instruction through the control state adapter; passing the first PCIe HIP control instruction to the PCIe HIP component through the control state adapter; executing, by the PCIe HIP component, the first direct memory access operation according to the first PCIe HIP control instruction.

In one embodiment, the lower computer includes a main controller, a control state adaptor and a PCIe HIP element, and the first receiving module is specifically configured to: receiving a second bar address write command transmitted by the upper computer through the PCIe HIP element, and transmitting the second bar address write command to the control state adapter; converting the second bar address write instruction into second host controller control information through the control state adapter, and transferring the second host controller control information to the host controller.

In one embodiment, the second generating module is specifically configured to generate the second direct memory access instruction through the host controller.

In one embodiment, the second execution module is specifically configured to: transmitting the second DMA command to the control state adapter through the host controller; converting the second direct memory access instruction into a second PCIe HIP control instruction through the control state adapter; passing the second PCIe HIP control instruction to the PCIe HIP component through the control state adapter; executing, by the PCIe HIP component, the second direct memory access operation according to the second PCIe HIP control instruction.

In one embodiment, the lower computer includes a main controller, a control state adaptor, and a PCIe HIP element, and the sending module is specifically configured to: generating an execution finishing instruction through the PCIe HIP element, and transmitting the execution finishing instruction to the control state adapter; converting the execution finishing instruction into third main controller control information through the control state adapter, and transmitting the third main controller control information to the main controller; generating intermediate execution completion information according to the third main controller control information through the main controller, and transmitting the intermediate execution completion information to the control state adapter; converting the intermediate execution completion information into the execution completion information through the control state adapter, and transmitting the execution completion information to the PCIe HIP component; and transmitting the execution completion information to the second storage space according to the second target address through the PCIe HIP component.

In a third aspect, a computer device is provided, comprising a memory and a processor, the memory storing a computer program which, when executed by the processor, implements the data transmission method as described in any of the first aspects above.

In a fourth aspect, there is provided a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a data transmission method as described in any one of the first aspects above.

The beneficial effects brought by the technical scheme provided by the embodiment of the application at least comprise:

when the lower computer of the PCIe bus architecture transmits first data to the upper computer, it may generate a first direct memory access instruction, and execute a first direct memory access operation according to the first direct memory access instruction, so as to transmit the first data from the lower computer to a first storage space of the main memory through the first direct memory access operation, where the first storage space is a preset storage space for storing data mutually transmitted by the upper computer and the lower computer through the direct memory access operation, and since the first storage space for storing data mutually transmitted by the upper computer and the lower computer through the direct memory access operation in the main memory is preset, an address of a storage space capable of storing data transmitted by the lower computer in the main memory is not required to be obtained by the upper computer in a system call manner in a process of transmitting the first data to the upper computer, that is, in a process of transmitting uplink data, the first storage space is preset, so that the lower computer can acquire the address of the first storage space in advance, and the upper computer is not required to send the address to the lower computer in the uplink data transmission process, so that the interaction flow between the upper computer and the lower computer in the uplink data transmission process can be simplified, the time delay of the uplink data transmission can be reduced, and the efficiency of the uplink data transmission can be improved.

Drawings

FIG. 1 is a schematic diagram of a typical PCIe bus architecture.

Fig. 2 is a schematic structural diagram of a lower computer according to an embodiment of the present disclosure;

fig. 3 is a flowchart of a data transmission method according to an embodiment of the present application;

fig. 4 is a flowchart of a data transmission method according to an embodiment of the present application;

fig. 5 is a flowchart of a data transmission method according to an embodiment of the present application;

fig. 6 is a flowchart of a data transmission method according to an embodiment of the present application;

fig. 7 is a block diagram of a data transmission apparatus according to an embodiment of the present application;

fig. 8 is a block diagram of another data transmission apparatus according to an embodiment of the present application.

Detailed Description

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

PCIe (peripheral component interconnect express) is a high-speed serial computer expansion bus standard.

Referring to fig. 1, a schematic diagram of a typical PCIe bus architecture is shown, as shown in fig. 1, the PCIe bus architecture may include an upper computer 00, a lower computer 01, a main memory 03, a root element 04, and a switch 05. The upper computer 00, the main memory 03 and the switch 05 are all connected to the root element 04, and the lower computer 01 is connected to the switch 05. The upper computer 00 can store data in the main memory 03 through a multi-level cache mechanism, and the upper computer 00 can access the main memory 03 through the root component 04; meanwhile, the lower computer 01 can access the main memory 03 through the switch 05 and the root element 04.

In practical applications, the upper computer 00 in the PCIe bus architecture may be a CPU (central processing unit; chinese: central processing unit), and the lower computer 01 may also be called a terminal (PCIe endpoint), which may be an FPGA (Field Programmable Gate Array) chip.

In general, data transmission may be performed between an upper computer and a lower computer in a PCIe architecture, where the data transmission between the upper computer and the lower computer in the PCIe architecture may include uplink data transmission and downlink data transmission. The uplink data transmission refers to the lower computer transmitting data to the upper computer, in the uplink data transmission, the data are transferred to the main memory from the storage space of the lower computer, the downlink data transmission refers to the upper computer transmitting the data to the lower computer, and in the downlink data transmission, the data are transferred to the storage space of the lower computer from the main memory.

In the process of uplink data transmission, the upper computer needs to acquire an address (hereinafter referred to as a first address) of a storage space capable of storing data transmitted by the lower computer in the main memory in a system call mode, then the upper computer can trigger the lower computer to execute the transmission process of the uplink data, and send the first address to the lower computer in the triggering process, and after receiving the first address, the lower computer can transfer the data stored in the lower computer to the storage space of the main memory corresponding to the first address.

In the process of downlink data transmission, the upper computer needs to acquire an address (hereinafter referred to as a second address) of a storage space in the main memory, where data to be transmitted is stored, in a system call manner, and then the upper computer can send the second address to the lower computer, and after receiving the second address, the lower computer can acquire the data to be transmitted from the storage space of the main memory corresponding to the second address and store the data to be transmitted into the storage space of the lower computer.

As can be seen from the above description, in the transmission process of the uplink data and the downlink data, the upper computer needs to send address information (the first address and the second address described above) to the lower computer, which results in a complicated interaction flow between the upper computer and the lower computer in the transmission process of the uplink data and the downlink data, and thus, the time delay of data transmission is long, and the transmission efficiency of data is affected.

In view of this, embodiments of the present application provide a data transmission method, which may simplify an interaction flow between an upper computer and a lower computer in a data transmission process, reduce data transmission delay, and improve data transmission efficiency.

In the following, the structure of the lower computer will be briefly described by taking the lower computer as an FPGA as an example, and referring to fig. 2, the lower computer may include a main controller (english: main controller), a control state adapter (english: control and status adapter), a PCIe HIP element, a user data interface adapter (english: user logic data adapter), a cache monitor element (buffer monitor), an uplink data cache (english: uplink buffer), a downlink data cache (english: downlink buffer), a PCIe HIP data interface adapter (PCIe: HIP adapter), and a driver.

The main controller is used for providing processing and control functions, for example, the main controller can control the lower computer to perform data interaction with the upper computer and the like.

The control state adapter is used to adapt data interaction between the host controller and the PCIe HIP element. In many cases, the PCIe HIP element generally cannot directly parse data generated by the host controller, and meanwhile, the host controller also generally cannot directly parse data generated by the PCIe HIP element, so to implement data interaction between the host controller and the PCIe HIP element, in this embodiment of the present application, a control state adaptor may be set, and the control state adaptor may adapt to the data generated by the PCIe HIP element, so as to enable the host controller to parse the data generated by the PCIe HIP element through adaptation, and in addition, the control state adaptor may also adapt to the data generated by the host controller, so as to enable the PCIe HIP element to parse the data generated by the host controller through adaptation.

It should be noted that the adaptation between the host controller and the control state adapter does not change with the change of the lower computer platform, and therefore, when the technical solution provided in the embodiment of the present application is deployed on a different lower computer platform (for example, Xilinx or Intel), the adaptation between the host controller and the control state adapter does not need to be modified.

The PCIe HIP component can execute data interaction between the lower computer and the upper computer under the control of the main controller.

The user data interface adapter is a cache interface of the lower computer, can receive data generated by the application layer and store the data in the uplink data cache, and meanwhile, the user data interface adapter can also transmit the data stored in the downlink data cache to the application layer.

The uplink data cache is used for storing data generated by the application layer, and in the data transmission process, the lower computer can transmit the data stored in the uplink data cache to the upper computer (namely, the main memory). The downlink data cache is used for storing data sent by the upper computer.

The buffer monitoring element may monitor the status of the uplink data buffer and the downlink data buffer.

The PCIe HIP data interface adapter is used for adapting data interaction among the PCIe HIP element, the uplink data cache and the downlink data cache so as to provide a data transmission channel among the PCIe HIP element, the uplink data cache and the downlink data cache.

Referring to fig. 3, a flowchart of a data transmission method provided in an embodiment of the present application is shown, where the data transmission method may be applied to a lower computer of a PCIe bus architecture, and as shown in fig. 3, the data transmission method may include the following steps:

step 101, when the first data is transmitted to the upper computer, the lower computer generates a first direct memory access instruction.

In the process of uplink data transmission, that is, in the process of transmitting the first data to the upper computer, the lower computer may generate the first direct memory access instruction. The first direct memory access instruction can indicate a source address and a first target address, the source address refers to a storage address of first data in the lower computer, that is, the source address refers to an address of the first data stored in an uplink data cache of the lower computer, the first target address refers to an address of a first storage space in a main memory, the first storage space is a preset storage space used for storing data mutually transmitted by the upper computer and the lower computer through Direct Memory Access (DMA), and the direct memory access operation refers to a technology of directly transmitting the data from one storage space to another storage space without a CPU.

It should be noted that the source address and the first destination address are address fields, and the address field includes the start address of the memory space and the offset size of the memory space.

In an optional embodiment of the present application, the cache monitoring element in the lower computer may monitor an uplink data cache of the lower computer, and when the cache monitoring element monitors that data is stored in the uplink data cache, the cache monitoring element may send uplink data cache state information to the main controller, where the uplink data cache state information is used to indicate that data is stored in the uplink data cache, and after receiving the uplink data cache state information, the main controller may generate the first direct memory access instruction.

And 102, executing a first direct memory access operation by the lower computer according to the first direct memory access instruction.

The first direct memory access operation comprises the steps of obtaining first data from a storage space corresponding to a source address and transmitting the first data to a first storage space of the main memory according to a first target address.

As described above, in an optional embodiment of the present application, the host controller may generate the first direct memory access instruction, after the first direct memory access instruction is generated, the host controller may transmit the first direct memory access instruction to the control state adapter, the control state adapter may convert the first direct memory access instruction into a first PCIe HIP control instruction, where the first PCIe HIP control instruction is an instruction that the PCIe HIP element can directly parse, and then the control state adapter may transmit the first PCIe HIP control instruction to the PCIe HIP element, and the PCIe HIP element may perform the first direct memory access operation according to the first PCIe HIP control instruction.

In summary, in the data transmission method provided in this embodiment of the present application, when a lower computer of a PCIe bus architecture transmits first data to an upper computer, a first direct memory access instruction may be generated, and a first direct memory access operation is executed according to the first direct memory access instruction, so that the first data is transmitted from the lower computer to a first storage space of a main memory through the first direct memory access operation, where the first storage space is a preset storage space for storing data mutually transmitted by the upper computer and the lower computer through the direct memory access operation, and since the first storage space for storing data mutually transmitted by the upper computer and the lower computer through the direct memory access operation in the main memory is preset, in a process of transmitting the first data to the upper computer by the lower computer, that is, in a process of performing uplink data transmission, the upper computer is not required to acquire the address of the storage space capable of storing the data transmitted by the lower computer in the main memory in a system calling mode, and the first storage space is preset, so that the lower computer can acquire the address of the first storage space in advance, and the upper computer is not required to send the address to the lower computer in the uplink data transmission process, so that the interactive flow between the upper computer and the lower computer in the uplink data transmission process can be simplified, the time delay of the uplink data transmission can be reduced, and the efficiency of the uplink data transmission is improved.

In addition, in the embodiment of the application, the upper computer does not need to send the address to the lower computer in the transmission process of the uplink data, so that the transmission of the uplink data in the embodiment of the application can be started by the lower computer independently without being triggered by the upper computer, the flexibility of the transmission of the uplink data can be improved, and the time delay of the transmission of the uplink data is further reduced.

Referring to fig. 4, on the basis of the above-mentioned embodiment, the data transmission method provided in the embodiment of the present application may further include the following steps:

step 201, the lower computer receives the first data generated by the application layer through the user data interface adapter, and stores the first data into the uplink data cache.

Step 202, the lower computer monitors the uplink data cache through the cache monitoring element, obtains the storage address of the first data in the uplink data cache through monitoring, takes the storage address of the first data in the uplink data cache as a source address, and transmits the source address to the main controller.

Through the technical processes of step 201 and step 202, the host controller may obtain the source address, and then, the host controller may generate the first direct memory access instruction according to the source address.

Referring to fig. 5, on the basis of the above-mentioned embodiment, the data transmission method provided in the embodiment of the present application may further include the following steps:

and step 301, the lower computer receives the data downlink indication information sent by the upper computer.

As described above, the data transmission between the upper computer and the lower computer may include uplink data transmission and downlink data transmission, and in steps 301 to 303, the process of downlink data transmission will be described in this embodiment of the application.

In the process of downlink data transmission, the upper computer can store second data (data to be transmitted in a downlink mode) into the first storage space of the main memory, and then the upper computer can generate downlink data indication information and send the downlink data indication information to the lower computer. The data downlink indication information is used for triggering the lower computer to perform downlink data transmission.

In an optional embodiment of the present application, the data downlink indication information may be a second bar address write instruction, in a downlink data transmission process, a PCIe HIP element in the lower computer may receive the second bar address write instruction transmitted by the upper computer, and transmit the second bar address write instruction to the control state adaptor, and the control state adaptor may convert the second bar address write instruction into second host controller control information, where the second host controller control information is information that can be directly analyzed by the host controller, and then the control state adaptor may transmit the second host controller control information to the host controller. Therefore, the lower computer realizes the receiving of the data downlink indication information.

And step 302, the lower computer generates a second direct memory access instruction according to the indication of the data downlink indication information.

Wherein the second dma instruction is used to indicate the first target address described above.

In an optional embodiment of the present application, the host controller may generate the second dma command after receiving the second host controller control information.

And step 303, the lower computer executes a second direct memory access operation according to the second direct memory access instruction.

And optionally, the second direct memory access operation can store the second data into a downlink data cache of the lower computer.

As described above, in an optional embodiment of the present application, the host controller may generate the second direct memory access instruction, after the second direct memory access instruction is generated, the host controller may transmit the second direct memory access instruction to the control state adapter, the control state adapter may convert the second direct memory access instruction into a second PCIe HIP control instruction, the second PCIe HIP control instruction is an instruction that the PCIe HIP element can directly parse, and then the control state adapter may transmit the second PCIe HIP control instruction to the PCIe HIP element, and the PCIe HIP element may perform a second direct memory access operation according to the second PCIe HIP control instruction.

In summary, in the data transmission method provided in this embodiment of the present application, the lower computer of the PCIe architecture can receive the data downlink indication information transmitted by the upper computer, generate the second direct memory access instruction according to the indication of the data downlink indication information, then execute the second direct memory access operation according to the second direct memory access instruction, so as to transmit the second data from the first storage space of the main memory to the lower computer through the second direct memory access operation, where the first storage space is a preset storage space for storing data mutually transmitted by the upper computer and the lower computer through the direct memory access operation, and since the first storage space for storing data mutually transmitted by the upper computer and the lower computer through the direct memory access operation in the main memory is preset, in the process of transmitting the second data by the upper computer to the lower computer, that is, in the process of downlink data transmission, the upper computer is not required to acquire the address of the storage space in the main memory, which stores the data (i.e., the second data) to be transmitted, in a system call manner, and since the first storage space is preset, the lower computer can acquire the address of the first storage space in advance, so that in the process of downlink data transmission, the upper computer is not required to send the address to the lower computer, and thus, the interactive flow between the upper computer and the lower computer in the downlink data transmission process can be simplified, the delay of downlink data transmission can be reduced, and the efficiency of downlink data transmission can be improved.

Referring to fig. 6, on the basis of the above-mentioned embodiment, the data transmission method provided in the embodiment of the present application may further include the following steps:

step 401, after the first direct memory access operation or the second direct memory access operation is executed, the lower computer generates execution completion information.

Optionally, in an embodiment of the present application, since the PCIe HIP element executes the first direct memory access operation and the second direct memory access operation, after the first direct memory access operation or the second direct memory access operation is completed, the PCIe HIP element may generate an execution completion instruction and transmit the execution completion instruction to the control state adaptor, the control state adaptor may convert the execution completion instruction into third host controller control information, where the third host controller control information is information that can be directly analyzed by the host controller, and then the control state adaptor may transmit the third host controller control information to the host controller, and the host controller may generate intermediate execution completion information according to the third host controller control information and transmit the intermediate execution completion information to the control state adaptor, the control state adapter can convert the intermediate execution finishing information into execution finishing information, wherein the execution finishing information is information which can be directly analyzed by the PCIe HIP component, and then the control state adapter can transmit the execution finishing information to the PCIe HIP component, so that the lower computer finishes the generation process of the execution finishing information.

Step 402, the lower computer transmits the execution completion information to a second storage space in the main memory according to the second target address.

The second target address is an address of a second storage space, the second storage space is a preset storage space for storing the execution completion information transmitted by the lower computer, and the second target address may also be an address field, which may include a start address of the storage space and an offset size of the storage space.

After the control state adapter passes the done message to the PCIe HIP component, the PCIe HIP component may pass the done message to the second storage space according to the second destination address.

The upper computer can check the second storage space when needed to determine whether the uplink data transmission or the downlink data transmission is finished through the execution finishing information in the second storage space.

For example, when the upper computer needs to perform downlink data transmission, the upper computer may check the second storage space to determine whether the lower computer has a first direct memory access operation or a second direct memory access operation that is not performed, and when it is determined that the lower computer does not have the first direct memory access operation or the second direct memory access operation that is not performed, the upper computer may perform downlink data transmission, thereby avoiding occurrence of a situation that the lower computer performs two direct memory access operations at the same time, and further avoiding system abnormality.

For another example, when the upper computer needs to use the data transmitted by the lower computer, the upper computer may check the second storage space to determine whether the lower computer has performed the first direct memory access operation, and when it is determined that the lower computer has performed the first direct memory access operation, it is described that the lower computer has completely transmitted the data to the main memory, and at this time, the upper computer may normally use the data transmitted by the lower computer.

For another example, when the upper computer needs to store data in the first storage space of the main memory, the second storage space may be checked to determine whether the lower computer has performed the second direct memory access operation, and when it is determined that the lower computer has performed the second direct memory access operation, it is described that the data in the first storage space has been completely transferred to the lower computer.

In an embodiment of the present application, the upper computer may be a multi-core CPU, in which case, one CPU may be used to monitor the second storage space in real time, and at this time, the upper computer may not only view the second storage space when needed, but also view the second storage space in real time.

On the basis of the above embodiments, the data transmission method provided in the embodiments of the present application may further include the following steps:

and the lower computer receives the first target address and the second target address transmitted by the upper computer.

Optionally, in an embodiment of the present application, a PCIe HIP element in the lower computer may receive a first bar address write instruction transmitted by the upper computer, and transmit the first bar address write instruction to the control state adapter, where the first bar address write instruction carries a first target address and a second target address, and then the control state adapter may convert the first bar address write instruction into first host controller control information, where the first host controller control information is information that can be directly resolved by the host controller, and then the control state adapter may transmit the first host controller control information to the host controller, where the first host controller control information carries the first target address and the second target address. Therefore, the lower computer receives the first target address and the second target address transmitted by the upper computer.

The first target address and the second target address are sent by the upper computer after the upper computer sets the first storage space and the second storage space, and the first storage space and the second storage space are set by the upper computer after the upper computer finishes the drive loading of the lower computer.

It should be noted that the data transmission method provided in the embodiment of the present application may be applied to a PCIe bus architecture deployed in a 5G base station (e.g., a 5G indoor base station), where in the 5G base station, the upper computer may be a CPU, the lower computer may be an FPGA, the CPU may process L2 and L3 protocols by using its own general computing capability, and the FPGA may process an L1 protocol by using its own parallel processing capability.

In the 5G base station, service data or operation, maintenance and management data (OAM for short) can be transmitted between an upper computer and a lower computer.

Referring to fig. 7, a block diagram of a data transmission device 700 according to an embodiment of the present application is shown, where the data transmission device 700 may be configured in the lower computer described above. As shown in fig. 7, the data transmission apparatus 700 may include: a first generation module 701 and a first execution module 702.

The first generating module 701 is configured to generate a first direct memory access instruction when first data is transferred to an upper computer, where the first direct memory access instruction is used to indicate a source address and a first target address, the source address is a storage address of the first data in the lower computer, the first target address is an address of a first storage space in the main memory, and the first storage space is a preset storage space used for storing data mutually transferred by the upper computer and the lower computer through a direct memory access operation.

The first executing module 702 is configured to execute a first direct memory access operation according to the first direct memory access instruction; the first direct memory access operation includes obtaining the first data from the storage space corresponding to the source address, and transferring the first data to the first storage space according to the first target address.

In an embodiment of the present application, the first generating module 701 is specifically configured to: the first direct memory access instruction is generated by a host controller.

In an embodiment of the present application, the first executing module 702 is specifically configured to: transmitting the first direct memory access instruction to a control state adapter through a host controller; converting the first direct memory access instruction into a first PCIe HIP control instruction through the control state adapter; passing the first PCIe HIP control instruction to a PCIe HIP component through the control state adapter; executing, by the PCIe HIP component, the first direct memory access operation according to the first PCIe HIP control instruction.

Referring to fig. 8, an embodiment of the present application further provides another data transmission apparatus 800, where the data transmission apparatus 800 includes, in addition to the modules included in the data transmission apparatus 700, optionally, the data transmission apparatus 800 may further include a first receiving module 703, a second generating module 704, a second executing module 705, a sending module 706, a second receiving module 707, a third receiving module 708, and a monitoring module 709.

The first receiving module 703 is configured to receive downlink data indication information sent by the upper computer.

The second generating module 704 is configured to generate a second direct memory access instruction according to the indication of the data downlink indication information, where the second direct memory access instruction is used to indicate the first target address.

The second executing module 705, configured to execute a second direct memory access operation according to the second direct memory access instruction; the second direct memory access operation comprises acquiring second data from the first storage space and storing the second data into the lower computer.

The sending module 706 is configured to generate execution completion information after the first direct memory access operation or the second direct memory access operation is completed, and transmit the execution completion information to a second storage space in the main memory according to a second target address; the second target address is an address of the second storage space, and the second storage space is a preset storage space for storing the execution completion information transmitted by the lower computer.

The second receiving module 707, configured to receive the first target address and the second target address transmitted by the upper computer; the first target address and the second target address are sent by the upper computer after the upper computer sets the first storage space and the second storage space, and the first storage space and the second storage space are set by the upper computer after the upper computer finishes the drive loading of the lower computer.

The second receiving module 707 is specifically configured to: receiving a first bar address write instruction transmitted by the upper computer through the PCIe HIP element, and transmitting the first bar address write instruction to the control state adapter, wherein the first bar address write instruction carries the first target address and the second target address; and converting the first bar address writing instruction into first main controller control information through the control state adapter, and transmitting the first main controller control information to the main controller, wherein the first main controller control information carries the first target address and the second target address.

The third receiving module 708 is configured to receive the first data generated by the application layer through the user data interface adapter, and store the first data in the uplink data buffer.

The monitoring module 709 is configured to monitor the uplink data cache through the cache monitoring element, obtain a storage address of the first data in the uplink data cache through monitoring, use the storage address of the first data in the uplink data cache as the source address, and transmit the source address to the host controller.

The first receiving module 703 is specifically configured to: receiving a second bar address write command transmitted by the upper computer through a PCIe HIP element, and transmitting the second bar address write command to the control state adapter; converting the second bar address write instruction into second host controller control information through the control state adapter, and transferring the second host controller control information to the host controller.

The second generating module 704 is specifically configured to generate the second dma instruction through the host controller.

The second executing module 705 is specifically configured to: transmitting the second DMA command to the control state adapter through the host controller; converting the second direct memory access instruction into a second PCIe HIP control instruction through the control state adapter; passing the second PCIe HIP control instruction to the PCIe HIP component through the control state adapter; executing, by the PCIe HIP component, the second direct memory access operation according to the second PCIe HIP control instruction.

The sending module 706 is specifically configured to: generating an execution finishing instruction through the PCIe HIP element, and transmitting the execution finishing instruction to the control state adapter; converting the execution finishing instruction into third main controller control information through the control state adapter, and transmitting the third main controller control information to the main controller; generating intermediate execution completion information according to the third main controller control information through the main controller, and transmitting the intermediate execution completion information to the control state adapter; converting the intermediate execution completion information into the execution completion information through the control state adapter, and transmitting the execution completion information to the PCIe HIP component; and transmitting the execution completion information to the second storage space according to the second target address through the PCIe HIP component.

The apparatus for determining the CPU utilization provided in the embodiment of the present application can implement the method embodiment, and the implementation principle and the technical effect are similar, which are not described herein again.

For specific limitations of determining the data transmission device, reference may be made to the above limitations for determining the data transmission method, which are not described herein again. The various modules in the above-described deterministic data transmission apparatus may be implemented in whole or in part by software, hardware, and combinations thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.

In one embodiment of the present application, there is provided a computer device comprising a memory and a processor, the memory having stored therein a computer program, the processor implementing the following steps when executing the computer program:

when first data are transmitted to an upper computer, a first direct memory access instruction is generated, wherein the first direct memory access instruction is used for indicating a source address and a first target address, the source address is a storage address of the first data in the lower computer, the first target address is an address of a first storage space in the main memory, and the first storage space is a preset storage space used for storing data mutually transmitted by the upper computer and the lower computer through direct memory access operation; executing a first direct memory access operation according to the first direct memory access instruction; the first direct memory access operation includes obtaining the first data from the storage space corresponding to the source address, and transferring the first data to the first storage space according to the first target address.

In one embodiment of the application, the processor when executing the computer program further performs the steps of: receiving data downlink indication information sent by the upper computer; generating a second direct memory access instruction according to the indication of the data downlink indication information, wherein the second direct memory access instruction is used for indicating the first target address; executing a second direct memory access operation according to the second direct memory access instruction; the second direct memory access operation comprises acquiring second data from the first storage space and storing the second data into the lower computer.

In one embodiment of the application, the processor when executing the computer program further performs the steps of: after the first direct memory access operation or the second direct memory access operation is executed, executing finish information is generated, and the executing finish information is transmitted to a second storage space in the main memory according to a second target address; the second target address is an address of the second storage space, and the second storage space is a preset storage space for storing the execution completion information transmitted by the lower computer.

In one embodiment of the application, the processor when executing the computer program further performs the steps of: receiving the first target address and the second target address transmitted by the upper computer; the first target address and the second target address are sent by the upper computer after the upper computer sets the first storage space and the second storage space, and the first storage space and the second storage space are set by the upper computer after the upper computer finishes the drive loading of the lower computer.

The lower computer comprises a main controller, a control state adapter and a PCIe HIP element, and in one embodiment of the application, the processor executes the computer program to further realize the following steps: receiving a first bar address write instruction transmitted by the upper computer through the PCIe HIP element, and transmitting the first bar address write instruction to the control state adapter, wherein the first bar address write instruction carries the first target address and the second target address; and converting the first bar address writing instruction into first main controller control information through the control state adapter, and transmitting the first main controller control information to the main controller, wherein the first main controller control information carries the first target address and the second target address.

In one embodiment of the application, the processor when executing the computer program further performs the steps of: generating, by the host controller, the first direct memory access command.

The lower computer further includes a user data interface adapter, an uplink data cache, and a cache monitoring element, and in an embodiment of the present application, the processor further implements the following steps when executing the computer program: receiving the first data generated by an application layer through the user data interface adapter, and storing the first data to the uplink data cache; and monitoring the uplink data cache through the cache monitoring element, obtaining the storage address of the first data in the uplink data cache through monitoring, taking the storage address of the first data in the uplink data cache as the source address, and transmitting the source address to the main controller.

In one embodiment of the application, the processor when executing the computer program further performs the steps of: transmitting the first direct memory access instruction to the control state adapter through the host controller; converting the first direct memory access instruction into a first PCIe HIP control instruction through the control state adapter; passing the first PCIe HIP control instruction to the PCIe HIP component through the control state adapter; executing, by the PCIe HIP component, the first direct memory access operation according to the first PCIe HIP control instruction.

The lower computer comprises a main controller, a control state adapter and a PCIe HIP element, and in one embodiment of the application, the processor executes the computer program to further realize the following steps: receiving a second bar address write command transmitted by the upper computer through the PCIe HIP element, and transmitting the second bar address write command to the control state adapter; converting the second bar address write instruction into second host controller control information through the control state adapter, and transferring the second host controller control information to the host controller.

In one embodiment of the application, the processor when executing the computer program further performs the steps of: generating, by the host controller, the second direct memory access command.

In one embodiment of the application, the processor when executing the computer program further performs the steps of: transmitting the second DMA command to the control state adapter through the host controller; converting the second direct memory access instruction into a second PCIe HIP control instruction through the control state adapter; passing the second PCIe HIP control instruction to the PCIe HIP component through the control state adapter; executing, by the PCIe HIP component, the second direct memory access operation according to the second PCIe HIP control instruction.

The lower computer comprises a main controller, a control state adapter and a PCIe HIP element, and in one embodiment of the application, the processor executes the computer program to further realize the following steps: generating an execution finishing instruction through the PCIe HIP element, and transmitting the execution finishing instruction to the control state adapter; converting the execution finishing instruction into third main controller control information through the control state adapter, and transmitting the third main controller control information to the main controller; generating intermediate execution completion information according to the third main controller control information through the main controller, and transmitting the intermediate execution completion information to the control state adapter; converting the intermediate execution completion information into the execution completion information through the control state adapter, and transmitting the execution completion information to the PCIe HIP component; and transmitting the execution completion information to the second storage space according to the second target address through the PCIe HIP component.

The implementation principle and technical effect of the computer device provided by the embodiment of the present application are similar to those of the method embodiment described above, and are not described herein again.

In an embodiment of the application, a computer-readable storage medium is provided, on which a computer program is stored, which computer program, when being executed by a processor, carries out the steps of:

In one embodiment of the application, the computer program when executed by the processor further performs the steps of: receiving data downlink indication information sent by the upper computer; generating a second direct memory access instruction according to the indication of the data downlink indication information, wherein the second direct memory access instruction is used for indicating the first target address; executing a second direct memory access operation according to the second direct memory access instruction; the second direct memory access operation comprises acquiring second data from the first storage space and storing the second data into the lower computer.

In one embodiment of the application, the computer program when executed by the processor further performs the steps of: after the first direct memory access operation or the second direct memory access operation is executed, executing finish information is generated, and the executing finish information is transmitted to a second storage space in the main memory according to a second target address; the second target address is an address of the second storage space, and the second storage space is a preset storage space for storing the execution completion information transmitted by the lower computer.

In one embodiment of the application, the computer program when executed by the processor further performs the steps of: receiving the first target address and the second target address transmitted by the upper computer; the first target address and the second target address are sent by the upper computer after the upper computer sets the first storage space and the second storage space, and the first storage space and the second storage space are set by the upper computer after the upper computer finishes the drive loading of the lower computer.

The lower computer comprises a host controller, a control state adaptor and a PCIe HIP element, and in one embodiment of the application, the computer program when executed by the processor further implements the steps of: receiving a first bar address write instruction transmitted by the upper computer through the PCIe HIP element, and transmitting the first bar address write instruction to the control state adapter, wherein the first bar address write instruction carries the first target address and the second target address; and converting the first bar address writing instruction into first main controller control information through the control state adapter, and transmitting the first main controller control information to the main controller, wherein the first main controller control information carries the first target address and the second target address.

In one embodiment of the application, the computer program when executed by the processor further performs the steps of: generating, by the host controller, the first direct memory access command.

The lower computer further comprises a user data interface adapter, an uplink data cache and a cache monitoring element, and in one embodiment of the application, the computer program when executed by the processor further implements the steps of: receiving the first data generated by an application layer through the user data interface adapter, and storing the first data to the uplink data cache; and monitoring the uplink data cache through the cache monitoring element, obtaining the storage address of the first data in the uplink data cache through monitoring, taking the storage address of the first data in the uplink data cache as the source address, and transmitting the source address to the main controller.

In one embodiment of the application, the computer program when executed by the processor further performs the steps of: transmitting the first direct memory access instruction to the control state adapter through the host controller; converting the first direct memory access instruction into a first PCIe HIP control instruction through the control state adapter; passing the first PCIe HIP control instruction to the PCIe HIP component through the control state adapter; executing, by the PCIe HIP component, the first direct memory access operation according to the first PCIe HIP control instruction.

The lower computer comprises a host controller, a control state adaptor and a PCIe HIP element, and in one embodiment of the application, the computer program when executed by the processor further implements the steps of: receiving a second bar address write command transmitted by the upper computer through the PCIe HIP element, and transmitting the second bar address write command to the control state adapter; converting the second bar address write instruction into second host controller control information through the control state adapter, and transferring the second host controller control information to the host controller.

In one embodiment of the application, the computer program when executed by the processor further performs the steps of: generating, by the host controller, the second direct memory access command.

In one embodiment of the application, the computer program when executed by the processor further performs the steps of: transmitting the second DMA command to the control state adapter through the host controller; converting the second direct memory access instruction into a second PCIe HIP control instruction through the control state adapter; passing the second PCIe HIP control instruction to the PCIe HIP component through the control state adapter; executing, by the PCIe HIP component, the second direct memory access operation according to the second PCIe HIP control instruction.

The lower computer comprises a host controller, a control state adaptor and a PCIe HIP element, and in one embodiment of the application, the computer program when executed by the processor further implements the steps of: generating an execution finishing instruction through the PCIe HIP element, and transmitting the execution finishing instruction to the control state adapter; converting the execution finishing instruction into third main controller control information through the control state adapter, and transmitting the third main controller control information to the main controller; generating intermediate execution completion information according to the third main controller control information through the main controller, and transmitting the intermediate execution completion information to the control state adapter; converting the intermediate execution completion information into the execution completion information through the control state adapter, and transmitting the execution completion information to the PCIe HIP component; and transmitting the execution completion information to the second storage space according to the second target address through the PCIe HIP component.

The implementation principle and technical effect of the computer-readable storage medium provided by this embodiment are similar to those of the above-described method embodiment, and are not described herein again.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A data transmission method is used in a lower computer of a PCIe bus architecture, the PCIe bus architecture comprises an upper computer, a main memory and the lower computer, and the data transmission method comprises the following steps:

receiving a first target address transmitted by the upper computer, wherein the first target address is transmitted after the upper computer sets a first storage space, the first storage space is set after the upper computer finishes driving and loading on the lower computer, the first target address is an address of the first storage space in the main memory, and the first storage space is a preset storage space for storing data mutually transmitted by the upper computer and the lower computer through direct memory access operation;

generating a first direct memory access instruction when first data are transmitted to the upper computer, wherein the first direct memory access instruction is used for indicating a source address and the first target address, and the source address is a storage address of the first data in the lower computer;

executing a first direct memory access operation according to the first direct memory access instruction;

the first direct memory access operation comprises the steps of obtaining the first data from a storage space corresponding to the source address and transmitting the first data to the first storage space according to the first target address.

2. The data transmission method according to claim 1, wherein the data transmission method further comprises:

receiving data downlink indication information sent by the upper computer;

generating a second direct memory access instruction according to the indication of the data downlink indication information, wherein the second direct memory access instruction is used for indicating the first target address;

executing a second direct memory access operation according to the second direct memory access instruction;

and the second direct memory access operation comprises the steps of acquiring second data from the first storage space and storing the second data into the lower computer.

3. The data transmission method according to claim 2, wherein the data transmission method further comprises:

after the first direct memory access operation or the second direct memory access operation is executed, executing finish information is generated, and the executing finish information is transmitted to a second storage space in the main memory according to a second target address;

the second target address is an address of the second storage space, and the second storage space is a preset storage space for storing the execution completion information transmitted by the lower computer.

4. The data transmission method according to claim 3, wherein before the generating the first direct memory access command, the data transmission method further comprises:

receiving the second target address transmitted by the upper computer;

the second target address is sent after the upper computer sets the second storage space, and the second storage space is set after the upper computer finishes driving and loading of the lower computer.

5. The data transmission method according to claim 4, wherein the lower computer comprises a main controller, a control state adapter and a PCIe HIP element, and the receiving the first target address and the second target address transmitted by the upper computer comprises:

receiving a first bar address write instruction transmitted by the upper computer through the PCIe HIP element, and transmitting the first bar address write instruction to the control state adapter, wherein the first bar address write instruction carries the first target address and the second target address;

converting the first bar address writing instruction into first main controller control information through the control state adapter, and transmitting the first main controller control information to the main controller, wherein the first main controller control information carries the first target address and the second target address.

6. The data transmission method according to claim 5, wherein the generating a first direct memory access command comprises:

generating, by the host controller, the first direct memory access instruction.

7. The data transmission method according to claim 6, wherein the lower computer further comprises a user data interface adapter, an uplink data cache and a cache monitoring element; before the generating, by the host controller, the first direct memory access instruction, the data transmission method further includes:

receiving the first data generated by an application layer through the user data interface adapter, and storing the first data to the uplink data cache;

monitoring the uplink data cache through the cache monitoring element, obtaining a storage address of the first data in the uplink data cache through monitoring, taking the storage address of the first data in the uplink data cache as the source address, and transmitting the source address to the main controller.

8. The method according to claim 6, wherein the performing a first direct memory access operation according to the first direct memory access instruction comprises:

transmitting the first direct memory access instruction to the control state adapter through the host controller;

converting the first direct memory access instruction into a first PCIe HIP control instruction through the control state adapter;

passing the first PCIe HIP control instruction to the PCIe HIP element through the control state adapter;

and executing the first direct memory access operation according to the first PCIe HIP control instruction through the PCIe HIP element.

9. The data transmission method according to claim 2, wherein the lower computer includes a main controller, a control state adaptor and a PCIe HIP element, and the receiving the data downlink indication information sent by the upper computer includes:

receiving a second bar address write instruction transmitted by the upper computer through the PCIe HIP element, and transmitting the second bar address write instruction to the control state adapter;

and converting the second bar address write instruction into second host controller control information through the control state adapter, and transmitting the second host controller control information to the host controller.

10. The data transmission method according to claim 9, wherein the generating a second dma command according to the indication of the data downlink indication information includes:

generating, by the host controller, the second direct memory access instruction.

11. The method according to claim 10, wherein the performing a second dma operation according to the second dma command comprises:

transmitting the second direct memory access instruction to the control state adapter through the host controller;

converting the second direct memory access instruction into a second PCIe HIP control instruction through the control state adapter;

passing the second PCIe HIP control instruction to the PCIe HIP element through the control state adapter;

and executing the second direct memory access operation according to the second PCIe HIP control instruction through the PCIe HIP element.

12. The data transmission method according to claim 3, wherein the lower computer includes a main controller, a control state adaptor, and a PCIe HIP element, and the generating execution completion information and transmitting the execution completion information to the second storage space in the main memory according to the second target address includes:

generating an execution finishing instruction through the PCIe HIP element, and transmitting the execution finishing instruction to the control state adapter;

converting the execution finishing instruction into third main controller control information through the control state adapter, and transmitting the third main controller control information to the main controller;

generating intermediate execution completion information according to the third main controller control information through the main controller, and transmitting the intermediate execution completion information to the control state adapter;

converting the intermediate execution completion information into the execution completion information through the control state adapter, and transmitting the execution completion information to the PCIe HIP element;

and transmitting the execution completion information to the second storage space according to the second target address through the PCIe HIP element.

13. The utility model provides a data transmission device which characterized in that for in the lower computer of PCIe bus architecture, PCIe bus architecture includes host computer, main memory and the lower computer, data transmission device includes:

a first execution module, configured to execute a first direct memory access operation according to the first direct memory access instruction;

the first direct memory access operation comprises the steps of obtaining the first data from a storage space corresponding to the source address and transmitting the first data to the first storage space according to the first target address;

the second receiving module is used for receiving the first target address transmitted by the upper computer, wherein the first target address is sent after the upper computer sets the first storage space, and the first storage space is set after the upper computer finishes driving and loading of the lower computer.

14. A computer device comprising a memory and a processor, the memory storing a computer program which, when executed by the processor, implements a data transmission method as claimed in any one of claims 1 to 12.

15. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the data transmission method according to any one of claims 1 to 12.