CN111176926A - IP (Internet protocol) core simulation system and simulation method based on double-port SRAM (static random Access memory) - Google Patents
IP (Internet protocol) core simulation system and simulation method based on double-port SRAM (static random Access memory) Download PDFInfo
- Publication number
- CN111176926A CN111176926A CN201911395393.XA CN201911395393A CN111176926A CN 111176926 A CN111176926 A CN 111176926A CN 201911395393 A CN201911395393 A CN 201911395393A CN 111176926 A CN111176926 A CN 111176926A
- Authority
- CN
- China
- Prior art keywords
- interface
- port sram
- double
- simulation
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The utility model provides an IP core simulation system and a simulation method based on a double-port SRAM, wherein the simulation system comprises a design module to be verified, a central processing unit and the double-port SRAM; the CPU is used for constructing a hierarchical CPU bus function model, and the bus function model is used for accessing the double-port SRAM module to make corresponding data structure preparation for transmitting read-write data to the double-port SRAM module and transmitting read-write commands according to a register configuration interface of the to-be-verified design module; the double-port SRAM is used for replacing a bus controller and an arbiter in a traditional system to realize the direct access of two MASTER to the SRAM, so that the complexity of the simulation system is greatly reduced, and meanwhile, a hierarchical CPU bus function model is arranged, and when a module interface changes, only the corresponding MASTER BFM needs to be selected for instantiation, so that the simulation system can be continuously used. The reusability of the whole verification assembly is greatly improved, different modules can use the system to quickly construct own simulation systems, and the working efficiency of verification personnel is greatly improved.
Description
Technical Field
The disclosure relates to the technical field of interface module verification, in particular to an IP core simulation system and a simulation method based on a double-port SRAM.
Background
The statements in this section merely provide background information related to the present disclosure and may not necessarily constitute prior art.
Development and multiplexing of IP (Intellectual Property) are key technologies of a System on Chip (SoC), and IP verification is a core link of IP development. The time and workload of functional timing simulation, test and verification of IP greatly exceed the system and logic design. Therefore, simulation testing of IP becomes a critical part of the design. The general soft IP core verification method is to perform software simulation in a software environment to verify the correctness of an IP (intelligent performance) core function, then write the software simulation into an FPGA (Field programmable Gate Array) device to verify a hardware circuit, if the test is correct, the IP core verification is completed, and if the test has a problem, the IP core is returned to be modified again.
The interface module is one of the IP cores, and is used for realizing data transmission between different devices or different systems, and at present, the data transmission process of the interface module, especially a high-speed interface module, is often complex, and often requires the participation of a CPU and an SRAM. To verify that the interface module requires more bus function models, i.e., BFMs, to form a small system, the coordination of the small system requires the participation of various bus controllers and arbiters. Since the bus controller and the arbiter tend to be complex, the design and application need to consume large human resources and time resources.
At present, many interface modules, especially high-speed interface modules, need to configure a certain data structure in advance for an SRAM through a bus by means of a CPU to realize high-speed transmission of data. At this time, two hosts, namely MASTER, access the SRAM through an interface (one is a CPU connection interface, and the other is a data interface of a module), if the common SRAM is used at this time, the access of the two MASTERs must be arbitrated, generally, arbitration among different MASTERs is carried out through a bus controller in a system, and the two MASTERs may adopt different interfaces, so that a plurality of bus controllers are needed, and a conversion interface needs to be constructed between the two controllers, so that the whole verification system becomes very large, and the rapid compiling and simulation of a simulator are not facilitated.
Disclosure of Invention
The invention provides an IP nuclear simulation system and a simulation method based on a double-port SRAM (static random access memory), wherein a design module to be tested (DUT), a CPU and the SRAM are tightly combined through the double-port SRAM to form a small simulation system which is clear in labor division and simple and convenient to operate, the CPU has double functions of accessing the SRAM to prepare a corresponding data structure for the module and accessing a module register, the characteristic that two interfaces of the double-port SRAM can be used for reading and writing respectively is utilized, the arbitration process can be omitted, two host MASTERs can directly access the SRAM, can share the data of the SRAM and cannot make mistakes due to resource competition, and therefore the complexity of a verification system is reduced.
In order to achieve the purpose, the following technical scheme is adopted in the disclosure:
one or more embodiments provide an IP core simulation system based on a dual-port SRAM, including a design module to be verified, a central processing unit, and a dual-port SRAM;
a central processing unit: the system comprises a bus function model, a register configuration interface and a double-port SRAM module, wherein the bus function model is used for constructing a hierarchical CPU bus function model and is used for accessing the double-port SRAM module to make a corresponding data structure to prepare for transmitting read-write data to the double-port SRAM module and transmitting a read-write command according to the register configuration interface of the to-be-verified design module;
a to-be-verified design module: the double-port SRAM is used for reading and writing data from the double-port SRAM according to a reading and writing command received from the CPU;
a double-port SRAM: the design verification system is configured to realize data interaction between the CPU and the design module to be verified, which are connected through the two interfaces.
Furthermore, the hierarchical CPU bus function model comprises an interface task layer, a read-write task generation layer and a simulation case construction layer;
interface task layer: the data conversion interface is used for configuring data transmission among the central processing unit CPU, the double-port SRAM and the design module to be verified according to different interfaces;
read-write task generation layer: the interface type is used for converting the data into the interface type, abstracting the read-write task according to the interface type, and abstracting the read-write task into the read-write task corresponding to the interface type conversion;
simulation case construction layer: the method comprises the steps of obtaining a simulation case input by a user, calling a read-write task generation layer according to the simulation case, and generating a simulation configuration corresponding to the functional verification of a design module to be verified, wherein the simulation configuration comprises a plurality of data read-write tasks corresponding to the verification function.
Furthermore, the data conversion interface of the interface task layer comprises a register configuration interface according to the design module to be verified and host bus function models respectively selected according to the interfaces of the dual-port SRAM, and access of the CPU to the dual-port SRAM and the register of the design module to be verified is respectively completed through the read-write tasks of the two host bus function models, namely MASTER BFM.
Further, when the selected host bus function model is not matched with the register configuration interface, a second interface conversion bridge is arranged to convert the host bus function model into a MASTER interface corresponding to the DUT register configuration interface, and connection between the DUT register configuration interface and an interface of the double-port SRAM is established;
or
When the selected host bus function model is not matched with the interface of the dual-port SRAM, an additional first interface conversion bridge 1 is needed to convert the host bus function model into a MASTER interface corresponding to the central processing unit, namely, the connection between the central processing unit and the interface of the dual-port SRAM is established.
Further, the system also comprises a dual-port SRAM creating module which is used for defining the storage data type of the dual-port SRAM and defining the relationship of two interfaces.
Further, the stored data of the dual-port SRAM is defined as a two-dimensional array, or two interfaces of the SRAM are in an asynchronous relation.
An IP simulation method based on a double-port SRAM comprises the following steps:
acquiring a simulation case for a software module to be tested;
generating a simulation configuration corresponding to the function verification of the design module to be verified according to the simulation use case, wherein the simulation configuration comprises a plurality of data reading and writing tasks corresponding to the verification function;
configuring a data conversion interface for data transmission among a Central Processing Unit (CPU), a double-port SRAM and the to-be-verified design module according to a register configuration interface of the to-be-verified design module and an interface of the double-port SRAM;
and abstracting the read-write task of the CPU according to the configured data conversion interface and the simulation configuration, abstracting the read-write task corresponding to the interface type conversion of the data conversion interface, and executing the read-write task to complete the simulation verification of the software module to be tested.
Further, the acquisition of the simulation use case constructs a random use case or a directed use case through a task/function of a system verilog language, or directly transplants a firmware code construct through a DPI interface.
Further, a host bus function model respectively selected according to a register configuration interface of a design module to be verified and an interface of a double-port SRAM is the MASTER BFM;
or
When the conversion of the interface can not be realized through the set MASTER BFM, a conversion bridge is set, and the conversion bridge comprises a first interface conversion bridge for realizing the data communication between the double-port SRAM and the CPU and a second interface conversion bridge for realizing the data communication between the double-port SRAM and the design module to be verified.
Furthermore, the read-write task of the CPU is abstracted according to the configured data conversion interface and the simulation configuration, wherein the abstraction step comprises the following steps: the configuration operation to the register and the read-write operation to the SRAM are distinguished by different addresses.
Compared with the prior art, the beneficial effect of this disclosure is:
(1) the system and the method can be widely applied to module-level verification of the interface module, and the double-port SRAM is utilized to replace a bus controller and an arbiter in the traditional system to realize the direct access of two MASTERs to the SRAM, so that the complexity of the simulation system is greatly reduced, and the workload of verification personnel is greatly reduced.
(2) According to the hierarchical CPU bus function model, when the module interface changes, only the corresponding MASTER BFM needs to be selected for instantiation, and the CPU bus function model can be continuously used. The reusability of the whole verification assembly is greatly improved, different modules can use the system to quickly construct own simulation systems, and the working efficiency of verification personnel is greatly improved.
(3) This approach provides an alternative interface conversion module to provide a simple portable simulation environment for verifying the selection of different DUTs and different CPUs. The verifier only needs to select the corresponding interface conversion module to convert into an interface capable of operating the SRAM according to the data interface of the module and the interface of the CPU BFM. The independent design facilitates the replacement of the interface conversion module and the reuse of the interface conversion module by the verifier according to different modules.
The system can be directly transplanted to a system level from the module level, and directly used as a BFM for a simulation use case of a system level construction module, all the module level simulation use cases can be directly transplanted to the system level without changing, so that the verification workload of the module at the system level is greatly simplified, and precious verification time and human resources can be saved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure and not to limit the disclosure.
FIG. 1 is a block diagram of a simulation system of embodiment 1 of the present disclosure;
fig. 2 is a functional model structure diagram of a CPU bus according to embodiment 1 of the present disclosure;
fig. 3 is a flowchart of a simulation method according to embodiment 2 of the present disclosure.
The specific implementation mode is as follows:
the present disclosure is further described with reference to the following drawings and examples.
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise. It should be noted that, in the case of no conflict, the embodiments and features in the embodiments in the present disclosure may be combined with each other. The embodiments will be described in detail below with reference to the accompanying drawings.
Technical term interpretation:
SRAM: static Random-Access Memory (SRAM) is one type of Random Access Memory. By "static," it is meant that the data stored in such a memory is always maintained as long as the memory remains powered on.
A CPU: (Central Processing Unit).
BFM: (Bus Functional Model) Bus function Model.
DUT: (Design Under Test) Design to be tested.
PHY: (Physical Layer) Physical Layer interface.
SystemVerilog is abbreviated as SV language, is established on the basis of Verilog language, is the extension enhancement of IEEE1364Verilog-2001 standard, is compatible with Verilog 2001, combines a hardware description language with a modern high-level verification language, and newly becomes a language for designing and verifying next-generation hardware.
A to-be-verified design module: refers to a software module, also called an IP core, which is to be tested and is programmed to implement a certain function. The interface module is one of the IP cores.
Example 1
In the technical solutions disclosed in one or more embodiments, as shown in fig. 1, an IP core simulation system based on a dual-port SRAM includes a design module to be verified, a central processing unit, and a dual-port SRAM;
the CPU is used for constructing a hierarchical CPU bus function model, and the bus function model is used for realizing accessing the double-port SRAM module to make corresponding data structure preparation for transmitting read-write data to the double-port SRAM module and transmitting read-write commands according to a register configuration interface of the to-be-verified design module;
design to be verified module i.e. design to be tested (DUT): the double-port SRAM is used for reading and writing data from the double-port SRAM according to a reading and writing command received from the CPU;
a double-port SRAM: the design verification system is configured to realize data interaction between a CPU and a design module to be verified (DUT) which are connected through two interfaces.
The layered CPU bus function model comprises an interface task layer, a read-write task generation layer and a simulation case construction layer.
Interface task layer: the data conversion interface is used for configuring data transmission among the central processing unit CPU, the double-port SRAM and the design module to be verified according to different interfaces;
optionally, the data conversion interface may include a register configuration interface according to the design module to be verified and a host bus function model respectively selected according to the interface of the dual-port SRAM, which is the MASTER BFM; the access to the interface which needs to be accessed by the two CPUs can be respectively completed through the read-write tasks of the two MASTER BFMs, namely the access of the CPUs to the double-port SRAM and the register of the design module to be verified.
As a further technical scheme, when the selected host bus function model is not matched with the register configuration interface, setting a second interface conversion bridge to convert the host bus function model into a MASTER interface corresponding to the DUT register configuration interface, and establishing connection between the DUT register configuration interface and an interface of a double-port SRAM; or, when the selected host bus function model is not matched with the interface of the dual-port SRAM, an additional first interface conversion bridge 1 is needed to convert the host bus function model into a MASTER interface corresponding to the central processing unit, that is, the connection between the central processing unit and the interface of the dual-port SRAM is established.
The host bus function model is the MASTER BFM, which is used to provide function instantiation for software testing, and may be a function model of function verification that has been implemented by a verifier before.
In this embodiment, two of MASTER BFMs are selected for implementing interface conversion: the method is used for realizing data communication of different interface types, and can also comprise the steps of providing a first interface conversion bridge 1 for the double-port SRAM to realize the data communication between the double-port SRAM and a CPU, and providing a second interface conversion bridge 2 for the double-port SRAM to realize the data communication between the double-port SRAM and a design module to be verified (DUT).
And selecting a second interface conversion bridge 2 according to the selected MASTER BFM for realizing data transmission of the interface of the MASTER BFM and the SRAM, and selecting a first interface conversion bridge 1 according to the data interface of the DUT, wherein the two bridges are respectively connected with two interfaces of the SRAM. Therefore, the data interface of the CPU and the DUT can carry out random read-write operation on the content of the SRAM.
Read-write task generation layer: the interface conversion device is used for abstracting the read-write task according to the interface types of the first interface conversion bridge 1 and the second interface conversion bridge 2 into the read-write task corresponding to the interface type conversion; the read-write behavior of the CPU is simulated, and the interface is distinguished by different offset addresses, just like a decoder of a real bus controller.
Simulation case construction layer: the method comprises the steps of obtaining a simulation case input by a user, calling a read-write task generation layer according to the simulation case, and generating a simulation configuration corresponding to the functional verification of a design module to be verified, wherein the simulation configuration comprises a plurality of data read-write tasks corresponding to the verification function.
The mode of acquiring the simulation use case can be flexible, optional, a random or directional use case can be constructed through a task/function of a system verilog language, a use case closer to a system layer can be constructed by directly transplanting firmware codes through a DPI interface, and different modes can be selected by a verifier according to specific situations and requirements.
The system also comprises a double-port SRAM creating module, which is used for defining the storage data type of the double-port SRAM and defining two interface relations, optionally, the storage data of the double-port SRAM can be defined as a two-dimensional array, the width of the array is defined as 8 bits (1Byte), the two interfaces of the SRAM are in an asynchronous relation, the two-dimensional array can be independently read and written, and the specific W can be defined as Bit [7:0] SRAM _ array [1024 ].
In other embodiments, further, two interface relationships of the dual-port SRAM may be: the two interfaces can simultaneously carry out reading operation, and when the two interfaces carry out writing operation on the two-dimensional array at the same time, the writing operation of one interface is judged to be effective.
Optionally, the IO interface of the DUT is connected to an external PHY or other module.
Example 2
The embodiment also provides an IP simulation method based on the dual-port SRAM, as shown in fig. 2 and 3, including the following steps:
step 1, acquiring a simulation case for a software module to be tested;
step 2, generating a simulation configuration corresponding to the function verification of the design module to be verified according to the simulation case, wherein the simulation configuration comprises a plurality of data reading and writing tasks corresponding to the verification function;
step 3, configuring a data conversion interface for data transmission among the central processing unit CPU, the double-port SRAM and the design module to be verified respectively according to the register configuration interface of the design module to be verified and the interface of the double-port SRAM;
and 4, abstracting the read-write task of the CPU according to the configured data conversion interface and the simulation configuration, abstracting the read-write task corresponding to the interface type conversion of the data conversion interface, and executing the read-write task to complete the simulation verification of the software module to be tested.
In step 1, a simulation case for the to-be-tested software module is obtained, wherein the simulation case is set by a verifier according to the functional requirements of different to-be-tested software modules, and the different to-be-tested software modules are different and need to be input and configured by the verifier. Random or directional use cases can be constructed through tasks/functions of a system verilog language, use cases closer to a system layer can be constructed by directly transplanting firmware codes through a DPI interface, and different modes can be selected by verification personnel according to specific situations and requirements.
The DPI Interface is called a direct compilation Interface, and systemwell introduces a direct compilation Interface (DPI), which can be more simply connected to C, C + + or other non-verilog programming languages.
The MASTER BFM can be mapped to the C language through the DPI interface, so that module simulation can be closer to real application, and a firmware driver can be directly transplanted to provide more practical application references for a construction case of a verification person.
In step 2, generating a simulation configuration corresponding to the functional verification of the design module to be verified according to the simulation case, wherein the simulation configuration comprises a method for a plurality of data read-write tasks corresponding to the verification function, and specifically comprises the following steps:
and step 21, generating a configuration task and a read-write task for the register according to the simulation case and the register of the software module to be tested DUT.
Step 22 generates read/write tasks for the SRAM according to the simulation case.
In step 3, the data conversion interface comprises a register configuration interface according to a design module to be verified and a host bus function model which is a MASTER BFM and is respectively selected according to an interface of the double-port SRAM; the access to the interface required to be accessed by the two CPUs can be respectively completed through the read-write tasks of the two MASTER BFMs; when the interface conversion cannot be realized through the set MASTER BFM, a conversion bridge may be additionally set, as shown in fig. 2, a dual-port SRAM may be further included to provide a first interface conversion bridge 1 to realize data communication between the dual-port SRAM and the CPU, and a second interface conversion bridge 2 is provided for the dual-port SRAM to realize data communication between the dual-port SRAM and a design module to be verified (DUT).
And selecting a second interface conversion bridge 2 according to the selected MASTER BFM for realizing data transmission of the interface of the MASTER BFM and the SRAM, and selecting a first interface conversion bridge 1 according to the data interface of the DUT, wherein the two bridges are respectively connected with two interfaces of the SRAM. Therefore, the data interface of the CPU and the DUT can carry out random read-write operation on the content of the SRAM.
And 4, abstracting a read-write task of the CPU according to the configured data conversion interface and the simulation configuration, abstracting the read-write task corresponding to the interface type conversion of the data conversion interface, and executing the read-write task to complete the simulation verification of the software module to be tested, wherein the abstracting step comprises the following steps: the configuration operation of the register and the read-write operation of the SRAM are distinguished by different addresses, and can be completed by the same read-write task.
The method also comprises a step of creating the dual-port SRAM, which comprises defining the storage data type of the dual-port SRAM and defining the relationship between two interfaces, optionally, the storage data of the dual-port SRAM can be defined as a two-dimensional array, the width of the array is defined as 8 bits (1Byte), the two interfaces of the SRAM are in an asynchronous relationship, and the two-dimensional array can be independently read and written. The data dimension and data width of the stored data defining the dual-port SRAM can be set as needed, and can also be defined as a 1-dimensional array, or as a 2-bit array but with a data width of not 8 bits. The SRAM stores by taking Byte as a unit, and the serial number of the array in the SRAM corresponds to the address of the SRAM one by one, so that a verifier can directly obtain data for comparison through the serial number of the array in the SRAM.
The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure, and various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.
Although the present disclosure has been described with reference to specific embodiments, it should be understood that the scope of the present disclosure is not limited thereto, and those skilled in the art will appreciate that various modifications and changes can be made without departing from the spirit and scope of the present disclosure.
Claims (10)
1. An IP nuclear simulation system based on a double-port SRAM is characterized in that: the system comprises a design module to be verified, a central processing unit and a double-port SRAM;
a central processing unit: the system comprises a bus function model, a register configuration interface and a double-port SRAM module, wherein the bus function model is used for constructing a hierarchical CPU bus function model and is used for accessing the double-port SRAM module to make a corresponding data structure to prepare for transmitting read-write data to the double-port SRAM module and transmitting a read-write command according to the register configuration interface of the to-be-verified design module;
a to-be-verified design module: the double-port SRAM is used for reading and writing data from the double-port SRAM according to a reading and writing command received from the CPU;
a double-port SRAM: the design verification system is configured to realize data interaction between the CPU and the design module to be verified, which are connected through the two interfaces.
2. The IP core emulation system based on dual-port SRAM of claim 1, wherein: the hierarchical CPU bus function model comprises an interface task layer, a read-write task generation layer and a simulation case construction layer;
interface task layer: the data conversion interface is used for configuring data transmission among the central processing unit CPU, the double-port SRAM and the design module to be verified according to different interfaces;
read-write task generation layer: the interface type is used for converting the data into the interface type, abstracting the read-write task according to the interface type, and abstracting the read-write task into the read-write task corresponding to the interface type conversion;
simulation case construction layer: the method comprises the steps of obtaining a simulation case input by a user, calling a read-write task generation layer according to the simulation case, and generating a simulation configuration corresponding to the functional verification of a design module to be verified, wherein the simulation configuration comprises a plurality of data read-write tasks corresponding to the verification function.
3. The IP core emulation system based on dual-port SRAM of claim 2, wherein: the data conversion interface of the interface task layer comprises a register configuration interface according to the design module to be verified and host bus function models respectively selected according to the interfaces of the dual-port SRAM, and the access of the CPU to the dual-port SRAM and the register of the design module to be verified is respectively completed through the read-write tasks of the two host bus function models, namely MASTER BFM.
4. The IP core simulation system based on the dual-port SRAM as claimed in claim 4, wherein: when the selected host bus function model is not matched with the register configuration interface, setting a second interface conversion bridge to convert the host bus function model into a MASTER interface corresponding to the DUT register configuration interface, and establishing the connection between the DUT register configuration interface and an interface of a double-port SRAM;
or
When the selected host bus function model is not matched with the interface of the double-port SRAM, a first interface conversion bridge is arranged to convert the host bus function model into a MASTER interface corresponding to the central processing unit, namely, the connection between the central processing unit and the interface of the double-port SRAM is established.
5. The IP core emulation system based on dual-port SRAM of claim 1, wherein: the system also comprises a double-port SRAM creating module which is used for defining the storage data type of the double-port SRAM and defining the relationship of two interfaces.
6. The IP core emulation system based on dual-port SRAM of claim 1, wherein: the stored data of the double-port SRAM is defined as a two-dimensional array, or two interfaces of the double-port SRAM are in an asynchronous relation.
7. An IP simulation method based on a double-port SRAM is characterized by comprising the following steps:
acquiring a simulation case for a software module to be tested;
generating a simulation configuration corresponding to the function verification of the design module to be verified according to the simulation use case, wherein the simulation configuration comprises a plurality of data reading and writing tasks corresponding to the verification function;
configuring a data conversion interface for data transmission among a Central Processing Unit (CPU), a double-port SRAM and the to-be-verified design module according to a register configuration interface of the to-be-verified design module and an interface of the double-port SRAM;
and abstracting the read-write task of the CPU according to the configured data conversion interface and the simulation configuration, abstracting the read-write task corresponding to the interface type conversion of the data conversion interface, and executing the read-write task to complete the simulation verification of the software module to be tested.
8. The IP simulation method based on the dual-port SRAM as claimed in claim 7, wherein: the acquisition of the simulation use case constructs a random use case or a directed use case through a task/function of a system verilog language, or directly transplants a firmware code construct through a DPI interface.
9. The IP simulation method based on the dual-port SRAM as claimed in claim 7, wherein:
the method comprises the steps that a host bus function model which is respectively selected according to a register configuration interface of a design module to be verified and an interface of a double-port SRAM is a MASTER BFM;
or
When the conversion of the interface can not be realized through the set MASTER BFM, a conversion bridge is set, and the conversion bridge comprises a first interface conversion bridge for realizing the data communication between the double-port SRAM and the CPU and a second interface conversion bridge for realizing the data communication between the double-port SRAM and the design module to be verified.
10. The IP simulation method based on the dual-port SRAM as claimed in claim 7, wherein:
abstracting a read-write task of the CPU according to the configured data conversion interface and the simulation configuration, wherein the abstracting step comprises the following steps: the configuration operation to the register and the read-write operation to the SRAM are distinguished by different addresses.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911395393.XA CN111176926B (en) | 2019-12-30 | 2019-12-30 | IP core simulation system and simulation method based on dual-port SRAM |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911395393.XA CN111176926B (en) | 2019-12-30 | 2019-12-30 | IP core simulation system and simulation method based on dual-port SRAM |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111176926A true CN111176926A (en) | 2020-05-19 |
| CN111176926B CN111176926B (en) | 2023-08-15 |
Family
ID=70623306
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911395393.XA Active CN111176926B (en) | 2019-12-30 | 2019-12-30 | IP core simulation system and simulation method based on dual-port SRAM |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111176926B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112417797A (en) * | 2020-11-27 | 2021-02-26 | 海光信息技术股份有限公司 | Register configuration synchronization method, verification platform system and configuration method and device |
| CN112580287A (en) * | 2020-12-24 | 2021-03-30 | 西安翔腾微电子科技有限公司 | Verification module of embedded FPGA of SoPC chip |
| CN115391114A (en) * | 2022-08-26 | 2022-11-25 | 山东浪潮科学研究院有限公司 | Simulation method for data transmission between SRAM and AHB bus |
| CN115859872A (en) * | 2021-09-23 | 2023-03-28 | Oppo广东移动通信有限公司 | Verification model and construction method thereof, chip verification method and verification system |
| EP4154113A4 (en) * | 2020-06-15 | 2023-11-22 | Zeku Technology (Shanghai) Corp., Ltd. | Data stack mips analysis tool for data plane |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006018488A (en) * | 2004-06-30 | 2006-01-19 | Ricoh Co Ltd | Functional verification device, test bench, simulator program, and storage medium |
| US20070016731A1 (en) * | 2005-07-01 | 2007-01-18 | Atmel Nantes Sa | Asynchronous arbitration device and microcontroller comprising such an arbitration device |
| CN101262380A (en) * | 2008-04-17 | 2008-09-10 | 中兴通讯股份有限公司 | A device and method for FPGA simulation |
| CN101625705A (en) * | 2008-07-08 | 2010-01-13 | 华为技术有限公司 | Verification environment system and construction method thereof |
| CN102508753A (en) * | 2011-11-29 | 2012-06-20 | 青岛海信信芯科技有限公司 | IP (Internet protocol) core verification system |
| CN207503208U (en) * | 2017-09-12 | 2018-06-15 | 北京兆易创新科技股份有限公司 | Control the test system of storage chip |
-
2019
- 2019-12-30 CN CN201911395393.XA patent/CN111176926B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006018488A (en) * | 2004-06-30 | 2006-01-19 | Ricoh Co Ltd | Functional verification device, test bench, simulator program, and storage medium |
| US20070016731A1 (en) * | 2005-07-01 | 2007-01-18 | Atmel Nantes Sa | Asynchronous arbitration device and microcontroller comprising such an arbitration device |
| CN101262380A (en) * | 2008-04-17 | 2008-09-10 | 中兴通讯股份有限公司 | A device and method for FPGA simulation |
| CN101625705A (en) * | 2008-07-08 | 2010-01-13 | 华为技术有限公司 | Verification environment system and construction method thereof |
| CN102508753A (en) * | 2011-11-29 | 2012-06-20 | 青岛海信信芯科技有限公司 | IP (Internet protocol) core verification system |
| CN207503208U (en) * | 2017-09-12 | 2018-06-15 | 北京兆易创新科技股份有限公司 | Control the test system of storage chip |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP4154113A4 (en) * | 2020-06-15 | 2023-11-22 | Zeku Technology (Shanghai) Corp., Ltd. | Data stack mips analysis tool for data plane |
| CN112417797A (en) * | 2020-11-27 | 2021-02-26 | 海光信息技术股份有限公司 | Register configuration synchronization method, verification platform system and configuration method and device |
| CN112417797B (en) * | 2020-11-27 | 2023-09-26 | 海光信息技术(成都)有限公司 | Register configuration synchronization method, verification platform system, configuration method and device |
| CN112580287A (en) * | 2020-12-24 | 2021-03-30 | 西安翔腾微电子科技有限公司 | Verification module of embedded FPGA of SoPC chip |
| CN115859872A (en) * | 2021-09-23 | 2023-03-28 | Oppo广东移动通信有限公司 | Verification model and construction method thereof, chip verification method and verification system |
| CN115391114A (en) * | 2022-08-26 | 2022-11-25 | 山东浪潮科学研究院有限公司 | Simulation method for data transmission between SRAM and AHB bus |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111176926B (en) | 2023-08-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111176926B (en) | IP core simulation system and simulation method based on dual-port SRAM | |
| US8438306B2 (en) | Apparatus and methods for on layer concurrency in an integrated circuit | |
| JP4014080B2 (en) | Digital circuit design apparatus and design method, program, and storage medium | |
| US7424416B1 (en) | Interfacing hardware emulation to distributed simulation environments | |
| CN112286746B (en) | Universal verification platform and method for AXI slave device interface | |
| US7240268B2 (en) | Test component and method of operation thereof | |
| CN107907814B (en) | Method for improving mass production test efficiency of chips | |
| CN114707453B (en) | Chip function verification method, device, electronic device and storage medium | |
| CN114970411B (en) | Simulation verification method and system | |
| US6959272B2 (en) | Method and system for generating an ATPG model of a memory from behavioral descriptions | |
| Siegmund et al. | SystemC/sup SV: an extension of SystemC for mixed multi-level communication modeling and interface-based system design | |
| Hussien et al. | Development of a generic and a reconfigurable UVM-Based verification environment for SoC buses | |
| CN115659906A (en) | Chip verification system, method and related equipment | |
| CN113609052A (en) | Chip simulation system based on FPGA and microprocessor and implementation method | |
| CN110221867A (en) | Pulse I/O function cartoon letters drive system and method under a kind of XP system | |
| US7228513B2 (en) | Circuit operation verification device and method | |
| CN113204929A (en) | Method for realizing AHB VIP based on SV and UVM, electronic device and storage medium | |
| CN113010361A (en) | MIO function rapid verification method of fully programmable SOC chip | |
| CN116627496B (en) | UVM-based register model construction and verification method, system and electronic equipment | |
| Dobis et al. | Open-source verification with chisel and scala | |
| CN113496108B (en) | CPU model applied to simulation | |
| CN117762771A (en) | Verification platform building method, electronic equipment and storage medium | |
| US12073155B2 (en) | Method and system for building hardware images from heterogeneous designs for electronic systems | |
| Datta et al. | Formal verification of a public-domain DDR2 controller design | |
| CN111950219A (en) | Method, apparatus, device, and medium for implementing a simulator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |