CN111176911B - Novel high-speed FPGA auxiliary configuration system of large storage capacity - Google Patents

Abstract

The invention relates to a novel high-speed FPGA auxiliary configuration system with large storage capacity, wherein an operation configuration file of a main control FPGA module in a configuration stage is stored in a configuration memory module; the configuration memory module sends the stored operation configuration file to the main control FPGA module when the system is electrified every time, and the main control FPGA module completes configuration; in the programming stage, a programming stage configuration file is sent to a main control FPGA module from an upper computer, the main control FPGA module completes programming control configuration, the upper computer programming module sends a configuration code stream to the main control FPGA module through a communication module, the main control FPGA module writes the configuration code stream to a code stream memory, and the system is powered off; in the configuration stage, the system is powered on, after the configuration file is run by the main control FPGA module to complete configuration, a configuration instruction sent from the outside is received, a corresponding configuration code stream is obtained from the code stream memory, and the obtained configuration code stream is sent to the FPGA to be tested by the communication module to complete configuration of the FPGA to be tested.

Description

A New Auxiliary Configuration System of Large Memory and High Speed FPGA

technical field

The invention relates to a novel large-storage high-speed FPGA auxiliary configuration system, which belongs to the technical field of integrated circuits.

Background technique

A very large-scale Field Programmable Gate Array (FPGA, Field Programmable Gate Array) with programmable capabilities includes a large number of programmable resources, and these programmable resources cannot be used simultaneously in one test code stream. With the progress of the technology and the substantial increase of the circuit scale, the test stream file is also further increased. For ultra-large-scale FPGAs, the capacity of a single code stream has reached tens of megabits. In addition, the increase in the complexity of the test structure of the device under test has led to a significant increase in the number of required code stream files, reaching about 100 to 200. Therefore, during the test process, usually Hundreds of configurations are required to achieve a certain fault coverage. At present, the maximum memory of UltraFLEX and V93000 devices with high configuration is only 128Mbyte, and the files of hundreds of bits far exceed the memory capacity of the tester, and the capacity gap is more than 20 times, so the stream configuration cannot be directly performed by the tester. At the same time, for mass production testing, hundreds of test vectors need to be tested in a short time, and the downloader configuration rate provided by the device manufacturer is only about 12 megabits, and it may take an hour to complete the test of a circuit. The cost of testing does not have actual engineering value. Therefore, completing a large number of test configurations in a short time is a challenge for the mass production test system of tens of millions of FPGAs. To solve this problem, it is necessary to compress the number of test vectors, and more importantly, to use the high-speed configuration interface of the device to develop a dedicated configuration auxiliary system to speed up the single configuration, so that the entire test system is capable of implementing mass production testing. feasibility.

Contents of the invention

The technical problem solved by the present invention is to overcome the deficiencies of the prior art and provide a new large-storage high-speed FPGA auxiliary configuration system. Insufficient, the problem of being unable to store a large number of FPGA test code streams, and meeting the needs of high-speed configuration of FPGA in the mass production test of ultra-large-scale FPGA production.

The technical solution solution of the present invention is: a novel high-speed FPGA auxiliary configuration system with a large storage capacity, including a host computer programming module running on the host computer, and a code stream memory, a main control FPGA module, a configuration memory module, and a communication module;

The configuration memory module stores the operating configuration file of the main control FPGA module in the configuration stage; the configuration memory module sends the stored operating configuration file to the main control FPGA module when the system is powered on each time, and the main control FPGA module according to the described The running configuration file to complete the configuration;

In the programming phase, the configuration file of the programming phase is sent from the upper computer to the main control FPGA module, and the main control FPGA module completes the programming control configuration according to the configuration file of the programming phase, and the programming module of the upper computer sends the configuration code The stream is sent to the main control FPGA module through the communication module, and the main control FPGA module burns the configuration code stream to the code stream memory, and the system is powered off;

In the configuration phase, the system is powered on, and after the main control FPGA module runs the configuration file to complete the configuration, it receives the configuration command sent from the outside, obtains the corresponding configuration code stream from the code stream memory, and sends the acquired configuration code stream through the communication module Go to the FPGA to be tested and complete the configuration of the FPGA to be tested.

Preferably, also comprise FPGA model selection module, send different coded data to main control FPGA module by this module, main control FPGA module determines the specific model of FPGA to be tested according to coded data; Burn the configuration of different FPGA models in code stream memory Code stream; the main control FPGA module obtains the corresponding configuration code stream from the code stream memory according to the specific model for configuration.

Preferably, in the programming phase, after the configuration code stream is programmed into the code stream memory, the host computer programming module sends a read-back verification command to the main control FPGA module through the communication module, and the main control FPGA module stores the data in the code stream memory The configuration code stream data is read out, and sent to the host computer through the communication module, and the host computer checks with the pre-stored code stream. If the check is qualified, the programming stage is completed, and the system is powered off; Under the configuration of the FPGA module, perform the programming operation again until the verification is passed.

Preferably, the code stream memory is a FLASH memory, a FLASH array is composed of multiple pieces of FLASH, and the data signal and control signal of each piece of FLASH are connected to the data signal and control signal of the main control FPGA module, and the main control FPGA module completes each Read, write and erase operations of the chip FLASH.

Preferably, in the programming stage, after the main control FPGA module is configured, it includes a control module, a FIFO module, an erase module, a write module, an address conversion module, and a communication control module;

The control module realizes the jump of standby state, mode judgment, handshaking, erasing, and writing state in the form of a state machine;

The FIFO module is used for data buffering when writing to the code stream memory;

The address conversion module determines the start position and end position of the current programming according to the preset configuration code stream storage address;

Under the control of the state machine, the erase module and the write module respectively perform erase and write operations on the code stream memory; during the write operation, the data is burned from the FIFO module according to the start and end positions determined by the address conversion module Write.

Preferably, in the programming phase, after the main control FPGA module is configured, it includes a control module, a FIFO module, an erasing module, a reading module, a writing module, an address conversion module, and a communication control module;

The control module realizes the transition of standby state, mode judgment, handshaking, erasing, reading, and writing state by means of a state machine;

The FIFO module is used for data buffering when reading and writing the code stream memory;

The address conversion module determines the start position and end position of the current programming according to the preset configuration code stream storage address;

Under the control of the state machine, the erase module, the read module and the write module respectively perform erase and write operations on the code stream memory; during the write operation, the data is transferred from the FIFO module according to the start and end determined by the address conversion module The location is programmed, and the read operation process is used for code stream verification.

Preferably, the erasing module uses a state machine to realize jumps from standby state, unlock command state, unlock command confirmation state, erase command state, erase command confirmation state, and erase time waiting state;

When the control module enters the standby state, the erasing module enters the standby state at the same time; when the control module enters the erasing state, the erasing module enters the unlock command state from the standby state, and enters the unlock command confirmation state after a delay of a preset period of time, and Perform an unlock command operation on the code stream memory, enter the erase command state after the operation is completed, enter the erase command confirmation state after a preset period of time delay, and perform an erase command operation on the code stream memory to enter the erase time waiting state, Return to standby after the time wait is complete.

Preferably, the writing module realizes the transition from standby state, write preparation state, and write operation state through a state machine;

When the control module enters the standby state, the write module is in the standby state at the same time; when the control module enters the write state, the write module enters the write preparation state and performs write preparation operations on the code stream memory; after completing this operation, it enters the write operation state, according to the upper Receive the configuration code stream data from the communication module, write it into the specified area of the code stream memory, and jump back to the standby state after completing the operation.

Preferably, the read module implements the standby state, read ready state, and read data state through a state machine;

When the control module enters the standby state, the reading module is in the standby state at the same time; when the control module enters the reading state, the reading module enters the read preparation state, and performs the read preparation operation on the code stream memory; after completing this operation, it enters the read data state, according to the address Convert the address provided by the module, read the code stream data in the specified area, and jump back to the standby state after completing the operation.

Preferably, in the configuration stage, after the main control FPGA module is configured, it includes a control module, a FIFO module, a reading module, an address conversion module, and a stream output module;

The control module realizes the jump of standby state, handshake, address judgment, address conversion, read state, and code stream output state in the form of a state machine, and controls the corresponding module through the state jump;

The FIFO module is used for data buffering when reading the code stream memory;

The address conversion module judges the address according to the address sent by the received external tester, determines the serial number of the code stream that needs to be read out at present, and determines the start position and end position of the read operation of the current reading module according to the serial number of the code stream;

The reading module reads the corresponding code stream from the code stream memory according to the start position and the end position;

The code stream output module outputs the read code stream to the communication module.

The beneficial effect of the present invention compared with prior art is:

(1) The system of the present invention can be used in the mass production test of ultra-large-scale FPGA production, which not only solves the problem that the automatic test equipment has insufficient memory and cannot store a large amount of FPGA test code streams, but also satisfies the need for FPGA completion in the mass production test of ultra-large-scale FPGA production. High-speed configuration needs.

(2) Compared with the internal memory of traditional automatic test equipment, the large-capacity FLASH memory of the present invention can be used to store a large number of test code streams to meet the mass production test of ultra-large-scale FPGA production;

(3) adopt JTAG configuration mode with tradition, the highest configuration rate is only compared with 6 megabits, the present invention adopts SelectMap configuration mode, configuration clock is 30 megahertz, adopts 8 configuration data widths, configuration rate reaches 240 megabits, improves Improve the configuration efficiency of FPGA;

(4) The two stages of programming FLASH and configuring FPGA in the present invention are completely independent, and are equipped with an FPGA model selection function, which has strong flexibility and versatility, and can greatly improve the test efficiency of FPGA mass production.

(5) The present invention is designed with an FPGA model selection module, so that the present invention can complete the configuration functions of various types of FPGAs, increasing the universality and versatility of the auxiliary configuration system.

(6) Read and write preparation operations are added to the state machine of the read-write module designed by the present invention, which makes the sequence of memory read-write operations clearer and increases the stability of the entire auxiliary configuration system.

(7) In the state machine of the erasing module of the present invention, there is a preset sufficient delay time in the unlocking command state, the erasing command state and the erasing time waiting state, so that the memory has enough time to confirm the command and respond to the command, increasing the Auxiliary configuration system stability.

Description of drawings

Fig. 1 is the detailed diagram of the modules of the auxiliary configuration system of the present invention in the programming stage;

Fig. 2 is the detailed module diagram of the main control FPGA module of the auxiliary configuration system of the present invention in the programming stage;

Fig. 3 is the state transfer diagram of the control module in the main control FPGA module of the auxiliary configuration system of the present invention in the programming stage;

Fig. 4 is the FIFO module state transfer diagram in the main control FPGA module of the auxiliary configuration system of the present invention;

Fig. 5 is a state transition diagram of the FLASH erasing module in the main control FPGA module of the auxiliary configuration system of the present invention in the programming stage;

Fig. 6 is a state transition diagram of the FLASH reading module in the main control FPGA module of the auxiliary configuration system of the present invention;

Fig. 7 is a state transition diagram of the FLASH writing module in the main control FPGA module of the auxiliary configuration system of the present invention in the programming stage;

Fig. 8 is the state transfer diagram of the address conversion module in the main control FPGA module of the auxiliary configuration system of the present invention in the programming stage;

Fig. 9 is a state transition diagram of the communication control module in the main control FPGA module of the auxiliary configuration system of the present invention in the programming stage;

Fig. 10 is a detailed diagram of modules of the auxiliary configuration system of the present invention in the configuration phase;

Fig. 11 is the detailed module diagram of the main control FPGA module of the auxiliary configuration system of the present invention in the configuration stage;

Fig. 12 is a state transition diagram of the control module in the main control FPGA module of the auxiliary configuration system of the present invention in the configuration stage;

13 is a state transition diagram of the address conversion module in the main control FPGA module of the auxiliary configuration system of the present invention in the configuration stage;

Fig. 14 is a state transition diagram of the configuration output module in the main control FPGA module of the auxiliary configuration system of the present invention in the configuration phase.

Detailed ways

The present invention will be further elaborated below in conjunction with embodiment.

A new large-storage high-speed FPGA auxiliary configuration system, including a host computer programming module 205 running on the host computer, a code stream memory 201, a main control FPGA module 202, a configuration memory module 208, and a communication module 204; code stream memory 201, the main control FPGA module 202, the configuration memory module 208, and the communication module can be made on one circuit board, and of course other different forms can also be adopted according to actual needs. The configuration memory module is used to store the running configuration file of the main control FPGA module in the configuration phase; the configuration memory module will send the stored running configuration file to the main control FPGA module every time the system is powered on, and the main control FPGA module will Run the configuration file to complete the configuration;

In the programming stage, the programming stage configuration file is sent from the upper computer to the main control FPGA module 202, and the main control FPGA module 202 completes the programming control configuration according to the configuration file of the programming stage, and the upper computer programming module 205 will configure The code stream is sent to the main control FPGA module through the communication module, and the configuration code stream is programmed into the code stream memory 201 by the main control FPGA module 202, and the system is powered off; FIG. 1 is a detailed module diagram of the auxiliary configuration system of the present invention in the programming stage , wherein the communication module 204 is composed of a host computer communication module 206 and a test interface module 207 . In this programming phase, an additional FPGA model selection module 203 can be configured to send different encoded data to the main control FPGA module, and the main control FPGA module determines the specific model of the FPGA to be tested according to the encoded data; The configuration code stream of the model; the main control FPGA module obtains the corresponding configuration code stream from the code stream memory according to the specific model for configuration.

In the programming stage, the code stream memory 201, the FPGA model selection module 203 and the upper computer communication module 206 are respectively connected with the main control FPGA module 202 and perform data interaction. The host computer programming module 205 is connected with the main control FPGA module 202 through the host computer communication module 206 .

The code stream storage module 201 is mainly composed of a FLASH array, and the control signals and data signals of each piece of FLASH are connected to the main control FPGA module 202. These signals include: data signal terminal DATA[31:0], address signal terminal ADDR[26: 0], clock signal CLK, chip select signal terminal CE, output enable signal terminal OE, and write enable signal terminal WE. The FPGA model selection module 203 is connected to the FPGA through 4-bit signals, namely: M3, M2, M1, and M0; the upper computer communication module 206 uses the data signal DATA[7:0], the chip selection signal terminal CE, and the output enable signal terminal OE, the write enable signal terminal WR, and the read enable signal terminal RD are connected to the main control FPGA module 202 , and connected to the programming module 205 of the host computer through TX and RX signals.

The present invention is divided into modules, and the code stream storage module 201 is used as the core storage module. Consists of a FLASH array and is used to store the configuration code stream of the test FPGA.

In the programming stage, as shown in FIG. 2 , the main control FPGA module 202 includes a control module 301, a FIFO module 302, an erase module 303, a read module 304, a write module 305, an address conversion module 306, and a communication control module 307.

After the system is powered on and enters the working state, as shown in Figure 3, the control module 301 will enter the state 401; after entering the state 401, it will enter the state 402 under the action of the control signal provided by the host computer programming module 205; in the programming mode , the working steps are: state 401, state 402, state 403, state 404, state 405, state 406.

Among them, the state 401 is the standby state after entering the work, waiting for the instruction of the host computer programming module 205; the state 402 is the mode judgment state, according to the command from the host computer programming module 205, choose to enter the state 401, state 403, and state 404 , state 405, state 406 one of the states; state 403 is the handshake state, when receiving the instruction from the host computer programming module 205 to enter the state 403, the main control FPGA module 202 selects the encoded data of the module 203 according to the FPGA model, and sends The current coded data specifies the FPGA model, shakes hands with the upper computer programming module 205, and then enters the state 401; the state 404 is the FLASH erasing state. Module 202 performs an erase operation on the designated FLASH area according to the instruction data of host computer programming module 205. After the erasing is completed, the completion status is fed back to host computer programming module 205, and then enters state 401; state 405 is FLASH read State, after receiving the command request from the host computer programming module 205 to enter the state 405, the main control FPGA module 202 reads the specified FLASH area according to the instruction data of the host computer programming module 205, and reads the read data Upload to the host computer programming module 205, after completing the data reading work in the specified area, the completion status will be fed back to the host computer programming module 205, and then enter the state 401; the state 406 is the FLASH writing state, when receiving from the host computer After the command request of the write module 205 enters the state 406, the main control FPGA module 202 performs a write operation on the specified FLASH area according to the instruction data of the host computer programming module 205, and accepts the code stream data from the host computer programming module 205, Write the data to the specified area of FLASH, and after the writing operation is completed, the completion status is fed back to the programming module 205 of the host computer, and then enters the state 401 .

The FIFO module 302 is a data buffer module when the control module 301 reads and writes the code stream memory, and plays the role of buffering data and asynchronous reading. As shown in Figure 4, it is divided into standby state 407, reset FIFO state 408, write operation state 409, and read operation state 410. The specific working steps are: state 407, state 408, state 409, and state 410.

Wherein, state 407 is standby state, and when control module 301 enters standby state, FIFO module 302 enters standby state simultaneously; State 408 is reset FIFO state, after FIFO module leaves standby state 407, enters reset FIFO state, resets FIFO , in preparation for read and write operations; state 409 is a write operation state, when the control module 301 executes state 405, the data read from the code stream memory will first be written into the FIFO module; when the control module 301 executes state 406, from The data received by the upper computer programming module 205 is first written into the FIFO module; the state 410 is a read operation state, and when the control module 301 executes the state 405, the data read from the FIFO module is uploaded to the upper computer programming module 205; When module 301 executes state 406, data is read from the FIFO module and written into FLASH.

The erasing module 303 is a module called when the control module 301 performs a block erasing operation on the code stream memory. As shown in FIG. Erase instruction confirmation state 415 , erasure time waiting state 416 , the working steps are state 411 , state 412 , state 413 , state 414 , state 415 , and state 416 .

Wherein, the state 411 is the standby state, when the control module 301 enters the standby state, the erasing module enters the standby state simultaneously; the state 412 is the unlock command state, when the control module 301 enters the state 404, the erasing module enters the state 412 from the state 411 , perform an unlock command operation on the specified FLASH; state 413 is the unlock command confirmation state, after completing state 412, enter state 413, perform an unlock command confirmation operation on the specified FLASH, and complete the preparation for erasing the FLASH; state 414 is the erase command state , after completing state 413, enter state 414, perform block erase command operation on the FLASH in the specified area; state 415 is the erase command confirmation state, after completing state 414, enter state 415, perform block erase command on the FLASH in the specified area Confirm the operation, after completion, FLASH starts to erase the designated area; state 416 is the erasing time waiting state, after completing state 415, enter state 416, because the FLASH block erase needs certain time, state 416 has set a block After the erasing waiting time is completed, jump back to state 411.

The reading module 304 is the module that the control module 301 enters the state 405 and calls when the FLASH is read. As shown in FIG. State 418, State 419.

Wherein, state 417 is standby state, and when control module 301 enters standby state, reading module is in standby state simultaneously; Enable the pin to perform the read preparation operation; state 419 is the read operation state, after completing state 418, enter state 419, read the FLASH data in the specified area according to the address provided by the address conversion module, and jump back to state 417 after completing the operation.

Write module 305 is the module that control module 301 enters state 406, calls when FLASH is written, as shown in Figure 7, is divided into standby state 420, write ready state 421, write operation state 422, working steps are: State 421, State 422.

Wherein, state 420 is standby state, when control module 301 enters standby state, write module is in standby state simultaneously; State 421 is write preparation state, when control module 301 enters state 406, write module enters write preparation state, relevant to FLASH Enable the pin for write preparation operation; state 422 is the write operation state, after completing state 421, enter state 422, according to the instruction of the host computer programming module 205, receive the code stream data of the host computer programming module 205, and write it into FLASH After completing the operation, jump back to state 420.

The address conversion module 306 is that the control module 301 divides the address area in the code stream memory according to the code stream and its serial number of the specified FPGA model in the instruction data sent by the host computer programming module 205 under the state 404, state 405, and state 406 , to facilitate the writing and reading of stream data. As shown in FIG. 8 , it is divided into a standby state 423 , an address conversion waiting state 424 , a FLASH mode judging state 425 , and a stream number judging state 426 . The working steps are divided into: state 423, state 424, state 425, state 426;

Wherein, state 423 is the standby state of address translation module, when control module 301 enters standby state, address translation module enters standby state simultaneously; The module waits to receive the start enable signal, and is ready to jump to the next state; state 425 is the judgment state of FLASH mode. After completing state 424, the address conversion module receives the instruction of the control module, and enters the following three modes through the judgment of the current instruction: FLASH erase One of the delete mode, FLASH read mode, and FLASH write mode; state 426 is the code stream sequence number judgment state, after completing state 425, according to the code stream sequence number in the command of the control module, the designated FLASH area is allocated and provided to the FLASH eraser The delete module, the FLASH read module, and the FLASH write module perform corresponding operations on the specified area, and jump back to state 423 after the operation is completed.

The communication control module 307 is a module for the main control FPGA module 202 to realize data interaction with the upper computer communication module 206, and read or write the upper computer communication module 206 according to the status of the corresponding pins of the upper computer communication module 206; as shown in Figure 9 It is divided into standby state 427, mode judgment state 428, read mode state 429, and write mode state 430; the working steps are state 427, state 428, state 429 or state 430.

Wherein, state 427 is standby state, when control module 301 enters standby state, communication control module 307 enters standby state simultaneously; State 428 is mode judgment state, after control module 301 jumps out of standby state, communication control module 307 jumps out of standby state simultaneously According to the level state of the corresponding pin of the upper computer communication module 206, it is judged to perform the following two modes: one of the read mode and the write mode; the state 429 is the state of the read mode, and after the completion of the state 428, it is judged that the read mode condition is met, The communication control module 307 enters the read mode state, reads the valid data output by the upper computer communication module 206, and transmits it to the control module 301 for the control module 301 to analyze the instruction. After completing the operation, jump back to the state 427; the state 430 is the write mode state, After completing state 428, it is determined that the write mode condition is met, and the communication control module 307 enters the write mode state, receives data from the control module 301, and transmits it to the corresponding pin of the upper computer communication module 206, and jumps back to state 427 after completing the operation.

The FPGA model selection module 203 provides the specific model of the FPGA to be tested for the main control FPGA module through different coded data, and by adjusting the code value of the FPGA model selection module 203, the same auxiliary configuration system can be used to carry out mass production tests of different types of FPGAs, Increased versatility of the auxiliary configuration system.

The communication module 204 is composed of a host computer communication module 206 and a test interface module 207 . In the programming phase, the upper computer communication module 206 mainly completes the communication between the upper computer programming module 205 and the main control FPGA module 202 . The upper computer communication module 206 is connected with the upper computer programming module 205 through a USB interface, and realizes communication with the main control FPGA module 202 through data signals and control signals.

The host computer programming module 205 mainly completes configuration and readback verification. The host computer programming module 205 realizes the interaction of data and control signals with the main control FPGA module 202 through the host computer communication module 206 . When configuring the code stream, the upper computer sends the clock, configures the code stream data and control instructions, and connects the main control FPGA module 202 through the upper computer communication module 206 to complete the operation of programming the configured code stream to the code stream memory. During code stream verification, the host computer programming module 205 sends a read-back verification instruction to the main control FPGA module 202 through the host computer communication module 206, and the main control FPGA module 202 reads the configuration code stream data stored in the code stream memory. sent to the host computer through the main control FPGA module 202 and the host computer communication module 206, and checked with the pre-stored code stream in the host computer.

FIG. 10 is a detailed module diagram of the auxiliary configuration system of the present invention in the configuration stage. In the configuration stage, the auxiliary configuration system mainly consists of a code stream memory 201, a main control FPGA module 202, an FPGA model selection module 203, a communication module 204, and a configuration memory module 208. Composition; wherein, the communication module 204 is composed of the upper computer communication module 206 and the test interface module 207.

The code stream memory 201, the configuration memory module 208, the communication module 204 and the FPGA model selection module 203 are respectively connected with the main control FPGA module 202 and perform data interaction. When configuring the FPGA to be tested, the automatic tester sends an address signal and a control signal, and the main control FPGA module 202 reads the configuration code stream from the code stream memory module 201 after receiving the address signal and the control signal, and burns it into the FPGA to be tested middle. In the configuration stage, the FPGA model selection module 203 provides the master FPGA module 202 with a specific model of the FPGA to be tested through different coded data.

In the configuration phase, the main control FPGA module 202 includes a control module 501, a FIFO module 502, a reading module 503, an address conversion module 504, and a configuration output module 505;

As shown in Figure 11, after the system is powered on and enters the working state, the control module 501 will enter the standby state 601; after entering the state 601, it will enter the handshake state 602 under the control signal provided by the automatic tester; in the configuration mode, as As shown in Figure 12, the working steps are: state 601, state 602, state 603, state 604, state 605, state 606.

Among them, the state 601 is the standby state after the system is powered on and enters the working state; the state 602 is the handshake state, and the control module 501 realizes the handshake state according to the corresponding pin level state of the test interface module 207; the state 603 is the address judgment state, complete After the state 602, the control module 501 calculates the sequence number of the code stream that needs to be read out according to the corresponding pin level state of the test interface module 207; the state 604 is the address conversion state, and after completing the state 603, according to the code stream sequence number, the control module 501 obtains corresponding address information by address conversion module; State 605 is the FLASH read mode state, and control mode 501 reads the FLASH data of corresponding area according to address information; State 606 is configuration output state, adopts the configuration mode of SelectMAP among the present invention, Through the read data, the code stream data is transmitted to the test interface module 207 through the configuration output module 506 until the FPGA to be tested, and then jumps back to the state 601 after the operation is completed.

The FIFO module 502 is a data buffer module when the control module 501 reads the code stream memory, and plays the role of buffering data and asynchronously reading. As shown in Figure 4, it is divided into standby state 607, reset FIFO state 608, write operation state 609, and read operation state 610. The specific working steps are: state 607, state 608, state 609, and state 610.

Wherein, state 607 is standby state, and when control module 501 enters standby state, FIFO module 502 enters standby state simultaneously; State 608 is reset FIFO state, after FIFO module leaves standby state 607, enters reset FIFO state, resets FIFO , to prepare for read and write operations; state 609 is a write operation state, when the control module 501 executes state 605, the data read from the code stream memory will first be written into the FIFO module, and after the operation is completed, jump back to state 607; state 610 is the read operation state. When the control module 501 executes the state 606, the data is read from the FIFO module and sent to the configuration output module 506. After the operation is completed, it returns to the state 607.

The reading module 503 is a module called when the control module 501 enters the state 605 and reads the FLASH. As shown in FIG. 611 , status 612 , status 613 .

Wherein, state 611 is standby state, when control module 501 enters standby state, read module is in standby state simultaneously; State 612 is read preparation state, when control module 501 enters state 605, read module enters read preparation state, related to Enable the pin to perform the read preparation operation; state 613 is the read operation state, after completing state 612, enter state 613, read the FLASH data in the specified area according to the address provided by the address conversion module, and jump back to state 611 after completing the operation.

The address conversion module 504 is a module for the control module 501 to calculate the corresponding address according to the currently selected FPGA model and the serial number of the code stream sent by the automatic tester in the state 604 . As shown in FIG. 13 , it is divided into a standby state 614 , an address conversion waiting state 615 , and a stream sequence number judgment state 616 . The working steps are divided into: state 614 , state 615 , and state 616 .

Wherein, state 614 is the standby state of address conversion module, when control module 501 enters standby state, address conversion module 504 enters standby state simultaneously; State 615 is address conversion waiting state, after control module 501 enters state 603 handshake success, address The conversion module waits for the start enable signal to be received, and is ready to jump to the next state; state 616 is the code stream sequence number judgment state, and after completing state 615, the corresponding FLASH area is calculated according to the code stream sequence number, and provided to the FLASH reading module for the specified The area performs a read operation, and jumps back to state 614 after the operation is completed.

Configuration output module 505 is that control module 501 is under state 606, calls this module to test interface module 207 and outputs the data flow of SelectMAP form, completes the work of configuring the FPGA to be tested, as shown in Figure 14, is divided into standby state 617, handshake state 618. Data output status 619. The working steps are divided into state 617 , state 618 and state 619 .

Wherein, state 617 is standby state, when control module 501 enters standby state, configuration output module 505 enters standby state simultaneously; State 618 is handshake state, when control mode 501 enters state 606, configuration output module 505 sends Program request signal, according to Receive the change of the Initial signal to judge whether the handshake is successful; the state 619 is the data output state, after completing the state 618, the configuration output module 505 sends the data of the corresponding area in the FLASH to the test interface module 207 according to the SelectMAP data format, until the FPGA to be tested , after the operation is completed, jump back to state 617.

Parts not described in detail in the present invention belong to the common knowledge of those skilled in the art.

Claims (8)

1. A new type of high-speed FPGA auxiliary configuration system with large storage capacity, characterized in that: it includes a host computer programming module running on the host computer, and a code stream memory, a main control FPGA module, a configuration memory module, and a communication module; The configuration memory module stores the operating configuration file of the main control FPGA module in the configuration stage; the configuration memory module sends the stored operating configuration file to the main control FPGA module when the system is powered on each time, and the main control FPGA module according to the described The running configuration file to complete the configuration; In the programming phase, the configuration file of the programming phase is sent from the upper computer to the main control FPGA module, and the main control FPGA module completes the programming control configuration according to the configuration file of the programming phase, and the programming module of the upper computer sends the configuration code The stream is sent to the main control FPGA module through the communication module, and the main control FPGA module burns the configuration code stream to the code stream memory, and the system is powered off; in the programming phase, after the configuration of the main control FPGA module is completed, including the control module and FIFO module , an erasing module, a writing module, an address conversion module, and a communication control module; the control module realizes standby state, mode judgment, handshaking, erasing, and writing state jumps in the form of a state machine; the FIFO module is used for code matching The stream memory performs data buffering when performing write operations; the address conversion module determines the current programming start position and end position according to the preset configuration code stream storage address; the erase module and the write module are controlled by the state machine, respectively Erase and write the code stream memory; during the write operation, burn the data from the FIFO module according to the start and end positions determined by the address conversion module; In the configuration phase, the system is powered on, and after the main control FPGA module runs the configuration file to complete the configuration, it receives the configuration command sent from the outside, obtains the corresponding configuration code stream from the code stream memory, and sends the obtained configuration code stream through the communication module Go to the FPGA to be tested and complete the configuration of the FPGA to be tested; In the configuration stage, after the main control FPGA module is configured, it includes the control module, FIFO module, reading module, address conversion module, and code stream output module; The control module realizes the jump of standby state, handshake, address judgment, address conversion, read state, and code stream output state in the form of a state machine, and controls the corresponding module through the state jump; The FIFO module is used for data buffering when reading the code stream memory; The address conversion module judges the address according to the address sent by the received external tester, determines the serial number of the code stream that needs to be read out at present, and determines the start position and end position of the read operation of the current reading module according to the serial number of the code stream; The reading module reads the corresponding code stream from the code stream memory according to the start position and the end position; The code stream output module outputs the read code stream to the communication module. 2. system according to claim 1, it is characterized in that: also comprise FPGA model selection module, send different coded data to main control FPGA module by this module, main control FPGA module determines the concrete model of FPGA to be tested according to coded data ; Program the configuration code streams of different FPGA models in the code stream memory; the main control FPGA module obtains the corresponding configuration code stream from the code stream memory according to the specific model for configuration. 3. The system according to claim 1, characterized in that: in the programming stage, after the configuration code stream is programmed into the code stream memory, the programming module of the upper computer sends a read-back verification instruction to the main control FPGA module through the communication module , the main control FPGA module reads the configuration code stream data stored in the code stream memory, and sends it to the host computer through the communication module, and the host computer checks with the pre-stored code stream. If the verification is qualified, the programming is completed In the stage, the system is powered off; otherwise, under the configuration of the current main control FPGA module, the programming operation is performed again until the verification is passed. 4. system according to claim 1, it is characterized in that: described code stream memory is FLASH memory, is formed FLASH array by a plurality of slices of FLASH, the data signal of every slice of FLASH and the control signal and the data signal of main control FPGA module It is connected with the control signal, and the main control FPGA module completes the read, write and erase operations of each piece of FLASH. 5. The system of claim 3, wherein: In the programming stage, after the main control FPGA module is configured, it includes a control module, a FIFO module, an erase module, a read module, a write module, an address conversion module, and a communication control module; The control module realizes the transition of standby state, mode judgment, handshaking, erasing, reading, and writing state by means of a state machine; The FIFO module is used for data buffering when reading and writing the code stream memory; The address conversion module determines the start position and end position of the current programming according to the preset configuration code stream storage address; Under the control of the state machine, the erase module, the read module and the write module respectively perform erase and write operations on the code stream memory; during the write operation, the data is transferred from the FIFO module according to the start and end determined by the address conversion module The location is programmed, and the read operation process is used for code stream verification. 6. The system according to claim 1 or 5, wherein the erasing module realizes the standby state, unlock command state, unlock command confirmation state, erase command state, and erase command confirmation in the form of a state machine. The state, the jump of the erasing time waiting state; When the control module enters the standby state, the erasing module enters the standby state at the same time; when the control module enters the erasing state, the erasing module enters the unlock command state from the standby state, and enters the unlock command confirmation state after a delay of a preset period of time, and Perform an unlock command operation on the code stream memory, enter the erase command state after the operation is completed, enter the erase command confirmation state after a preset period of time delay, and perform an erase command operation on the code stream memory to enter the erase time waiting state, Return to standby after the time wait is complete. 7. The system according to claim 1 or 5, characterized in that: the write module realizes the jump of standby state, write preparation state, and write operation state through a state machine; When the control module enters the standby state, the write module is in the standby state at the same time; when the control module enters the write state, the write module enters the write preparation state and performs write preparation operations on the code stream memory; after completing this operation, it enters the write operation state, according to the upper Receive the configuration code stream data of the communication module, write it into the designated area of the code stream memory, and jump back to the standby state after completing the operation. 8. The system according to claim 5, characterized in that: the read module implements a standby state, a read ready state, and a data read state through a state machine; When the control module enters the standby state, the reading module is in the standby state at the same time; when the control module enters the reading state, the reading module enters the read preparation state, and performs the read preparation operation on the code stream memory; after completing this operation, it enters the read data state, according to the address Convert the address provided by the module, read the code stream data in the specified area, and jump back to the standby state after completing the operation.