CN111176917A

CN111176917A - Method, system, terminal and storage medium for testing functional stability of CPU SST-BF

Info

Publication number: CN111176917A
Application number: CN201911371619.2A
Authority: CN
Inventors: 刘瑞雪
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Priority date: 2019-12-27
Filing date: 2019-12-27
Publication date: 2020-05-19
Anticipated expiration: 2039-12-27
Also published as: CN111176917B

Abstract

The present invention provides a CPU SST-BF function stability testing method, system, terminal and storage medium. Randomly select a test core from the CPU core, and the selected quantity of the test core is a single up-frequency number; Invoke the SST-BF function to up-frequency the test core, and down-frequency the core except the test core; Pressurize the CPU and collect the actual frequency of the test core during the pressurization process; calculate the difference between the actual frequency and the theoretical frequency of the up-frequency, and determine whether the difference exceeds a preset threshold: if yes, then determine that the test fails; If not, the test is judged to pass. The invention can automatically turn on the CPU SST-BF function and test the stability of the CPU SST-BF function, save manpower and test time, and at the same time cover all CPU cores, and improve the test accuracy.

Description

Method, system, terminal and storage medium for testing functional stability of CPU SST-BF

Technical Field

The invention relates to the technical field of server testing, in particular to a method, a system, a terminal and a storage medium for testing the stability of a CPU SST-BF function.

Background

At present, besides the CPU with general functions, the Intel CPU has SKUs optimized for the operating environment when being released, wherein the CPU with N is the CPU optimized for NFV (Network Function Virtualization) functions. The current cascade platform mainly comprises three types, namely 6252N, 6230N and 5218N, the CPU mainly has an SST-BF function compared with the common CPU, and the purpose of improving the performance is achieved mainly by increasing the fundamental frequency of certain specific cores and reducing the fundamental frequency of the rest cores.

Therefore, the SST-BF functional test is an important item of CPU test, but no effective automatic test method is available for testing the SST-BF functional stability.

Disclosure of Invention

In order to overcome the defects in the prior art, the invention provides a method, a system, a terminal and a storage medium for testing the stability of a CPU SST-BF function, so as to solve the technical problems.

In a first aspect, the invention provides a method for testing the stability of a CPU SST-BF function, which comprises the following steps:

acquiring the number of CPU cores and the number of upgradable cores, and taking the number of upgradable cores as the number of single upgradable cores;

randomly selecting test cores from CPU cores, wherein the selection number of the test cores is the single frequency increasing number;

calling an SST-BF function to carry out frequency increasing on the test core, and carrying out frequency reduction on cores except the test core;

pressurizing the CPU and collecting the actual frequency of the test core in the pressurizing process;

calculating a difference value between the actual frequency and the frequency-increasing theoretical frequency, and judging whether the difference value exceeds a preset threshold value:

if so, judging that the test is failed;

if not, the test is judged to be passed.

Further, the method further comprises:

storing the CPU model with SST-BF function into a comparison list;

reading the CPU model of the tester;

judging whether the CPU model of the tester exists in a comparison list:

if not, outputting a CPU model error prompt.

Further, the method further comprises:

deriving BIOS initial configuration information by using a SCELNX tool, and saving the initial configuration information as a configuration file;

reading the configuration file, modifying the status of an Activate PBF option in the configuration file into an Enabled status, and storing the modified configuration file;

importing the modified configuration file into the BIOS by using a SCELNX tool;

restarting the tester and checking whether the Activate PBF option state is an Enabled state:

if yes, the SST-BF output function is started successfully;

if not, the output SST-BF function is failed to automatically start.

Further, the method further comprises:

marking the cores which are subjected to frequency boosting;

judging whether the number of unmarked cores reaches the single frequency increasing number:

if yes, randomly selecting a test core from the unmarked cores;

if not, calculating the difference between the number of the unmarked cores and the single frequency increasing number, randomly selecting the marked cores with the difference number, and taking the selected marked cores and all the unmarked cores as test cores.

In a second aspect, the present invention provides a CPU SST-BF function stability testing system, including:

the device comprises a parameter acquisition unit, a parameter processing unit and a parameter setting unit, wherein the parameter acquisition unit is configured to acquire the number of CPU cores and the number of upgradable cores and take the number of the upgradable cores as the number of single upgradable cores;

the random selection unit is configured for randomly selecting test cores from the CPU cores, and the selection number of the test cores is the single frequency increasing number;

the function execution unit is configured to call an SST-BF function to perform frequency up-conversion on the test core and perform frequency down-conversion on cores except the test core;

the pressurization testing unit is configured for pressurizing the CPU and acquiring the actual frequency of a test core in the pressurization process;

the frequency judgment unit is configured to calculate a difference value between the actual frequency and the frequency-raising theoretical frequency and judge whether the difference value exceeds a preset threshold value;

a failure determination unit configured to determine that the test fails if the difference exceeds a preset threshold;

and the pass judgment unit is configured to judge that the test is passed if the difference value does not exceed a preset threshold value.

Further, the system further comprises:

the list setting unit is configured for storing the CPU model with the SST-BF function into a comparison list;

the model reading unit is configured for reading the model of the CPU of the tester;

the model judging unit is configured to judge whether the CPU model of the tester exists in the comparison list or not;

and the error prompt unit is configured to output a CPU model error prompt if the CPU model of the tester does not exist in the comparison list.

Further, the system further comprises:

the file export unit is configured to export BIOS initial configuration information by using a SCELNX tool and store the initial configuration information as a configuration file;

the state modification unit is configured and used for reading the configuration file, modifying the activated PBF option state in the configuration file into Enabled, and storing the modified configuration file;

the file import unit is configured to import the modified configuration file into the BIOS by using a SCELNX tool;

the state checking unit is configured for restarting the tester and checking whether the ActivatePBF option state is an Enabled state;

the success output unit is configured to output the SST-BF function to be started successfully if the activated PBF option state is the Enabled state;

and the failure output unit is configured for outputting the SST-BF function to automatically start failure if the activated PBF option state is not the Enabled state.

Further, the system further comprises:

an execution marking unit configured to mark a core that has performed the frequency up;

a number judgment unit configured to judge whether the number of unmarked cores reaches a single frequency-up number;

the first selection unit is configured to randomly select test cores from the unmarked cores if the number of the unmarked cores reaches the single frequency increasing number;

and the second selection unit is configured to calculate the difference between the number of the unmarked cores and the single frequency-up number if the number of the unmarked cores does not reach the single frequency-up number, randomly select the marked cores with the difference number, and use the selected marked cores and all the unmarked cores as the test cores.

In a third aspect, a terminal is provided, including:

a processor, a memory, wherein,

the memory is used for storing a computer program which,

the processor is used for calling and running the computer program from the memory so as to make the terminal execute the method of the terminal.

In a fourth aspect, a computer storage medium is provided having stored therein instructions that, when executed on a computer, cause the computer to perform the method of the above aspects.

The beneficial effect of the invention is that,

according to the method, the system, the terminal and the storage medium for testing the stability of the SST-BF function of the CPU, provided by the invention, the frequency of the test core is increased by randomly selecting the test core and calling the SST-BF function to set the frequency of other cores to be decreased, then the actual frequency of each core of the CPU is obtained by pressurizing the CPU, and whether the SST-BF function is effective or not is verified by comparing the actual frequency with the theoretical frequency. The invention can automatically open the CPU SST-BF function and test the stability of the CPU SST-BF function, saves labor and test time, and can cover all CPU cores, thereby improving the test accuracy.

In addition, the invention has reliable design principle, simple structure and very wide application prospect.

Drawings

In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.

FIG. 1 is a schematic flow diagram of a method of one embodiment of the invention.

FIG. 2 is a schematic block diagram of a system of one embodiment of the present invention.

Fig. 3 is a schematic structural diagram of a terminal according to an embodiment of the present invention.

Detailed Description

In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

FIG. 1 is a schematic flow diagram of a method of one embodiment of the invention. The execution main body in fig. 1 may be a CPU SST-BF function stability test system.

As shown in fig. 1, the method 100 includes:

step 110, acquiring the number of CPU cores and the number of upgradable cores, and taking the number of upgradable cores as the number of single upgradable cores;

step 120, randomly selecting test cores from CPU cores, wherein the selection number of the test cores is the single frequency increasing number;

step 130, calling an SST-BF function to carry out frequency increasing on the test core, and carrying out frequency reduction on cores except the test core;

step 140, pressurizing the CPU and collecting the actual frequency of the test core in the pressurizing process;

step 150, calculating a difference between the actual frequency and the frequency-up theoretical frequency, and judging whether the difference exceeds a preset threshold: if so, judging that the test is failed; if not, the test is judged to be passed.

In order to facilitate understanding of the present invention, the CPU SST-BF functional stability testing method provided by the present invention is further described below with reference to the principle of the CPU SST-BF functional stability testing method of the present invention and the process of testing the CPU SST-BF functional stability in the embodiment.

Specifically, the method for testing the functional stability of the SST-BF of the CPU comprises the following steps:

checking CPU model to judge whether the CPU has SST-BF function, if yes, jumping to

and secondly, exporting the configuration information in the BIOS into a file BIOS.txt by using/SCELNX _64, checking whether an active PBF option exists, if so, skipping to the third step, otherwise, outputting a BIOS not support sst-bf function by a screen.

changing the option Activate PBF to Enabled, then writing back the BIOS.

④ entering system, SCELNX deriving BIOS configuration information to determine whether the modification is successful, if yes, jumping to ⑤, otherwise screen output BIOS selects automatic fail, please enter BIOS to change manually

acquiring the spec of the current CPU from the effective SST-BF CPU spec list, wherein the number N of CPU cores (N core numbers are set as a set N), the number of cores (m) can increase the fundamental frequency to be P1_ Hi, and the number of cores (N-m) can reduce the fundamental frequency to be P1_ Lo.

sixthly, the set of Y is N;

therefore, m CPU core numbers with frequencies P1_ Hi to be increased are randomly generated from the set Y by using a random function, and the core number set of the m cores randomly generated from the set Y is assumed to be X, and other core number sets Z-N-X are set to be P1_ Lo.

⑧Y＝Z

ninthly, the wrmsr is used for changing the fundamental frequency of the corresponding core (set X) into P1_ Hi through the sysfs interface, and the other core set Z is set to P1_ Lo

stress test is carried out on CPU for 30 minutes at R, frequency of each core of current CPU is captured in real time, comparison with result set forth in fifth step is carried out, actual value is not equal to theoretical valueCan exceed 100 Mhz. If so, jump

Otherwise, outputting the stress fail by the screen

Checking the number s, s of data in the set Y>if m, jump, otherwise jump

m-s data are randomly generated from set Z to form set X with Y, Z equals N-X, execution ninc ends after the r.

As shown in fig. 2, the system 200 includes:

a parameter obtaining unit 210 configured to obtain the number of CPU cores and the number of scalable cores, and use the number of scalable cores as a single frequency-up number;

a random selection unit 220 configured to randomly select test cores from the CPU cores, where the selected number of the test cores is a single frequency-up number;

a function execution unit 230 configured to invoke an SST-BF function to perform frequency up-conversion on the test core and perform frequency down-conversion on cores other than the test core;

a pressurization test unit 240 configured to pressurize the CPU and collect the actual frequency of the test core during pressurization;

a frequency determining unit 250 configured to calculate a difference between the actual frequency and the frequency-up theoretical frequency, and determine whether the difference exceeds a preset threshold;

a failure determination unit 260 configured to determine that the test fails if the difference exceeds a preset threshold;

the pass determination unit 270 is configured to determine that the test passes if the difference does not exceed the preset threshold.

Optionally, as an embodiment of the present invention, the system further includes:

the state checking unit is configured for restarting the tester and checking whether the Activate PBF option state is an Enabled state;

Fig. 3 is a schematic structural diagram of a terminal system 300 according to an embodiment of the present invention, where the terminal system 300 may be used to execute the method for testing the stability of the CPU SST-BF function according to the embodiment of the present invention.

The terminal system 300 may include: a processor 310, a memory 320, and a communication unit 330. The components communicate via one or more buses, and those skilled in the art will appreciate that the architecture of the servers shown in the figures is not intended to be limiting, and may be a bus architecture, a star architecture, a combination of more or less components than those shown, or a different arrangement of components.

The memory 320 may be used for storing instructions executed by the processor 310, and the memory 320 may be implemented by any type of volatile or non-volatile storage terminal or combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The executable instructions in memory 320, when executed by processor 310, enable terminal 300 to perform some or all of the steps in the method embodiments described below.

The processor 310 is a control center of the storage terminal, connects various parts of the entire electronic terminal using various interfaces and lines, and performs various functions of the electronic terminal and/or processes data by operating or executing software programs and/or modules stored in the memory 320 and calling data stored in the memory. The processor may be composed of an Integrated Circuit (IC), for example, a single packaged IC, or a plurality of packaged ICs connected with the same or different functions. For example, the processor 310 may include only a Central Processing Unit (CPU). In the embodiment of the present invention, the CPU may be a single operation core, or may include multiple operation cores.

A communication unit 330, configured to establish a communication channel so that the storage terminal can communicate with other terminals. And receiving user data sent by other terminals or sending the user data to other terminals.

The present invention also provides a computer storage medium, wherein the computer storage medium may store a program, and the program may include some or all of the steps in the embodiments provided by the present invention when executed. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM) or a Random Access Memory (RAM).

Therefore, the invention randomly selects the test core and calls the SST-BF function to carry out frequency increasing setting on the test core and carry out frequency decreasing setting on other cores, then obtains the actual frequency of each core of the CPU by pressurizing the CPU, and verifies whether the SST-BF function is effective or not by comparing the actual frequency with the theoretical frequency. The CPU SST-BF function can be automatically turned on and the stability of the CPU SST-BF function can be tested, labor and test time are saved, meanwhile, all CPU cores can be covered, and test accuracy is improved.

Those skilled in the art will readily appreciate that the techniques of the embodiments of the present invention may be implemented as software plus a required general purpose hardware platform. Based on such understanding, the technical solutions in the embodiments of the present invention may be embodied in the form of a software product, where the computer software product is stored in a storage medium, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and the like, and the storage medium can store program codes, and includes instructions for enabling a computer terminal (which may be a personal computer, a server, or a second terminal, a network terminal, and the like) to perform all or part of the steps of the method in the embodiments of the present invention.

The same and similar parts in the various embodiments in this specification may be referred to each other. Especially, for the terminal embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant points can be referred to the description in the method embodiment.

In the embodiments provided in the present invention, it should be understood that the disclosed system and method can be implemented in other ways. For example, the above-described system embodiments are merely illustrative, and for example, the division of the units is only one logical functional division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, systems or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

Although the present invention has been described in detail by referring to the drawings in connection with the preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and these modifications or substitutions are within the scope of the present invention/any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A method for testing the functional stability of a CPU SST-BF is characterized by comprising the following steps:

if so, judging that the test is failed;

if not, the test is judged to be passed.

2. The method of claim 1, further comprising:

storing the CPU model with SST-BF function into a comparison list;

reading the CPU model of the tester;

judging whether the CPU model of the tester exists in a comparison list:

if not, outputting a CPU model error prompt.

3. The method of claim 1, further comprising:

importing the modified configuration file into the BIOS by using a SCELNX tool;

if yes, the SST-BF output function is started successfully;

if not, the output SST-BF function is failed to automatically start.

4. The method of claim 1, further comprising:

marking the cores which are subjected to frequency boosting;

if yes, randomly selecting a test core from the unmarked cores;

5. A CPU SST-BF functional stability test system is characterized by comprising:

6. The system of claim 5, further comprising:

7. The system of claim 5, further comprising:

8. The system of claim 5, further comprising:

9. A terminal, comprising:

a processor;

a memory for storing instructions for execution by the processor;

wherein the processor is configured to perform the method of any one of claims 1-4.

10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1-4.