CN111162087A - A 3D memory device and its manufacturing method - Google Patents
A 3D memory device and its manufacturing method Download PDFInfo
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- CN111162087A CN111162087A CN202010000390.8A CN202010000390A CN111162087A CN 111162087 A CN111162087 A CN 111162087A CN 202010000390 A CN202010000390 A CN 202010000390A CN 111162087 A CN111162087 A CN 111162087A
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
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Abstract
本发明公开了一种3D存储器件及其制作方法，在衬底上的堆叠层中形成栅极隔槽后，在栅极隔槽的侧壁和底部的表面上形成共源导体层，然后在形成有共源导体层的栅极隔槽内填充第一填充物、第二填充物以及第三填充物，共源导体层、第一填充物、第二填充物和第三填充物共同构成阵列共源极，且第二填充物的应力系数小于第一填充物的应力系数，第一填充物的应力系数小于第三填充物的应力系数。本发明在栅极隔槽中填充应力系数较小的第一填充物和第二填充物可以较大程度的降低阵列共源极的整体应力系数，避免晶圆由于应力而导致的弯曲，提高了存储器件的性能。
The invention discloses a 3D memory device and a manufacturing method thereof. After forming gate spacer grooves in a stack layer on a substrate, a common source conductor layer is formed on the sidewalls and the bottom surface of the gate spacer grooves, and then a common source conductor layer is formed on the surface of the sidewall and bottom of the gate spacer groove. The first filler, the second filler and the third filler are filled in the gate spacer formed with the common source conductor layer, and the common source conductor layer, the first filler, the second filler and the third filler together form an array The source electrode is common, and the stress coefficient of the second filler is smaller than that of the first filler, and the stress coefficient of the first filler is smaller than that of the third filler. In the present invention, filling the first filler and the second filler with smaller stress coefficients in the gate spacer can greatly reduce the overall stress coefficient of the common source of the array, avoid the bending of the wafer due to stress, and improve the memory device performance.
Description
Technical Field
The invention relates to the field of semiconductor devices and manufacturing thereof, in particular to a 3D memory device and a manufacturing method thereof.
Background
The NAND memory device is a nonvolatile memory product having low power consumption, light weight, and excellent performance, and is widely used in electronic products. NAND devices of a planar structure have been approaching the limit of practical expansion, and in order to further improve the memory capacity and reduce the memory cost per bit, 3D NAND memory devices have been proposed. In the 3D NAND memory device structure, a mode of vertically stacking a plurality of layers of grids is adopted, the central area of a stacking layer is an array storage area, the edge area of the stacking layer is a step structure, the array storage area is used for forming a memory cell string, a conductive layer in the stacking layer is used as a grid line of each layer of memory cells, and the grid line is led out through a contact structure on the step, so that the stacking type 3D NAND memory device is realized.
However, with the development of 3D NAND memory technology, the number of stacked layers is increased, the thickness of the stacked layers is increased, and the wafer is prone to bending, and if the bending of the wafer is beyond the specification range, the bonding failure is likely to be caused in the subsequent bonding process. Accordingly, it is desirable to further improve the structure of the 3D memory device and the method of manufacturing the same to improve the yield and reliability of the 3D memory device.
Disclosure of Invention
The embodiment of the invention provides a 3D memory device and a manufacturing method thereof, which can avoid the bending of a wafer caused by stress and improve the performance of the memory device.
An embodiment of the present invention provides a 3D memory device, including:
a substrate;
the stacked layer is formed on the substrate and comprises a plurality of gate conductor layers and interlayer insulating layers which are stacked alternately;
a gate spacer extending in a first direction of the stacked layers and vertically separating the stacked layers to have sidewalls and a bottom;
an array common source formed within the gate spacer and comprising:
the common source conductor layer is positioned on the surfaces of the side wall and the bottom of the grid isolation groove;
the first filler is positioned in the grid isolation groove and is surrounded by the common source conductor layer;
the second filler is positioned in the grid isolation groove and is surrounded by the first filler;
the third filler is positioned in the grid isolation groove and positioned on the first filler and the second filler;
wherein the stress coefficient of the second filler is smaller than the stress coefficient of the first filler, and the stress coefficient of the first filler is smaller than the stress coefficient of the third filler.
Optionally, the first filler is surrounded by the common source conductor layer.
Optionally, the second filler is surrounded by the first filler.
Optionally, the material of the first filler is polysilicon; the material of the second filler is silicon oxide; the third filler is made of metal tungsten; the material of the common source conductor layer is one of titanium and titanium nitride.
Optionally, the substrate includes a doped region, and the array common source is located on the doped region; the doped region comprises one of a P-type doped region and an N-type doped region.
An embodiment of the present invention further provides a 3D memory device, including:
a substrate;
the stacked layer is formed on the substrate and comprises a plurality of gate conductor layers and interlayer insulating layers which are stacked alternately;
a gate spacer extending in a first direction of the stacked layers and vertically separating the stacked layers to have sidewalls and a bottom;
an array common source formed within the gate spacer and comprising:
the first common source conductor layer is positioned on the surfaces of the side wall and the bottom of the grid isolation groove;
the polycrystalline silicon layer is positioned in the grid electrode separation groove and is surrounded by the first common source conductor layer;
the dielectric layer is positioned in the grid separation groove and is surrounded by the polycrystalline silicon layer;
and the second common source conductor layer is positioned in the grid isolation groove and positioned on the polycrystalline silicon layer and the dielectric layer.
Optionally, the polysilicon layer is surrounded by the first common source conductor layer.
Optionally, the dielectric layer is surrounded by the polysilicon layer.
Optionally, the dielectric layer is made of silicon oxide; the material of the first common source conductor layer comprises one of titanium and titanium nitride; the second common source conductor layer is made of metal tungsten.
Optionally, the substrate includes a doped region, and the array common source is located on the doped region; the doped region comprises one of a P-type doped region and an N-type doped region.
The embodiment of the invention also provides a manufacturing method of the 3D memory device, which comprises the following steps:
forming a stacked layer including a plurality of gate layers and interlayer insulating layers alternately stacked on a substrate;
forming gate isolation grooves extending along a first direction of the stacked layers and longitudinally separating the stacked layers from one another; the grid spacer groove is provided with a side wall and a bottom;
forming a common source conductor layer on the surface of the sidewall and the bottom of the gate spacer;
filling a first filler surrounded by the common source conductor layer in the gate isolation groove;
filling a second filler surrounded by the first filler in the gate isolation groove;
filling a third filler on the first filler and the second filler in the gate isolation groove; the common source conductor layer, the first filler, the second filler and the third filler form an array common source, the stress coefficient of the second filler is smaller than that of the first filler, and the stress coefficient of the first filler is smaller than that of the third filler.
Optionally, the manufacturing method further includes the following steps:
filling the first filler between the second filler and the third filler such that the second filler is surrounded by the first filler.
Optionally, the manufacturing method further includes the following steps:
filling the common source conductor layer between the first filler and the third filler such that the first filler is surrounded by the common source conductor layer.
Optionally, the material of the first filler is polysilicon; the material of the second filler is silicon oxide; the third filler is made of metal tungsten; the material of the common source conductor layer comprises one of titanium and titanium nitride.
The invention has the beneficial effects that: in the 3D memory device and the manufacturing method thereof provided by the invention, the common source conductor layer is formed on the side wall and the surface of the bottom of the gate isolation groove, then the gate isolation groove is filled with the first filler with a smaller stress coefficient, the second filler with a smaller stress coefficient than the first filler, and the third filler which is electrically connected with the common source conductor layer and used for conducting electricity, the common source conductor layer, the first filler, the second filler and the third filler jointly form the array common source, the stress coefficients of the first filler and the second filler are smaller, the stress coefficient of the second filler is smaller than that of the first filler, the overall stress coefficient of the array common source can be greatly reduced, in addition, the first filler and the second filler are positioned below the third filler, namely at the position where the stress is relatively concentrated, and the first filler and the second filler with smaller stress coefficients can effectively reduce the strain, therefore, the wafer is prevented from being bent due to stress, and the performance of the memory device is improved.
Drawings
The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.
FIG. 1 is a schematic diagram of a partial structure of a 3D memory device according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a partial structure of another 3D memory device according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a partial structure of another 3D memory device according to an embodiment of the present invention;
FIG. 4 is a schematic partial structure diagram of another 3D memory device according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a partial structure of another 3D memory device according to an embodiment of the present invention;
FIG. 6 is a schematic block diagram illustrating a flow chart of a method for fabricating a 3D memory device according to an embodiment of the present invention;
fig. 7a to 7i are schematic structural diagrams in another method for manufacturing a 3D memory device according to an embodiment of the present invention.
Detailed Description
Specific structural and functional details disclosed herein are merely representative and are provided for purposes of describing example embodiments of the present invention. The present invention may, however, be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present invention, it is to be understood that the terms "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified. Furthermore, the term "comprises" and any variations thereof is intended to cover non-exclusive inclusions.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
In a 3D memory device of NAND architecture, the gate conductors of the select transistors and the memory transistors are provided using stacked layers, and the source interconnections of the memory cell strings are implemented using Array common sources (Array common sources) that extend through the stacked layers. The array common source is formed by filling a metal material (for example, metal tungsten) in the gate isolation groove penetrating through the stacked layers, and the wafer is easy to bend due to the large stress coefficient of the metal material, and if the bending degree of the wafer exceeds the specification range, bonding failure is likely to be caused in the subsequent bonding process, so that the yield of products is greatly reduced. In order to improve the problem, polysilicon with a smaller stress coefficient and a metal material surrounding the polysilicon can be filled in the gate isolation groove, and the metal material with a larger stress coefficient can be prevented from being completely filled in the gate isolation groove on the premise of not influencing the realization of the interconnection of the source electrodes of the memory cell strings, so that the bending of a wafer caused by stress is avoided, and the performance of the device is improved. However, with the development of 3D NAND memory technology, the number of stacked layers in the memory device is increased, which results in an increased thickness of the common source of the array, and is more likely to cause wafer bending, and the filling of polysilicon and metal material in the gate spacer is not enough to solve the problem of wafer bending.
In order to solve the above problems, the present invention proposes a further improved 3D memory device and a method of fabricating the 3D memory device.
As shown in fig. 1, an embodiment of the present invention provides a 3D memory device 1. The 3D memory device 1 comprises a substrate 2, a stack of layers 3, gate spacers 4 and an array common source 5. The substrate 2 is a semiconductor substrate, and may be, for example, a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) or a GOI (Germanium On Insulator) substrate. Of course, the substrate 2 may also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP, SiC, or the like, may also be a stacked structure, such as Si/SiGe, or the like, and may also include other epitaxial structures, such as SGOI (silicon germanium on insulator) or the like.
The stack layer 3 is formed on the substrate 2, and includes a plurality of gate layers (specifically, gate conductor layers 31) and interlayer insulating layers 32 which are alternately stacked; the material of the gate conductor layer 31 includes, but is not limited to, tungsten, cobalt, copper, aluminum, doped silicon, or doped silicide, and the material of the interlayer insulating layer 32 includes, but is not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride. The stacked layer 3 is used for forming a memory cell string 6 perpendicular to the substrate 2 therein, the memory cell string 6 is a memory device connected in sequence along the direction perpendicular to the substrate 2, each layer of the gate conductor layer 31 and the memory cell string 6 form one memory cell, the more layers of the gate conductor layer 31 and the interlayer insulating layer 32 in the stacked layer 3, the more memory cells are formed, and the higher the integration degree of the device is. The Gate conductor layer 31 in the stack layer 3 includes a Gate layer of the memory cell and a Gate layer of the select Gate, wherein the select Gate may include a Source Select Gate (SSG) and a Drain Select Gate (DSG).
Specifically, the memory cell string 6 includes a channel hole 61, a memory function layer 62 and a channel layer 63 sequentially formed in the channel hole 61; the channel hole 61 penetrates the stacked layer 3 to the substrate 2, the channel layer 63 is formed on the sidewall of the memory function layer 62 and the bottom of the channel hole 61, and is in contact with the epitaxial structure 64, and a filler of an insulating material may be further formed between the channel layers 63. The memory function layer 62 includes a first blocking layer, a charge storage layer, and a Tunneling layer (not shown) sequentially formed in the channel hole 61; wherein the material of the first barrier layer comprises an oxide, such as silicon oxide; the material of the charge storage layer includes an insulating layer containing quantum dots or nanocrystals, such as silicon nitride containing metal or semiconductor particles; the tunneling layer material includes an oxide, such as silicon oxide.
Specifically, the bottom of the channel hole 61 is also formed with an epitaxial structure 64, the epitaxial structure 64 is formed by epitaxially growing a semiconductor material on the substrate 2 to serve as a channel of the lower gate device of the memory cell string 6, and the bottom gate conductor layer 31 in the stacked layer 3 will serve as a gate of the lower gate device. The upper conductor layer of the memory cell string 6 may be used to form the upper gate device of the memory cell string 6.
The gate spacer 4 extends along a first direction of the stacked layers 3 and vertically and longitudinally separates the stacked layers 3, the gate spacer 4 has a sidewall and a bottom, and specifically, the gate spacer 4 may extend toward the substrate 2. The array common source 5 is formed in the gate isolation groove 4 and is used for realizing source common connection of the memory cell string 6. The array common source 5 includes a common source conductor layer 51 filled in the gate spacer 4, a first filler 52, a second filler 53, and a third filler 54. Specifically, the common source conductor layer 51 is located on the surface of the sidewall and the bottom of the gate spacer 4; the first filler 52 is surrounded by the common source conductor layer 51 (the first filler 52 is in contact with the sidewalls and bottom of the common source conductor layer 51); the second filler 53 is surrounded by the first filler 52 (the second filler 53 is in contact with the side wall and the bottom of the first filler 52), however, as shown in fig. 2, the second filler 53 may also be surrounded by the first filler 52, i.e. the first filler 52 completely wraps the second filler 53; the third filler 54 is located on the first filler 52 and the second filler 53 (e.g., when the second filler 53 is surrounded by the first filler 52), or the third filler 54 is located on the first filler 52 (e.g., when the second filler 53 is surrounded by the first filler 52); wherein the stress coefficient of the second filler 53 is smaller than the stress coefficient of the first filler 52, and the stress coefficient of the first filler 52 is smaller than the stress coefficient of the third filler 54.
Specifically, the material of the first filler 52 includes polysilicon; the material of the second filler 53 includes silicon oxide or other material with a small stress coefficient; the material of the third filler 54 includes metallic tungsten or other conductive material; the material of the common source conductor layer 51 includes titanium or titanium nitride, but may be other conductive materials. The third filler 54 is electrically connected to the common source conductor layer 51, and is filled in the opening of the gate isolation trench 4, so as to increase the contact area with the upper contact, which is beneficial to achieving the stability of electrical connection with the upper structure.
Specifically, the substrate 2 may further include a doped region 7 as a source region of the lower gate tube, the doped region 7 extends along the first direction of the stack layer 3, and the array common source 5 is located on the doped region 7 and is in contact with the doped region 7. The doped region 7 may be formed by heavy doping, specifically including P-type doping or N-type doping.
Specifically, the second barrier layer 33 may be disposed between the gate conductor layer 31 and the common source conductor layer 51, and the material of the second barrier layer 33 includes a metal compound; a conductor layer 34 made of the same material as the common source conductor layer 51 can be further arranged between the gate conductor layer 31 and the interlayer insulating layer 32, and one side of the conductor layer 34 close to the first barrier layer is flush with one side of the gate conductor layer 31 close to the first barrier layer and is in contact with the first barrier layer; a third barrier layer 35 of high dielectric constant, such as alumina, may also be disposed between the conductor layer 34 and the interlayer insulating layer 32, the third barrier layer 35 also being located between the interlayer insulating layer 32 and the common source conductor layer 51. Meanwhile, the conductor layer 34 is also located between the gate conductor layer 31 and the memory cell string 6, and the third barrier layer 35 is also located between the conductor layer 34 and the memory cell string 6.
Specifically, a fourth barrier layer 36 may be further disposed between the bottom gate conductor layer 31 in the stacked layer 3 and the memory cell string 6, the substrate 2, and the gate spacer 4, respectively, and the fourth barrier layer 36 is specifically located between the third barrier layer 35 and the memory cell string 6, the substrate 2, and the gate spacer 4; in addition, a fifth barrier layer 37 may be further disposed between the top gate conductor layer 31 in the stacked layer 3 and the upper interlayer insulating layer 32, and the fifth barrier layer 37 is specifically located between the third barrier layer 35 and the upper interlayer insulating layer 32, and is located between the gate isolation trench 4 and the memory cell string 6; the material of the fourth barrier layer 36 and the fifth barrier layer 37 includes an oxide, such as silicon oxide.
In this embodiment, the common-source conductor layer 51 is formed on the surface of the sidewall and the bottom of the gate isolation trench 4, and then the gate isolation trench 4 formed with the common-source conductor layer 51 is filled with the first filler 52 with a smaller stress coefficient, the second filler 53 with a smaller stress than the first filler 52, and the third filler 54 for electrically connecting with the common-source conductor layer 51 and for conducting electricity, the common-source conductor layer 51, the first filler 52, the second filler 53, and the third filler 54 together constitute the array common-source 5, the stress coefficients of the first filler 52 and the second filler 53 are smaller, and the stress coefficient of the second filler 53 is smaller than the stress coefficient of the first filler 52, so that the overall stress coefficient of the array common-source 5 can be greatly reduced, and the first filler 52 and the second filler 53 are located below the third filler 54, that is, at a position where the stress is relatively concentrated, the first filler 52 and the second filler 53 with smaller stress coefficients can effectively reduce strain, thereby preventing the wafer from bending due to stress and improving the performance of the memory device.
As shown in fig. 3 and 4, an embodiment of the present invention also provides a 3D memory device 1. The difference from the above-described embodiment is that the first filler 52 is surrounded by the common source conductor layer 51, i.e. the common source conductor layer 51 is also located between the first filler 52 and the third filler 54, and the common source conductor layer 51 completely wraps the first filler 52 and is in contact with the third filler 54 above the first filler 52.
In this embodiment, on one hand, the third filler 54 is also a conductive material, and the common-source conductor layer 51 is located between the first filler 52 and the third filler 54, so that the contact area between the common-source conductor layer 51 and the third filler 54 is increased, which is favorable for the stability of electrical connection; on the other hand, when the first filler 52 is polysilicon and the third filler 54 is a metal material, the adhesion between the first filler 52 and the third filler 54 is poor, which easily causes the position of the third filler 54 to shift relative to the first filler 52, thereby causing unstable device performance, and the common-source conductor layer 51 and the third filler 54 are both made of metal materials, which have good adhesion, so that the common-source conductor layer 51 is located between the first filler 52 and the third filler 54, thereby avoiding the position shift of the first filler 52 and the third filler 54 due to the poor adhesion, and facilitating to improve the yield and performance of the memory device.
As shown in fig. 5, an embodiment of the present invention also provides a 3D memory device 1. The 3D memory device 1 includes a substrate 2, and the substrate 2 is a semiconductor substrate, and may be, for example, a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) or a GOI (Germanium On Insulator) or the like. Of course, the substrate 2 may also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP, SiC, or the like, may also be a stacked structure, such as Si/SiGe, or the like, and may also include other epitaxial structures, such as SGOI (silicon germanium on insulator) or the like.
The stack layer 3 is formed on the substrate 2, and includes a plurality of gate conductor layers 31 and interlayer insulating layers 32 stacked alternately; the material of the gate conductor layer 31 includes, but is not limited to, tungsten, cobalt, copper, aluminum, doped silicon, or doped silicide, and the material of the interlayer insulating layer 32 includes, but is not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride. The stacked layer 3 is used to form therein a memory cell string 6 in a direction perpendicular to the substrate 2.
The gate spacer 4 extends in a first direction of the stacked layers 3 and vertically separates the stacked layers 3, the gate spacer 4 having sidewalls and a bottom. The array common source 5 is formed in the gate isolation groove 4 and is used for realizing source common connection of the memory cell string 6. The array common source 5 includes a first common source conductor layer 510 filled in the gate spacer 4, a polysilicon layer 520, a dielectric layer 530, and a second common source conductor layer 540. Specifically, the first common source conductor layer 510 is located on the surface of the sidewall and the bottom of the gate isolation trench 4; the polysilicon layer 520 is surrounded by the first common source conductor layer 510, that is, the polysilicon layer 520 is completely wrapped by the first common source conductor layer 510; the dielectric layer 530 is surrounded by the polysilicon layer 520, i.e., the polysilicon layer 520 completely wraps the dielectric layer 530; the second common source conductor layer 540 is located above the polysilicon layer 520 and surrounded by the first common source conductor layer 510.
The first common source conductor layer 510 is in contact with the second common source conductor layer 540 above the polysilicon layer 520, which can increase the contact area between the first common source conductor layer 510 and the second common source conductor layer 540 to enhance the stability of electrical connection, and can also prevent the second common source conductor layer 540 from shifting due to poor adhesion between the second common source conductor layer 540 and the polysilicon layer 520, thereby facilitating the improvement of yield and performance of the memory device.
Specifically, the material of the dielectric layer 530 includes silicon oxide or other dielectric material with a relatively small stress coefficient; the material of the first common source conductor layer 510 includes titanium or titanium nitride, or a conductive material thereof; the material of the second common source conductor layer 540 includes metal tungsten or other conductive material.
Specifically, the substrate 2 may further include a doped region 7 as a source region of the lower gate tube, the doped region 7 extends along the first direction of the stack layer 3, and the array common source 5 is located on the doped region 7 and is in contact with the doped region 7. The doped region 7 may be formed by heavy doping, specifically including P-type doping or N-type doping.
In this embodiment, a first common source conductor layer 510 is formed on the surface of the sidewall and the bottom of the gate isolation trench 4, and then the gate isolation trench 4 formed with the first common source conductor layer 510 is filled with a polysilicon layer 520, a dielectric layer 530 and a second common source conductor layer 540, where the first common source conductor layer 510, the polysilicon layer 520, the dielectric layer 530 and the second common source conductor layer 540 together form an array common source 5, where the stress coefficients of the polysilicon layer 520 and the dielectric layer 530 are smaller than those of the first common source conductor layer 510 and the second common source conductor layer 540, so as to reduce the overall stress coefficient of the array common source 5 to a greater extent, and the polysilicon layer 520 and the dielectric layer 530 are located below the second common source conductor layer 540, that is, at a position where the stress is relatively concentrated, and the polysilicon layer 520 and the dielectric layer 530 with smaller stress coefficients can effectively reduce the strain, thereby preventing the wafer from bending due to the stress, the performance of the memory device is improved.
As shown in fig. 6 and fig. 1, an embodiment of the present invention provides a method for manufacturing a 3D memory device, including the steps of:
step S601: a stacked layer including a plurality of gate layers and interlayer insulating layers stacked alternately is formed on a substrate.
Specifically, the stacked layer 3 is used to form a memory cell string 6 therein in a direction perpendicular to the substrate 2, the gate layer 31 in the stacked layer 3 serves as a gate of each layer of memory cells in the memory cell string 6, and each layer of the gate layer 31 and the memory cell string 6 constitute one memory cell.
Specifically, the stacked layer 3 may be formed by a gate-last process, in which a plurality of sacrificial layers and interlayer insulating layers 32 stacked alternately are formed on the substrate 2, and then the sacrificial layers are replaced with gate conductor layers 31 in a subsequent step. Specifically, the material of the sacrificial layer includes silicon nitride, the material of the interlayer insulating layer 32 includes silicon oxide, and the material of the gate conductor layer 31 includes metal tungsten. After the stacked layer 3 is formed, a memory cell string 6 that penetrates the stacked layer 3 and is in contact with the substrate 2 may be formed in the stacked layer 3. Therefore, for convenience, the sacrificial layer and the gate conductor layer 31 formed by the gate-last process are collectively referred to as a gate layer, and the gate layer and the gate conductor layer are also denoted by the same reference numerals in the drawings.
Specifically, before the stacked layer 3 is formed, a doped region 7 may be formed on the substrate 2 through a doping process to serve as a source region of the memory cell string 6, the doped region 7 extends along a first direction of the stacked layer 3, and the array common source 5 is located on the doped region 7; the doped region 7 specifically comprises a P-type doping or an N-type doping. Of course, the doped region 7 may be formed on the substrate 2 after the gate spacer 4 is formed, which is not limited herein.
Step S602: forming grid isolation grooves which extend along the first direction of the stacked layers and vertically separate the stacked layers; the gate spacer has sidewalls and a bottom.
Specifically, the stacked layer 3 may be etched by an etching technique until reaching the substrate 2, thereby forming the gate line isolation trench. In the gate-last process, the gate line trench is used to remove and replace the sacrificial layer in the stack layer 3 with the gate conductor layer 31, and a second barrier layer 33 may be formed between the gate conductor layer 31 and the sidewall (common source conductor layer 51) of the gate trench 4 for isolating the gate conductor layer 31 and the common source conductor layer 51 formed in the gate trench 4.
Step S603: common source conductor layers are formed on the surfaces of the sidewalls and bottom of the gate spacer.
Specifically, a common source conductor layer 51 is deposited on the surface of the side wall and the bottom of the gate isolation groove 4; wherein the material of the common-source conductor layer 51 includes titanium or titanium nitride, and ALD (atomic layer deposition), CVD (chemical vapor deposition), PVD (physical vapor deposition) or other suitable methods may be used to form the common-source conductor layer 51. Of course, before the common-source conductor layer 51 is formed, an insulating barrier layer (not shown) may be formed on the sidewall of the gate spacer 4 to further isolate the gate conductor layer 31 from the common-source conductor layer 51 formed in the gate spacer 4.
Step S604: and filling a first filler surrounded by the common source conductor layer in the gate isolation groove.
Specifically, a first filler 52 is deposited on the surface of the common source conductor layer 51; wherein the material of the second filler 53 includes polysilicon, ALD, CVD, PVD or other suitable methods may be used to form the first filler 52.
Step S605: and filling a second filler surrounded by the first filler in the gate isolation groove.
Specifically, the second filler 53 is partially filled in the gate isolation trench 4 filled with the common source conductor layer 51 and the first filler 52, so that the second filler 53 is surrounded by the first filler 52, and the first filler 52 and the second filler 53 are etched back.
Step S606: filling third fillers positioned on the first fillers and the second fillers in the grid isolation grooves; the common source conductor layer, the first filler, the second filler and the third filler form an array common source, the stress coefficient of the second filler is smaller than that of the first filler, and the stress coefficient of the first filler is smaller than that of the third filler.
Specifically, after the third filler 54 is filled, a planarization process, such as chemical mechanical polishing, is performed on the end of the stacked layer 3 away from the substrate 2, so that the third filler 54, the common source conductor layer 51, and the end of the stacked layer 3 away from the substrate 2 are flush, and the array common source 5 located in the gate isolation trench 4 is obtained.
In this embodiment, in the present embodiment, the common source conductor layer 51 is formed on the surface of the sidewall and the bottom of the gate isolation trench 4, and then the gate isolation trench 4 is filled with the first filler 52 with a smaller stress coefficient, the second filler 53 with a smaller stress coefficient than the first filler 52, and the third filler 54 for electrically connecting with the common source conductor layer 51 and for conducting electricity, the common source conductor layer 51, the first filler 52, the second filler 53, and the third filler 54 together form the array common source 5, the stress coefficients of the first filler 52 and the second filler 53 are smaller, and the stress coefficient of the second filler 53 is smaller than that of the first filler 52, so that the overall stress coefficient of the array common source 5 can be greatly reduced, and the first filler 52 and the second filler 53 are located below the third filler 54, that is, at a position where the stress is relatively concentrated, the first filler 52 and the second filler 53 with smaller stress coefficients can effectively reduce strain, thereby preventing the wafer from bending due to stress and improving the performance of the memory device.
As shown in fig. 7a to 7i, the present invention further provides a manufacturing method of the 3D memory device 1, which is different from the above embodiments in that the manufacturing method of the 3D memory device 1 further includes filling the first filler 52 between the second filler 53 and the third filler 54, and filling the common source conductor layer 51 between the first filler 52 and the third filler 54, so that the first filler 52 is surrounded by the common source conductor layer 51, and the second filler 53 is surrounded by the first filler 52.
Specifically, the array common source 5 is formed by the following steps:
as shown in fig. 7a, depositing a common source conductor layer 51 on the surface of the sidewall and the bottom of the gate isolation trench 4, forming a first isolation trench 55 with the common source conductor layer 51 as the sidewall and the bottom; wherein the material of the common source conductor layer 51 includes titanium or titanium nitride, and ALD, CVD, PVD or other suitable methods may be used to form the common source conductor layer 51.
As shown in fig. 7b, a layer of first filler 52 is deposited on the sidewalls and bottom of the first trenches 55, forming second trenches 56 with the first filler 52 as sidewalls and bottom; wherein the material of the second filler 53 includes polysilicon, ALD, CVD, PVD or other suitable methods may be used to form the first filler 52.
As shown in fig. 7c and 7d, depositing a second filler 53 in the second isolation trench 56, and performing a back etching on the second filler 53 to form a third isolation trench 57 with the first filler 52 as a sidewall and the second filler 53 as a bottom; the material of the second filler 53 includes silicon oxide or other material with a small stress coefficient, and ALD, CVD, PVD or other suitable methods may be used to deposit the second filler 53, in this embodiment, ALD is used to deposit the second filler 53.
As shown in fig. 7e and 7f, the first filler 52 is again deposited in the third isolation trench 57, and the twice deposited first filler 52 is etched back to form a fourth isolation trench 58 with the common source conductor layer 51 as a sidewall and the first filler 52 as a bottom.
As shown in fig. 7g, a common source conductor layer 51 is deposited again on the sidewalls and bottom of the fourth isolation trench 58, and a fifth isolation trench 59 with the common source conductor layer 51 as sidewalls and bottom is formed.
As shown in fig. 7h and 7i, the fifth isolation trench 59 is filled with the third filler 54, and a planarization process, such as a chemical mechanical polishing process, is performed on an end of the stacked layer 3 away from the substrate 2, so that the third filler 54, the common-source conductor layer 51, and a side of the stacked layer 3 away from the substrate 2 are flush, resulting in the array common-source 5 located in the gate isolation trench 4.
In the present embodiment, the common source conductor layer 51 is formed on the surface of the sidewall and the bottom of the gate isolation trench 4, and then the first filler 52 with a smaller stress coefficient, the second filler 53 with a smaller stress coefficient than the first filler 52, and the third filler 54 for electrically connecting with the common source conductor layer 51 and for conducting electricity are filled in the gate isolation trench 4, the common source conductor layer 51, the first filler 52, the second filler 53, and the third filler 54 together form the array common source 5, the stress coefficients of the first filler 52 and the second filler 53 are smaller, and the stress coefficient of the second filler 53 is smaller than the stress coefficient of the first filler 52, so that the overall stress coefficient of the array common source 5 can be greatly reduced, and the first filler 52 and the second filler 53 are located below the third filler 54, that is, at a position where stress is relatively concentrated, the first filler 52 and the second filler 53 with a smaller stress coefficient can effectively reduce strain, therefore, the wafer is prevented from being bent due to stress, and the performance of the memory device is improved.
The embodiments in this specification are described in a progressive manner, and the same and similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from the other embodiments, and particularly, for the method embodiment, since it is substantially similar to the memory device embodiment, the description is simpler, and the related parts can be referred to the part of the memory device embodiment.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (14)
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| CN112331672A (en) * | 2020-11-05 | 2021-02-05 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
| CN111599818B (en) * | 2020-05-29 | 2021-03-19 | 长江存储科技有限责任公司 | Three-dimensional memory and method of making the same |
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