CN111159057A - System and method for recording accumulated power-on times of task machine under battery-free condition - Google Patents
System and method for recording accumulated power-on times of task machine under battery-free condition Download PDFInfo
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- CN111159057A CN111159057A CN201911271077.1A CN201911271077A CN111159057A CN 111159057 A CN111159057 A CN 111159057A CN 201911271077 A CN201911271077 A CN 201911271077A CN 111159057 A CN111159057 A CN 111159057A
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/16—Protection against loss of memory contents
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The embodiment of the invention discloses a system and a method for recording the accumulated power-on times of a task machine under the condition of no battery, wherein the system consists of a processor and an EEPROM (electrically erasable programmable read-only memory), and is connected and communicated through an IIC (inter-Integrated Circuit) interface in the processor; the accumulated power-on times of the processor are recorded through the EEPROM, and the data can be reserved when the equipment is powered down; the storage strategy is completed by mutual backup storage operation of the EEPROM, and the data in the EEPROM is refreshed after each power-on, so that the data recording function is completed by using an IIC interface inside the processor and matching the EEPROM, a peripheral circuit is simplified, and the project cost is saved; the accumulated power-on times are stored in a mutual backup mode, so that the accumulated power-on times can be recorded successfully when the EEPROM is powered off during refreshing storage. The embodiment of the invention solves the problems that the missile has strict requirements on the volume and space of the mission machine and does not have a large space arrangement counting device and a peripheral circuit.
Description
Technical Field
The present application relates to, but not limited to, the field of memory technologies, and in particular, to a system and method for recording the accumulated power-on times of a task machine in a battery-less situation.
Background
With the development and innovation of science and technology, more and more on-board electronic device processor reliability models need to evaluate the use times and the failure rate. The traditional device for recording the times completes counting and accumulating work through a small mechanical counting device driven by a battery. However, the missile has strict requirements on the volume and space of the mission machine, and a large space is not provided for arranging a counting device and a peripheral circuit.
Disclosure of Invention
In order to solve the above technical problems, embodiments of the present invention provide a system and a method for recording the accumulated power-on times of a mission machine without a battery, so as to solve the problem that the traditional counting device is not suitable for use because the missile has strict requirements on the volume and space of the mission machine and does not have a large space for arranging a counting device and a peripheral circuit.
The embodiment of the invention provides a system for recording the accumulated power-on times of a task machine under the condition of no battery, which comprises the following steps: a processor and a memory;
the processor is in data communication with the memory through an internal integrated circuit bus IIC interface and is used for executing a timing function through an internal timer;
the memory is provided with an address A and an address B which are mutually backed up, and is used for acquiring the accumulated times stored in the address of the processor when the processor is powered on every time, adding one to the accumulated times and writing the added times into the address A and the address B, so that the current accumulated times is used as the accumulated times when the processor is powered on next time under the condition that the processor is powered off.
Optionally, in the system for recording the accumulated power-on times of the task machine in the case of no battery as described above, the memory obtains the accumulated times stored in the address of the processor each time the processor is powered on, and adds one to the accumulated times and writes the added number into the address a and the address B, so that the current accumulated times is used as the accumulated times of the processor when the processor is powered off next time, including:
the memory is used for acquiring data in the address A and the address B when the processor is powered on, taking the number of correct accumulated checksums in the address A and the address B as the number of power-on times of this time, adding one to the number of power-on times of this time, and writing the added number into the address A and the address B as the accumulated number of power-on times of the processor at the next time.
Optionally, in the system for recording the accumulated power-on times of the mission machine without the battery as described above, the memory is an electrically erasable programmable read-only memory EEPROM;
the address A is 5 addresses of the EEPROM, starting from 0x0000 at address 0x 56; the address B is 5 addresses of the EEPROM starting from 0x0000 at address 0x 57.
Alternatively, in a system for recording the accumulated power-on times of a mission machine without a battery as described above,
the first 4 addresses of the address a and the address B starting from 0x0000 are used to store the accumulated number of times, and the 5 th address is used to store the checksum of the data in the first 4 addresses.
Alternatively, in a system for recording the accumulated power-on times of a mission machine without a battery as described above,
the EEPROM is used for writing all initial data of 5 addresses starting from 0x0000 of an address A as 0x00 and all initial data of 5 addresses starting from 0x0000 of an address B as 0x00 when the EEPROM is operated for the first time.
Optionally, in the system for recording the accumulated power-on times of the task machine in the battery-free condition as described above, the memory is configured to use the accumulated times of the checksums in the address a and the address B as the power-on times of this time, and includes:
the memory is used for judging whether the checksum in the address A and the address B is correct or not;
under the condition that the checksums in the address A and the address B are correct, taking the accumulated times in the address A or the address B as the times of the power-on;
under the condition that the checksum in the address A is correct and the checksum in the address B is wrong, taking the accumulated times in the address A as the times of power-on at this time;
under the condition that the checksum in the address B is correct and the checksum in the address A is wrong, taking the accumulated times in the address B as the times of power-on at this time;
and adding one to the power-on times, writing the power-on times into the address A and the address B as the accumulated times of the next power-on after the power-off of the processor.
The embodiment of the invention also discloses a method for recording the accumulated electrifying times of the task machine under the condition of no battery, which is implemented by adopting the system for recording the accumulated electrifying times of the task machine under the condition of no battery to record the accumulated electrifying times of the task machine under the condition of no battery, and comprises the following steps:
when the processor is powered on, acquiring data stored in a memory address A and a memory address B;
taking the number of correct check sums accumulated in the address A and the address B as the number of power-on times;
and adding one to the power-on times, and writing the added power-on times into the address A and the address B as the accumulated times of the next power-on of the processor.
Optionally, in the system for recording the accumulated power-on times of the task machine in the absence of the battery, taking the accumulated times of the checksums in the address a and the address B that are correct as the power-on times of this time includes:
judging whether the checksums in the address A and the address B are correct or not;
under the condition that the checksums in the address A and the address B are correct, taking the accumulated times in the address A or the address B as the times of the power-on;
under the condition that the checksum in the address A is correct and the checksum in the address B is wrong, taking the accumulated times in the address A as the times of power-on at this time;
under the condition that the checksum in the address B is correct and the checksum in the address A is wrong, taking the accumulated times in the address B as the times of power-on at this time;
and adding one to the power-on times, writing the power-on times into the address A and the address B as the accumulated times of the next power-on after the power-off of the processor.
The system and the method for recording the accumulated power-on times of the task machine under the condition of no battery provided by the embodiment of the invention use an EEPROM as a storage medium for recording the accumulated power-on times; the EEPROM is operated through the IIC interface in the processor, so that the internal resources of the processor are fully utilized, and the requirements of reducing electronic components and reducing cost are met; the accumulated power-on times are stored in the EEPROM in a mode that two storage addresses are mutually backed up, so that the accumulated power-on times can be successfully recorded when the EEPROM is powered off during refreshing storage. The system of the embodiment of the invention records the use times of the electronic equipment on the missile, uses the IIC interface in the processor to match with the EEPROM to complete the data recording function, simplifies the peripheral circuit and saves the project cost; in general, when the memory is refreshed, power failure can cause the failure of the whole stored data, and the data are stored in a mutual backup mode, so that the phenomenon can be avoided, and the stability of data storage for recording accumulated power-on times is enhanced.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.
Fig. 1 is a schematic structural diagram of a system for recording the accumulated power-on times of a task machine in the case of no battery according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a policy model for recording accumulated power-on times of a task machine in a system for recording accumulated power-on times of a task machine in the absence of a battery according to an embodiment of the present invention;
fig. 3 is a flowchart of a method for recording the accumulated power-on times of a task machine in the case of no battery according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
The embodiment of the invention provides a system for recording the accumulated power-on times of a task machine under the condition of no battery, which mainly solves the following technical problems:
1, evaluating the use times and failure rate of an on-missile core control processor;
2, the battery and the counting device are thrown away in a recording mode, so that the volume of the PCB is reduced; i.e. using as few electronic components as possible, for example, a counting device comprising a main processor, a memory and associated circuitry;
3, the counting device for recording the use times uses the internal and external devices of the processor as much as possible to control the manufacturing cost;
4, powering down at memory refresh time causes the recorded count data to be lost.
The technical solution provided by the present invention is explained in detail by several specific examples below. The following specific embodiments of the present invention may be combined, and the same or similar concepts or processes may not be described in detail in some embodiments.
Fig. 1 is a schematic structural diagram of a system for recording the accumulated power-on times of a task machine in the case of no battery according to an embodiment of the present invention. The system for recording the accumulated power-on times of the task machine under the condition of no battery provided by the embodiment can comprise: a processor and a Memory, such as an Electrically erasable programmable Read-Only Memory (EERPROM).
The system for recording the accumulated power-on times of the task machine under the condition of no battery in the embodiment of the invention consists of a main control processor and an EERPROM (slave device), and is connected with the EERPROM and carries out data communication through an Inter-Integrated Circuit (IIC) interface inside the processor; in addition, the processor performs a timing function by its internal timer.
The memory of the embodiment of the invention is provided with the address A and the address B which are mutually backed up, and is used for acquiring the accumulated times stored in the address of the processor when the processor is powered on every time, adding one to the accumulated times and writing the added times into the address A and the address B, thereby taking the current accumulated times as the accumulated times when the processor is powered on next time under the condition that the processor is powered off.
In practical application, the implementation manner of recording the power-on times and the next accumulated times by the memory may include:
and the memory is used for acquiring data in the address A and the address B when the processor is powered on, taking the number of correct accumulated checksums in the address A and the address B as the number of power-on times of this time, adding one to the number of power-on times of this time, and writing the added number into the address A and the address B as the accumulated number of power-on times of the processor at the next time.
Fig. 2 is a schematic diagram of a policy model for recording accumulated power-on times of a task machine in a system for recording accumulated power-on times of a task machine in the absence of a battery according to an embodiment of the present invention.
The storage strategy of the system provided by the embodiment of the invention is completed by mutual backup operation of the EEPROM, the strategy model is as shown in FIG. 2, a processor reads data in the EEPROM once after being electrified, and the recorded correct times data +1 is flashed into the address A and the address B by judging the checksum in the address A and the address B; and after the processor is powered off, the processor is powered on again to read the data in the address A and the address B firstly, and the data +1 with correct times is written into the address A and the address B by judging the checksums in the address A and the address B.
The system for recording the accumulated electrifying times of the task machine under the condition of no battery provided by the embodiment of the invention uses the EEPROM as a storage medium for recording the accumulated electrifying times; the EEPROM is operated through the IIC interface in the processor, so that the internal resources of the processor are fully utilized, and the requirements of reducing electronic components and reducing cost are met; the accumulated power-on times are stored in the EEPROM in a mode that two storage addresses are mutually backed up, so that the accumulated power-on times can be successfully recorded when the EEPROM is powered off during refreshing storage. The system of the embodiment of the invention records the use times of the electronic equipment on the missile, uses the IIC interface in the processor to match with the EEPROM to complete the data recording function, simplifies the peripheral circuit and saves the project cost; in general, when the memory is refreshed, power failure can cause the failure of the whole stored data, and the data are stored in a mutual backup mode, so that the phenomenon can be avoided, and the stability of data storage for recording accumulated power-on times is enhanced.
Alternatively, in the memory of the embodiment of the present invention, the address a may be 5 addresses of the EEPROM, where the address 0x56 starts from 0x 0000; address B may be 5 addresses of EEPROM, starting from 0x0000 at address 0x 57.
In the embodiment of the invention, the accumulated power-on times of the main control processor are recorded by the EEPROM, so that the data can be kept when the equipment is powered down. In order to avoid that the EEPROM is suddenly powered off during the execution of the write operation, causing data not to be updated to the EEPROM, two addresses, which are 5 addresses starting from 0x0000 of the EEPROM address 0x56 (address a) and 5 addresses starting from 0x0000 of the EEPROM address 0x57 (address B), are used to store the power-on cumulative number data. The two addresses are backed up with each other, so that the occurrence of recording data loss in the EEPROM caused by unexpected power failure of one of the addresses can be prevented.
According to the threshold analysis of the cumulative power-on number, a 32-bit data can satisfy the recording requirement (about 42 hundred million times), so that the stored value of the cumulative power-on number can be stored as a 32-bit data. However, one address in the EEPROM can store only one 8-bit data, so 32-bit data needs to be divided into 4 8-bit data, which are stored in the first 4 addresses starting from 0x0000, and in order to ensure the correctness of the data, the checksum of the data of the first four addresses is stored in the 5 th address; the checksum is byte 1+ byte 2+ byte 3+ byte 4, and if the checksum exceeds the 8-bit threshold, the lower 8 bits are selected.
In the embodiment of the present invention, when the EEPROM is operated for the first time, all 5 addresses of address a (0x56) of the EEPROM starting from 0x0000 need to be flashed to 0x00, and all 5 addresses of address B (0x57) of the EEPROM starting from 0x0000 need to be flashed to 0x 00; i.e. initially the cumulative power-up times is 0 and the checksum is also 0, and then this is not necessary.
Optionally, the memory in the embodiment of the present invention may use the number of correct checksums accumulated in the address a and the address B as an implementation manner of the number of power-on times, where the implementation manner of the number of power-on times includes:
the memory is used for judging whether the checksum in the address A and the address B is correct or not;
under the condition that the checksums in the address A and the address B are correct, taking the accumulated times in the address A or the address B as the times of the power-on;
under the condition that the checksum in the address A is correct and the checksum in the address B is wrong, taking the accumulated times in the address A as the times of power-on at this time;
under the condition that the checksum in the address B is correct and the checksum in the address A is wrong, taking the accumulated times in the address B as the times of power-on at this time;
and adding one to the power-on times, writing the power-on times into the address A and the address B as the accumulated times of the next power-on after the power-off of the processor.
In the embodiment of the invention, two addresses are stored in a backup mode, accumulated times data stored by the two addresses are read out firstly when the two addresses are powered on each time, the checksum of the data is calculated, whether the checksum is correct or not (incorrect may be that the last write fails) is judged, and the numerical value is updated according to the judgment of the checksum in three conditions: first, two numerical checksums are both correct (equal), and one of them is updated to two addresses as the number data + 1; second, if the first address value checksum is correct and the second address value checksum is incorrect, the first value is updated to two addresses as the number data + 1; third, if the first address value checksum is incorrect and the second address value checksum is correct, the second value is updated as count data +1 to both addresses.
Based on the system for recording the accumulated power-on times of the task machine under the condition of no battery provided by the embodiment of the invention, the embodiment of the invention also provides a method for recording the accumulated power-on times of the task machine under the condition of no battery, the method can be implemented by adopting the system provided by any embodiment of the invention, and the method comprises the following steps:
step 2, taking the number of correct check sums accumulated in the address A and the address B as the number of power-on times;
and 3, adding one to the power-on times, writing the power-on times into the address A and the address B as the accumulated times of the next power-on of the processor.
A policy model of the method for recording the accumulated power-on times of the task machine according to the embodiment of the present invention may be shown in fig. 2.
Optionally, fig. 3 is a flowchart of a method for recording the accumulated power-on times of the task machine in the case of no battery according to an embodiment of the present invention. The method provided by the embodiment of the invention can comprise the following steps:
s101, acquiring data of accumulated power-on times stored in an address A and an address B;
s102, judging whether the checksum of the data in the address A is correct or not; if the result is correct, executing S103, and if the result is incorrect, executing S105;
s103; judging whether the checksum of the data in the address B is correct or not; if the result is correct, executing S104, and if the result is incorrect, executing S106;
s104, taking the accumulated times in the address A or the address B as the reference accumulated times of the current electrifying data;
s105, taking the accumulated times in the address B as the reference accumulated times of the current electrifying data;
s106, taking the accumulated times in the address A as the reference accumulated times of the current electrifying data;
after S104 to S105, executing S107;
and S107, writing the reference times +1 into the address A and the address B, wherein the times are used as the times of next power-on after power-off.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (8)
1. A system for recording the cumulative power-on times of a task machine without a battery, comprising: a processor and a memory;
the processor is in data communication with the memory through an internal integrated circuit bus IIC interface and is used for executing a timing function through an internal timer;
the memory is provided with an address A and an address B which are mutually backed up, and is used for acquiring the accumulated times stored in the address of the processor when the processor is powered on every time, adding one to the accumulated times and writing the added times into the address A and the address B, so that the current accumulated times is used as the accumulated times when the processor is powered on next time under the condition that the processor is powered off.
2. The system for recording the accumulated power-on times of the task machine under the condition of no battery according to claim 1, wherein the memory acquires the accumulated times stored in the address of the processor during each power-on of the processor, and adds one to the accumulated times to write the accumulated times into the address A and the address B, so that the current accumulated times is taken as the accumulated times during the next power-on of the processor under the condition of power-off of the processor, and the system comprises:
the memory is used for acquiring data in the address A and the address B when the processor is powered on, taking the number of correct accumulated checksums in the address A and the address B as the number of power-on times of this time, adding one to the number of power-on times of this time, and writing the added number into the address A and the address B as the accumulated number of power-on times of the processor at the next time.
3. The system for recording the cumulative number of power-ups of a task machine without a battery of claim 2 wherein said memory is an EEPROM;
the address A is 5 addresses of the EEPROM, starting from 0x0000 at address 0x 56; the address B is 5 addresses of the EEPROM starting from 0x0000 at address 0x 57.
4. The system for recording the accumulated power-on times of a task machine without a battery according to claim 3,
the first 4 addresses of the address a and the address B starting from 0x0000 are used to store the accumulated number of times, and the 5 th address is used to store the checksum of the data in the first 4 addresses.
5. The system for recording the accumulated power-on times of a task machine without a battery according to claim 4,
the EEPROM is used for writing all initial data of 5 addresses starting from 0x0000 of an address A as 0x00 and all initial data of 5 addresses starting from 0x0000 of an address B as 0x00 when the EEPROM is operated for the first time.
6. The system for recording the accumulated power-on times of the task machine under the battery-free condition according to claim 5, wherein the memory is used for taking the accumulated times of the checksums in the address A and the address B as the correct accumulated times of the power-on of the current time, and comprises:
the memory is used for judging whether the checksum in the address A and the address B is correct or not;
under the condition that the checksums in the address A and the address B are correct, taking the accumulated times in the address A or the address B as the times of the power-on;
under the condition that the checksum in the address A is correct and the checksum in the address B is wrong, taking the accumulated times in the address A as the times of power-on at this time;
under the condition that the checksum in the address B is correct and the checksum in the address A is wrong, taking the accumulated times in the address B as the times of power-on at this time;
and adding one to the power-on times, writing the power-on times into the address A and the address B as the accumulated times of the next power-on after the power-off of the processor.
7. A method for recording the accumulated power-on times of a task machine in a battery-free situation, which is implemented by the system for recording the accumulated power-on times of the task machine in the battery-free situation according to any one of claims 1 to 6, and comprises the following steps:
when the processor is powered on, acquiring data stored in a memory address A and a memory address B;
taking the number of correct check sums accumulated in the address A and the address B as the number of power-on times;
and adding one to the power-on times, and writing the added power-on times into the address A and the address B as the accumulated times of the next power-on of the processor.
8. The system for recording the accumulated power-on times of the task machine under the battery-free condition according to claim 7, wherein the step of taking the accumulated times of the checksums in the address a and the address B as the correct accumulated times of the power-on of this time comprises:
judging whether the checksums in the address A and the address B are correct or not;
under the condition that the checksums in the address A and the address B are correct, taking the accumulated times in the address A or the address B as the times of the power-on;
under the condition that the checksum in the address A is correct and the checksum in the address B is wrong, taking the accumulated times in the address A as the times of power-on at this time;
under the condition that the checksum in the address B is correct and the checksum in the address A is wrong, taking the accumulated times in the address B as the times of power-on at this time;
and adding one to the power-on times, writing the power-on times into the address A and the address B as the accumulated times of the next power-on after the power-off of the processor.
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| CN111797031A (en) * | 2020-06-17 | 2020-10-20 | 江西洪都航空工业集团有限责任公司 | Method for recording power-on accumulated time of task machine by using EEPROM (electrically erasable programmable read-Only memory) under battery-free condition |
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