CN111128974A - Wafer stacking method and wafer stacking structure - Google Patents
Wafer stacking method and wafer stacking structure Download PDFInfo
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- CN111128974A CN111128974A CN201811296757.4A CN201811296757A CN111128974A CN 111128974 A CN111128974 A CN 111128974A CN 201811296757 A CN201811296757 A CN 201811296757A CN 111128974 A CN111128974 A CN 111128974A
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Abstract
本公开提供一种晶圆堆叠方法与晶圆堆叠结构。晶圆堆叠方法包括：提供第一晶圆，第一晶圆的上表面包括设置为连接于第一信号的第一焊盘和设置为连接于第二信号的第二焊盘；在第一晶圆上顺次制作第一下重布线层、第一上重布线层；将第二晶圆键合于第一上重布线层，第二晶圆的上表面包括设置为连接第一信号且位置对应于第二焊盘的第三焊盘、设置为连接第二信号且位置对应于第一焊盘的第四焊盘；在第二晶圆上对应于第一引线垫和第二引线垫的位置分别制作用于电连接第三焊盘的第一硅通孔和用于电连接第四焊盘的第二硅通孔，第一硅通孔的底部接触第一引线垫，第二硅通孔的底部接触第二引线垫。本公开提供的晶圆堆叠方法可以提高晶圆堆叠的良品率。
The present disclosure provides a wafer stacking method and a wafer stacking structure. The wafer stacking method includes: providing a first wafer, the upper surface of which includes a first pad configured to be connected to a first signal and a second pad configured to be connected to a second signal; The first lower redistribution layer and the first upper redistribution layer are sequentially fabricated on the circle; the second wafer is bonded to the first upper redistribution layer, and the upper surface of the second wafer includes a location set to connect to the first signal and A third pad corresponding to the second pad, a fourth pad arranged to connect to the second signal and positioned corresponding to the first pad; on the second wafer corresponding to the first lead pad and the second lead pad A first through-silicon via for electrically connecting the third pad and a second through-silicon via for electrically connecting the fourth pad are respectively made, the bottom of the first through-silicon via contacts the first lead pad, and the second through-silicon via The bottom of the hole contacts the second lead pad. The wafer stacking method provided by the present disclosure can improve the yield of wafer stacking.
Description
Technical Field
The present disclosure relates to the field of integrated circuit manufacturing technologies, and in particular, to a wafer stacking method capable of improving an electrical connection effect between wafers and a wafer stacking structure manufactured by using the wafer stacking method.
Background
Stacking multiple chips and establishing mechanical and electrical connections is an important method of reducing the volume of an integrated circuit during its manufacture. As shown in fig. 1A and 1B, in the prior art, a TSV (Through Silicon Vias) is usually fabricated for each chip to be stacked, a Bump (Micro-Bump) is then formed for each TSV, and finally, positioning and bonding are performed in a wafer-to-wafer or wafer-to-wafer manner, so as to electrically connect an upper chip and a lower chip Through each Bump and the TSV.
First, in the wafer-to-wafer or wafer-to-wafer bonding process, the inefficiency results in high costs. In addition, TSV needs to be made for each chip in advance, and bumps are made, so that the risk of positioning error and connection error is high in the bonding process, which easily causes disconnection of the electrical connection path between the upper and lower chips, and causes reduction of yield.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The present disclosure is directed to a wafer stacking method and a wafer stacking structure, which are used to overcome at least some of the disadvantages of high wafer stacking cost, high connection error probability, and low yield due to the limitations and defects of the related art.
According to a first aspect of the embodiments of the present disclosure, there is provided a wafer stacking method, including:
providing a first wafer, an upper surface of the first wafer comprising first pads configured to be connected to a first signal and second pads configured to be connected to a second signal;
sequentially manufacturing a first lower redistribution layer and a first upper redistribution layer on the first wafer, wherein the first lower redistribution layer comprises a first wire connected with the first pad and a second wire connected with the second pad, the first upper redistribution layer comprises a third wire connected with the first wire and a fourth wire connected with the second wire, the third wire comprises a first lead pad relatively close to the second pad in the horizontal direction, and the fourth wire comprises a second lead pad relatively close to the first pad in the horizontal direction;
bonding a second wafer to the first upper redistribution layer, wherein the upper surface of the second wafer comprises a third bonding pad arranged to be connected with the first signal and corresponding to the second bonding pad in position, and a fourth bonding pad arranged to be connected with the second signal and corresponding to the first bonding pad in position;
and manufacturing a first silicon through hole for electrically connecting the third bonding pad and a second silicon through hole for electrically connecting the fourth bonding pad on the second wafer at positions corresponding to the first lead pad and the second lead pad respectively, wherein the bottom of the first silicon through hole is contacted with the first lead pad, and the bottom of the second silicon through hole is contacted with the second lead pad.
In an exemplary embodiment of the present disclosure, the fabricating the first through silicon via for electrically connecting the third pad and the second through silicon via for electrically connecting the fourth pad includes:
manufacturing a first through hole and a second through hole in the second wafer at positions corresponding to the first lead pad and the second lead pad, wherein the first lead pad is exposed at the bottom of the first through hole, and the second lead pad is exposed at the bottom of the second through hole;
and filling a conductive material in the first through hole and the second through hole to form the first through silicon via and the second through silicon via.
In an exemplary embodiment of the present disclosure, further comprising:
in the process of manufacturing the first through hole and the second through hole, simultaneously manufacturing a groove for forming a second lower heavy wiring layer;
and in the process of filling the conductive material, simultaneously manufacturing a second lower heavy wiring layer in the groove, so that the first through silicon via is electrically connected with the third bonding pad and the second through silicon via is electrically connected with the fourth bonding pad.
In an exemplary embodiment of the present disclosure, further comprising:
and manufacturing a second lower heavy wiring layer on the second wafer, wherein the second lower heavy wiring layer comprises a fifth wiring electrically connected to the third bonding pad and the first through silicon via and a sixth wiring electrically connected to the fourth bonding pad and the second through silicon via.
In an exemplary embodiment of the present disclosure, further comprising:
forming a second upper redistribution layer on the second lower redistribution layer, the second upper redistribution layer including a seventh wiring electrically connected to the fifth wiring and an eighth wiring electrically connected to the sixth wiring, the seventh wiring including a third lead pad relatively close to the fourth pad in the horizontal direction, passing through the fourth lead pad in the horizontal direction but not intersecting the fourth lead pad; the eighth wire includes a fourth lead pad relatively close to the third pad in a horizontal direction, passing through the third lead pad in the horizontal direction but not intersecting the third lead pad.
According to a second aspect of the present disclosure, there is provided a wafer stack structure, comprising:
a first wafer having an upper surface including first pads configured to connect to a first signal and second pads configured to connect to a second signal;
a first lower redistribution layer on the first wafer, the first lower redistribution layer including a first wire electrically connected to the first pad and a second wire electrically connected to the second pad;
a first upper redistribution layer on the first lower redistribution layer, including a third wiring electrically connected to the first wiring and a fourth wiring electrically connected to the second wiring, the third wiring including a first lead pad relatively close to the second pad in a horizontal direction, the fourth wiring including a second lead pad relatively close to the first pad in the horizontal direction;
a second wafer, the bottom surface of which is attached to the first upper redistribution layer and is provided with a third pad corresponding to the second pad and configured to be connected with the first signal, a fourth pad corresponding to the first pad and configured to be connected with the second signal, a first through silicon via with a bottom electrically connected to the first lead pad, and a second through silicon via with a bottom electrically connected to the second lead pad;
a second lower rewiring layer located above the second wafer, including a fifth wire electrically connected to the first through silicon via and the third pad, and a sixth wire electrically connected to the second through silicon via and the fourth pad;
a second upper redistribution layer on the second lower redistribution layer, including a seventh wiring electrically connected to the fifth wiring and an eighth wiring electrically connected to the sixth wiring, the seventh wiring including a third lead pad relatively close to the fourth pad in a horizontal direction, the eighth wiring including a fourth lead pad relatively close to the third pad in the horizontal direction.
In an exemplary embodiment of the present disclosure, the wafer stack structure further includes:
a third wafer, a bottom surface of which is attached to the second upper redistribution layer, and which is provided with a fifth pad corresponding to the first pad and configured to connect the first signal, a sixth pad corresponding to the second pad and configured to connect the second signal, a third through silicon via whose bottom is electrically connected to the third lead pad, and a fourth through silicon via whose bottom is electrically connected to the fourth lead pad;
a third lower rewiring layer located above the third wafer, including a ninth wire electrically connected to the third through silicon via and the fifth pad, and a tenth wire electrically connected to the fourth through silicon via and the sixth pad;
a third upper redistribution layer on the third lower redistribution layer, including an eleventh wiring electrically connected to the ninth wiring and a twelfth wiring electrically connected to the tenth wiring, the eleventh wiring including a fifth lead pad relatively close to the sixth pad in a horizontal direction, the twelfth wiring including a sixth lead pad relatively close to the fifth pad in the horizontal direction.
According to a third aspect of the present disclosure, there is provided a chip stacking method comprising:
providing a wafer stack structure according to any one of the above;
and scribing and dividing the wafer stacking structure to form a preset number of chips.
According to a fourth aspect of the present disclosure, there is provided a chip stacking method comprising:
a first chip having an upper surface including a first pad configured to connect a first signal and a second pad configured to connect a second signal;
a first lower rewiring layer located above the first chip and including a first wire electrically connected to the first pad and a second wire electrically connected to the second pad;
a first upper redistribution layer on the first lower redistribution layer, including a third wiring electrically connected to the first wiring and a fourth wiring electrically connected to the second wiring, the third wiring including a first lead pad relatively close to the second pad in a horizontal direction, the fourth wiring including a second lead pad relatively close to the first pad in the horizontal direction;
a second chip, a bottom surface of which is attached to the first upper redistribution layer, and is provided with a third pad corresponding to the second pad and configured to be connected with the first signal, a fourth pad corresponding to the first pad and configured to be connected with the second signal, a first through-silicon-via having a bottom electrically connected to the first lead pad, and a second through-silicon-via having a bottom electrically connected to the second lead pad;
a second lower rewiring layer located on the second chip and including a fifth wire electrically connected to the first through-silicon via and the third pad, and a sixth wire electrically connected to the second through-silicon via and the fourth pad;
a second upper redistribution layer on the second lower redistribution layer, including a seventh wiring electrically connected to the fifth wiring and an eighth wiring electrically connected to the sixth wiring, the seventh wiring including a third lead pad relatively close to the fourth pad in a horizontal direction, the eighth wiring including a fourth lead pad relatively close to the third pad in the horizontal direction.
In an exemplary embodiment of the present disclosure, the chip stack structure further includes:
a third chip, a bottom surface of which is attached to the second upper redistribution layer, and which is provided with a fifth pad corresponding to the first pad and configured to connect the first signal, a sixth pad corresponding to the second pad and configured to connect the second signal, a third through-silicon via whose bottom is electrically connected to the third lead pad, and a fourth through-silicon via whose bottom is electrically connected to the fourth lead pad;
a third lower rewiring layer located above the third chip and including a ninth wire electrically connected to the third through silicon via and the fifth pad, and a tenth wire electrically connected to the fourth through silicon via and the sixth pad;
a third upper redistribution layer on the third lower redistribution layer, including an eleventh wiring electrically connected to the ninth wiring and a twelfth wiring electrically connected to the tenth wiring, the eleventh wiring including a fifth lead pad relatively close to the sixth pad in a horizontal direction, the twelfth wiring including a sixth lead pad relatively close to the fifth pad in the horizontal direction.
According to the wafer stacking method and the wafer stacking structure provided by the embodiment of the disclosure, through the mode of firstly bonding the wafers and then manufacturing the TSV and the mode of using the two layers of redistribution layers to realize signal connection between the wafers, the error of mechanical alignment and electric connection of the TSV in the related technology can be avoided, the electric connection between the TSVs can be realized only by manufacturing the mechanical connection between the wafers, salient points do not need to be manufactured, the negative influence of the salient points on the yield is reduced, the wafer stacking cost is reduced, and the yield is improved. In addition, the chips with the pad positions corresponding to the signals exchanged are stacked and electrically connected, so that the flexibility of the use of the chips can be improved, and the use efficiency of the chips is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
Fig. 1A and 1B are schematic diagrams of a chip stacking structure in the related art.
Fig. 2 is a flow chart of a wafer stacking method in an exemplary embodiment of the present disclosure.
Fig. 3A to 3D are schematic views illustrating a wafer stacking structure formed by applying the wafer stacking method according to an exemplary embodiment of the disclosure.
FIG. 4 is a flow chart of a wafer stacking method in yet another embodiment.
Fig. 5A and 5B are schematic views of a wafer stack structure formed by the wafer stacking method shown in fig. 4.
Fig. 6A and 6B are top views of the wafer stack structure shown in fig. 5B.
FIG. 7 is a schematic diagram of a wafer stack structure according to yet another embodiment.
Fig. 8 is a flow chart of a chip stacking method in an exemplary embodiment of the disclosure.
Fig. 9 is a schematic diagram of the chip stacking method shown in fig. 8.
Fig. 10 is a schematic diagram of a chip stack structure in an exemplary embodiment of the present disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, structures, steps, and so forth. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
Further, the drawings are merely schematic illustrations of the present disclosure, in which the same reference numerals denote the same or similar parts, and thus, a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different network and/or processor structures and/or microcontroller structures.
The following detailed description of exemplary embodiments of the disclosure refers to the accompanying drawings.
Fig. 2 schematically illustrates a flow chart of a wafer stacking method in an exemplary embodiment of the present disclosure. Referring to fig. 2, the wafer stacking method may include:
step S102, providing a first wafer, wherein the upper surface of the first wafer comprises a first bonding pad and a second bonding pad, the first bonding pad is connected with a first signal, and the second bonding pad is connected with a second signal;
step S104, sequentially manufacturing a first lower redistribution layer and a first upper redistribution layer on the first wafer, where the first lower redistribution layer includes a first wire connected to the first pad and a second wire connected to the second pad, the first upper redistribution layer includes a third wire connected to the first wire and a fourth wire connected to the second wire, the third wire includes a first lead pad relatively close to the second pad in a horizontal direction, and the fourth wire includes a second lead pad relatively close to the first pad in the horizontal direction;
step S106, bonding a second wafer to the first upper redistribution layer, wherein the upper surface of the second wafer comprises a third bonding pad which is set to be connected with the first signal and corresponds to the second bonding pad in position, and a fourth bonding pad which is set to be connected with the second signal and corresponds to the first bonding pad in position;
step S108, respectively fabricating a first through silicon via for electrically connecting the third bonding pad and a second through silicon via for electrically connecting the fourth bonding pad on the second wafer corresponding to the first and second lead pads, where a bottom of the first through silicon via contacts the first lead pad and a bottom of the second through silicon via contacts the second lead pad.
Fig. 3A to 3D are wafer stack structures manufactured by the wafer stacking method shown in fig. 2.
FIG. 3A illustrates the first wafer 10 provided in step S102, including first pads P1-S1 configured to couple to the first signal S1 and second pads P2-S2 configured to couple to the second signal S2.
Fig. 3B is a schematic diagram of sequentially manufacturing the first lower redistribution layer 11 and the first upper redistribution layer 12 on the first wafer 10 in step S104. The first lower rewiring layer 11 includes first wirings C1 to S1 connecting the first pads P1 to S1 and second wirings C2 to S2 connecting the second pads P2 to S2, the first upper rewiring layer 12 includes third wirings C3 to S1 connected to the first wirings C1 to S1 and fourth wirings C4 to S2 connected to the second wirings C2 to S2, the third wirings C3 to S1 include first lead pads PV1 relatively close to the second pads P2 to S2 in the horizontal direction, and the fourth wirings C4 to S2 include second lead pads PV2 relatively close to the first pads P1 to S1 in the horizontal direction.
Although fig. 3A-3D illustrate embodiments in which the first wafer 10 does not include TSVs, it is understood that the first wafer 10 may include TSVs electrically connected to the first pads and TSVs electrically connected to the second pads in other embodiments.
Fig. 3C is a schematic diagram illustrating the step S106 of bonding the second wafer 20 to the first upper redistribution layer 12. The second wafer 20 includes third pads P3-S1 configured to connect the first signal S1 and fourth pads P4-S2 configured to connect the second signal, the third pads P3-S1 are located to correspond to the second pads P2-S2, and the fourth pads P4-S2 are located to correspond to the first pads P2-S1.
It will be understood by those skilled in the art that the bonding process may include first performing Chemical Mechanical Polishing (CMP) on the upper surface of the first upper redistribution layer, then activating the surface of the first upper redistribution layer using plasma, and finally bonding a second wafer on the activated surface, which will not be described in detail herein.
In the embodiment shown in fig. 3C, a structure for isolating the third wirings C3-S1 and the fourth wirings C4-S2 is required between the second wafer 20 and the first upper rewiring layer 12. For example, the C3-S1, C4-S2 may be isolated from the second wafer 20 by growing an oxide or other insulating layer on the upper surface of the first upper redistribution layer 12. Alternatively, in some embodiments, the positions of C3-S1, C4-S2 may be controlled at the time of fabrication to be below the upper surface of the first upper redistribution layer. In this manner, for example, after the third wiring and the fourth wiring are formed by using the damascene process, the dielectric material of the first upper rewiring layer is deposited again on the third wiring and the fourth wiring so that the dielectric material covers the third wiring and the fourth wiring and only the PV1 and the PV2 are exposed. The interlayer insulation mode can be various, and the interlayer insulation mode can be set by a person skilled in the art according to the actual situation.
Fig. 3D is a diagram illustrating that, in step S108, a first through silicon via connected to the first lead pad at the bottom is formed at a position of the second wafer corresponding to the first lead pad, and a second through silicon via connected to the second lead pad at the bottom is formed at a position corresponding to the second lead pad. In some embodiments, the process of making the through silicon via may include, for example: through holes are respectively formed in the second wafer at positions corresponding to the first lead pad and the second lead pad, so that the bottoms of the two through holes are respectively exposed out of the first lead pad and the second lead pad, and then a conductive material, such as metal, is filled in the two through holes.
Therefore, the first bonding pad is electrically connected with the first silicon through hole through the first wiring and the third wiring, the second bonding pad is electrically connected with the second silicon through hole through the second wiring and the fourth wiring, position exchange can be carried out on the connection point of the first signal and the second signal on the second wafer without manufacturing a bump, and the problems of material leakage, false soldering, inaccurate alignment and the like easily caused in the chip stacking process in the related technology are avoided.
Further, the wafer stacking method may also electrically connect pads on the second wafer and pads on the first wafer. Fig. 4 is a flowchart of a wafer stacking method according to another embodiment of the disclosure. Referring to fig. 4, the wafer stacking method may further include:
step S110 of simultaneously forming a groove for forming a second lower redistribution layer in the process of forming the first through hole and the second through hole;
step S112, a second lower redistribution layer in the groove is simultaneously formed in the process of filling the conductive material, so that the first through silicon via is electrically connected to the third pad and the second through silicon via is electrically connected to the fourth pad.
Specifically, the second lower heavy wiring layer 21 includes fifth wirings C5-S1 electrically connected to third pads C3-S1 and the first through-silicon via PV1, and sixth wirings C6-S2 electrically connected to fourth pads C4-S2 and the second through-silicon via PV 2.
Fig. 5A and 5B are schematic diagrams of the steps shown in fig. 4.
Referring to fig. 5A, the second lower redistribution layer 21 and the third and fourth wirings C3-S1, C4-S2 may be formed on the second wafer 20 by first forming a through-silicon via on the second wafer, then depositing a first dielectric on the second wafer and the through-silicon via, and simultaneously forming a third wiring electrically connecting the through-silicon via and a fourth wiring electrically connecting the second pad in the first dielectric; the second wafer and the second lower redistribution layer may be first deposited with a first medium to form a second lower redistribution layer, then through holes are formed at positions corresponding to the first lead pad and the second lead pad on the second wafer and the second lower redistribution layer, and filled with a conductive material to form a first through silicon via electrically connected to the first lead pad at the bottom and a second through silicon via electrically connected to the second lead pad at the bottom, and finally a third wire electrically connected to the through silicon via and a fourth wire electrically connected to the second pad are formed in the second lower redistribution layer. That is, for the multi-layer wafer stack, the through-silicon via may be formed before the formation of the second lower redistribution layer or after the formation of the second lower redistribution layer, which is not particularly limited by the present disclosure. Wherein the first dielectric is, for example, an oxide.
Referring to fig. 5B, in preparation for the next wafer stacking, a second upper redistribution layer 22 may be further provided, and the lead pads for connecting the first signal and the second signal are subjected to position exchange through seventh wirings C7-S1 and eighth wirings C8-S2 therein, so as to provide conditions for signal connection of pads with positions exchanged at different layers.
Fig. 6A and 6B are top views of a second lower and a second upper redistribution layer, respectively, in the embodiment shown in fig. 5A and 5B. The seventh routing wires C7-S1 include third lead pads PV3 relatively close to the fourth pads C4-S2 in the horizontal direction, and the eighth routing wires C8-S2 include fourth lead pads PV4 relatively close to the third pads C3-S1 in the horizontal direction.
In this manner, when wafer layers are stacked again with reference to steps S104 to S112, a structure as shown in fig. 7 can be formed, i.e., a third lower redistribution layer is fabricated after a third wafer (the upper surface including fifth pads P5-S1 configured to connect to the first signal S1 and sixth pads P6-S2 configured to connect to the second signal S2) is bonded to the second upper redistribution layer 22, resulting in a wafer stack structure capable of connecting signal connection points (pads) with interchangeable positions in different wafer layers in series. The structure has more flexible electrical connection, and can control the bonding pads at the corresponding positions of the odd-numbered layer wafer and the even-numbered layer wafer to work simultaneously and also control the half layer circuit in the stacking structure to work by exchanging the positions of the bonding pads between layers.
In other embodiments, the wafer stack structure may be fabricated by:
1. manufacturing two layers of rewiring layers on a first wafer to lead out a signal of a first bonding pad to a first lead pad and a signal of a second bonding pad to a second lead pad, wherein the first lead pad and the second lead pad are respectively close to the second bonding pad and the first bonding pad;
2. bonding a second wafer to the first upper redistribution layer;
3. depositing a first medium on the second wafer;
4. etching a first through hole and a second through hole at positions of the second wafer and the first medium corresponding to the first lead pad and the second lead pad;
5. etching a lead slot for connecting the first through hole and the third bonding pad and a lead slot for connecting the second through hole and the fourth bonding pad in the second lower redistribution layer;
6. filling a conductive material in the through hole and the lead groove to form a first through silicon via, a second through silicon via, a fifth wiring electrically connected to the first through silicon via and the third pad, and a sixth wiring electrically connected to the second through silicon via and the fourth pad;
7. performing CMP (chemical mechanical polishing) on the second lower heavy wiring layer;
8. depositing a second medium on the second lower heavy wiring layer;
9. and etching the lead groove on the second medium and filling the conductive material to form a seventh wiring and a third lead pad which are electrically connected with the fifth wiring, and an eighth wiring and a fourth lead pad which are electrically connected with the sixth wiring.
10. CMP is performed on the second upper redistribution layer.
In the above process, the first dielectric and the second dielectric are both oxide, for example, and the materials of the two may be the same or different.
According to the embodiment of the disclosure, the wafer is bonded first, then the TSV is manufactured, the leading-out positions of signals are exchanged through the two layers of redistribution layers (RDLs), the wafer laminated structure with the pads connected with the same signals in a staggered mode can be achieved without the aid of the bumps, mechanical alignment and electrical connection of the TSV to the signals on the lower layer are achieved at one time, the problem of reduction of yield caused by the related technology can be effectively solved due to the fact that the bumps are not required to be manufactured, and manufacturing cost is reduced.
Fig. 8 is a flowchart of a chip stacking method according to an embodiment of the disclosure.
Referring to fig. 8, the chip stacking method may include:
step S81, providing a wafer stacking structure according to the above embodiment;
step S82, performing dicing and cutting on the wafer stack structure to form a preset number of chips with stack structures.
The wafer stacking structure according to the present disclosure is manufactured according to the wafer stacking method described in the above embodiments.
Fig. 9 is a schematic diagram of a chip manufactured using the chip stacking method shown in fig. 8, i.e., dicing the wafer stack structure to form unpackaged bare chips.
The chip manufactured by the method shown in fig. 9 does not have a bump structure, and the semiconductor layers are electrically connected through the redistribution layer and the TSV with the bottom directly connected with the redistribution layer, so that the reliability is high, and the problem that the chip in the related art is occasionally unstable in electrical connection can be avoided.
Fig. 10 is a schematic diagram of a chip stack structure provided by an embodiment of the disclosure.
Referring to fig. 10, the chip stack structure 100 may include:
a first chip 10 having an upper surface including first pads P1-S1 connected to a first signal S1 and second pads P2-S2 connected to a second signal S2;
a first lower rewiring layer 11 on the first chip 10, including first wirings C1 to S1 electrically connected to the first pads P1 to S1 and second wirings C2 to S2 electrically connected to the second pads P2 to S2;
a first upper rewiring layer 12 on the first lower rewiring layer 11, including third wirings C3-S1 electrically connected to the first wirings C1-S1 and fourth wirings C4-S2 electrically connected to the second wirings C2-S2, the third wirings C3-S1 including first lead pads PV1 relatively close to the second pads P2-S2 in the horizontal direction, and the fourth wirings C4-S2 including second lead pads PV2 relatively close to the first pads P1-S1 in the horizontal direction;
a second chip 20 bottom-attached to the first upper redistribution layer 12, and provided with third pads P3-S1 positioned corresponding to the second pads P2-S2 and configured to connect to the first signal S1, fourth pads P4-S2 positioned corresponding to the first pads P1-S1 and configured to connect to the second signal S2, a first through-silicon via TSV1 electrically connected at a bottom to the first lead pad PV1, and a second through-silicon via TSV2 electrically connected at a bottom to the second lead pad PV 2;
a second lower rewiring layer 21 on the second chip 20, including fifth wirings C5-S1 electrically connected to the first through-silicon vias TSV1 and the third pads P3-S1, and sixth wirings C6-S2 electrically connected to the second through-silicon vias TSV2 and the fourth pads P4-S2;
a second upper heavy wiring layer 22 located above the second lower heavy wiring layer 21 and including seventh wirings C7-S1 electrically connected to fifth wirings C5-S1 and eighth wirings C8-S2 electrically connected to sixth wirings C6-S2, the seventh wirings C7-S1 including third lead pads PV3 relatively close to fourth pads P4-S2 in the horizontal direction, the eighth wirings C8-S2 including fourth lead pads PV4 relatively close to third pads P3-S1 in the horizontal direction;
a third chip 30 having a bottom surface attached to the second upper redistribution layer 22, and provided with fifth pads P5-S1 corresponding to the first pads P1-S1 and configured to be connected to the first signal S1, sixth pads P4-S2 corresponding to the second pads P2-S2 and configured to be connected to the second signal S2, a third TSV3 having a bottom electrically connected to the third lead pad PV3, and a fourth TSV4 having a bottom electrically connected to the fourth lead pad PV 4;
a third lower rewiring layer 31 on the third chip 30, including ninth wirings C9-S1 electrically connected to the third through-silicon via TSV3 and the fifth pads P5-S1, tenth wirings C8-S2 electrically connected to the fourth through-silicon via TSV4 and the sixth pads P4-S2;
the third upper heavy wiring layer 32, which is located above the third lower heavy wiring layer 31, includes eleventh wirings C11-S1 electrically connected to the ninth wirings C9-S1 and twelfth wirings C12-S2 electrically connected to the tenth wirings C8-S2, the eleventh wirings C11-S1 include fifth lead pads PV5 relatively close to the sixth pads P4-S2 in the horizontal direction, and the twelfth wirings C12-S2 include sixth lead pads PV6 relatively close to the fifth pads P5-S1 in the horizontal direction.
The chip stacking structure provided by the present disclosure is manufactured according to the wafer stacking method described in the above embodiments.
In the chip stack structure shown in fig. 10, the signal connection positions of the odd-numbered layers and the even-numbered layers are reversed, and more flexible control of the stacked chips can be realized.
Furthermore, the above-described figures are merely schematic illustrations of processes involved in methods according to exemplary embodiments of the invention, and are not intended to be limiting. It will be readily understood that the processes shown in the above figures are not intended to indicate or limit the chronological order of the processes. In addition, it is also readily understood that these processes may be performed synchronously or asynchronously, e.g., in multiple modules.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (10)
1. A wafer stacking method, comprising:
providing a first wafer, an upper surface of the first wafer comprising first pads configured to be connected to a first signal and second pads configured to be connected to a second signal;
sequentially manufacturing a first lower redistribution layer and a first upper redistribution layer on the first wafer, wherein the first lower redistribution layer comprises a first wire connected with the first pad and a second wire connected with the second pad, the first upper redistribution layer comprises a third wire connected with the first wire and a fourth wire connected with the second wire, the third wire comprises a first lead pad relatively close to the second pad in the horizontal direction, and the fourth wire comprises a second lead pad relatively close to the first pad in the horizontal direction;
bonding a second wafer to the first upper redistribution layer, wherein the upper surface of the second wafer comprises a third bonding pad arranged to be connected with the first signal and corresponding to the second bonding pad in position, and a fourth bonding pad arranged to be connected with the second signal and corresponding to the first bonding pad in position;
and manufacturing a first silicon through hole for electrically connecting the third bonding pad and a second silicon through hole for electrically connecting the fourth bonding pad on the second wafer at positions corresponding to the first lead pad and the second lead pad respectively, wherein the bottom of the first silicon through hole is contacted with the first lead pad, and the bottom of the second silicon through hole is contacted with the second lead pad.
2. The wafer stacking method of claim 1, wherein the fabricating a first through silicon via for electrically connecting the third pad and a second through silicon via for electrically connecting the fourth pad comprises:
manufacturing a first through hole and a second through hole in the second wafer at positions corresponding to the first lead pad and the second lead pad, wherein the first lead pad is exposed at the bottom of the first through hole, and the second lead pad is exposed at the bottom of the second through hole;
and filling a conductive material in the first through hole and the second through hole to form the first through silicon via and the second through silicon via.
3. The wafer stacking method of claim 2, further comprising:
in the process of manufacturing the first through hole and the second through hole, simultaneously manufacturing a groove for forming a second lower heavy wiring layer;
and in the process of filling the conductive material, simultaneously manufacturing a second lower heavy wiring layer in the groove, so that the first through silicon via is electrically connected with the third bonding pad and the second through silicon via is electrically connected with the fourth bonding pad.
4. The wafer stacking method of claim 1, further comprising:
and manufacturing a second lower heavy wiring layer on the second wafer, wherein the second lower heavy wiring layer comprises a fifth wiring electrically connected to the third bonding pad and the first through silicon via and a sixth wiring electrically connected to the fourth bonding pad and the second through silicon via.
5. The wafer stacking method of claim 4, further comprising:
and forming a second upper redistribution layer on the second lower redistribution layer, wherein the second upper redistribution layer includes a seventh wire electrically connected to the fifth wire and an eighth wire electrically connected to the sixth wire, the seventh wire includes a third lead pad relatively close to the fourth pad in the horizontal direction, and the eighth wire includes a fourth lead pad relatively close to the third pad in the horizontal direction.
6. A wafer stack structure, comprising:
a first wafer having an upper surface including first pads configured to connect to a first signal and second pads configured to connect to a second signal;
a first lower redistribution layer on the first wafer, the first lower redistribution layer including a first wire electrically connected to the first pad and a second wire electrically connected to the second pad;
a first upper redistribution layer on the first lower redistribution layer, including a third wiring electrically connected to the first wiring and a fourth wiring electrically connected to the second wiring, the third wiring including a first lead pad relatively close to the second pad in a horizontal direction, the fourth wiring including a second lead pad relatively close to the first pad in the horizontal direction;
a second wafer, the bottom surface of which is attached to the first upper redistribution layer and is provided with a third pad corresponding to the second pad and configured to be connected with the first signal, a fourth pad corresponding to the first pad and configured to be connected with the second signal, a first through silicon via with a bottom electrically connected to the first lead pad, and a second through silicon via with a bottom electrically connected to the second lead pad;
a second lower rewiring layer located above the second wafer, including a fifth wire electrically connected to the first through silicon via and the third pad, and a sixth wire electrically connected to the second through silicon via and the fourth pad;
a second upper redistribution layer on the second lower redistribution layer, including a seventh wiring electrically connected to the fifth wiring and an eighth wiring electrically connected to the sixth wiring, the seventh wiring including a third lead pad relatively close to the fourth pad in a horizontal direction, the eighth wiring including a fourth lead pad relatively close to the third pad in the horizontal direction.
7. The wafer stack structure of claim 6, further comprising:
a third wafer, a bottom surface of which is attached to the second upper redistribution layer, and which is provided with a fifth pad corresponding to the first pad and configured to connect the first signal, a sixth pad corresponding to the second pad and configured to connect the second signal, a third through silicon via whose bottom is electrically connected to the third lead pad, and a fourth through silicon via whose bottom is electrically connected to the fourth lead pad;
a third lower rewiring layer located above the third wafer, including a ninth wire electrically connected to the third through silicon via and the fifth pad, and a tenth wire electrically connected to the fourth through silicon via and the sixth pad;
a third upper redistribution layer on the third lower redistribution layer, including an eleventh wiring electrically connected to the ninth wiring and a twelfth wiring electrically connected to the tenth wiring, the eleventh wiring including a fifth lead pad relatively close to the sixth pad in a horizontal direction, the twelfth wiring including a sixth lead pad relatively close to the fifth pad in the horizontal direction.
8. A method of chip stacking, comprising:
providing a wafer stack structure according to claim 6 or 7;
and scribing and dividing the wafer stacking structure to form a preset number of chips.
9. A chip stacking structure, comprising:
a first chip having an upper surface including a first pad configured to connect a first signal and a second pad configured to connect a second signal;
a first lower rewiring layer located above the first chip and including a first wire electrically connected to the first pad and a second wire electrically connected to the second pad;
a first upper redistribution layer on the first lower redistribution layer, including a third wiring electrically connected to the first wiring and a fourth wiring electrically connected to the second wiring, the third wiring including a first lead pad relatively close to the second pad in a horizontal direction, the fourth wiring including a second lead pad relatively close to the first pad in the horizontal direction;
a second chip, a bottom surface of which is attached to the first upper redistribution layer, and is provided with a third pad corresponding to the second pad and configured to be connected with the first signal, a fourth pad corresponding to the first pad and configured to be connected with the second signal, a first through-silicon-via having a bottom electrically connected to the first lead pad, and a second through-silicon-via having a bottom electrically connected to the second lead pad;
a second lower rewiring layer located on the second chip and including a fifth wire electrically connected to the first through-silicon via and the third pad, and a sixth wire electrically connected to the second through-silicon via and the fourth pad;
a second upper redistribution layer on the second lower redistribution layer, including a seventh wiring electrically connected to the fifth wiring and an eighth wiring electrically connected to the sixth wiring, the seventh wiring including a third lead pad relatively close to the fourth pad in a horizontal direction, the eighth wiring including a fourth lead pad relatively close to the third pad in the horizontal direction.
10. The chip stack structure of claim 9, further comprising:
a third chip, a bottom surface of which is attached to the second upper redistribution layer, and which is provided with a fifth pad corresponding to the first pad and configured to connect the first signal, a sixth pad corresponding to the second pad and configured to connect the second signal, a third through-silicon via whose bottom is electrically connected to the third lead pad, and a fourth through-silicon via whose bottom is electrically connected to the fourth lead pad;
a third lower rewiring layer located above the third chip and including a ninth wire electrically connected to the third through silicon via and the fifth pad, and a tenth wire electrically connected to the fourth through silicon via and the sixth pad;
a third upper redistribution layer on the third lower redistribution layer, including an eleventh wiring electrically connected to the ninth wiring and a twelfth wiring electrically connected to the tenth wiring, the eleventh wiring including a fifth lead pad relatively close to the sixth pad in a horizontal direction, the twelfth wiring including a sixth lead pad relatively close to the fifth pad in the horizontal direction.
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| CN111128974B (en) | 2024-08-02 |
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