CN111128698A - Novel diffusion process of TVS chip - Google Patents
Novel diffusion process of TVS chip Download PDFInfo
- Publication number
- CN111128698A CN111128698A CN201911364166.0A CN201911364166A CN111128698A CN 111128698 A CN111128698 A CN 111128698A CN 201911364166 A CN201911364166 A CN 201911364166A CN 111128698 A CN111128698 A CN 111128698A
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- Prior art keywords
- diffusion
- junction
- oxide film
- chip
- diffused
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- 238000009792 diffusion process Methods 0.000 title claims abstract description 37
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 239000010703 silicon Substances 0.000 claims abstract description 12
- 238000001259 photo etching Methods 0.000 claims abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 239000007788 liquid Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 230000001052 transient effect Effects 0.000 abstract description 4
- 230000001629 suppression Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 2
- 230000007547 defect Effects 0.000 description 2
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/228—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a liquid phase, e.g. alloy diffusion processes
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a novel diffusion process of a TVS chip, and belongs to the technical field of chip diffusion. The method comprises the following steps: after being cleaned, the silicon chip is oxidized, so that an oxide film is added on the surface of the silicon chip; removing the area oxide film needing to be diffused by adopting a photoetching mode; attaching a diffusion source to the region where the oxide film is removed, and diffusing to form a first PN junction; removing the oxide film on the surface of the previous non-diffused area of the diffused silicon wafer; attaching a diffusion source on the surface of the previous non-diffusion area, and performing secondary diffusion to form a second PN junction; according to the invention, through secondary diffusion, an inner PN junction and an outer PN junction are formed, the outer PN junction forms a protection structure, the inner PN junction is subjected to circuit transient suppression, and the reliability of the chip is improved.
Description
Technical Field
The invention belongs to the technical field of chip diffusion, and particularly relates to a novel diffusion process of a TVS chip.
Background
The current TVS chip of the semiconductor power device adopts the traditional phosphorus boron diffusion process, when the resistivity is too low, the leakage current is too large, and when the resistivity is increased, the VC capability is not enough.
Disclosure of Invention
Aiming at the problems of defects and defects in the prior art, the invention provides a novel diffusion process of a TVS chip, wherein an inner PN junction and an outer PN junction are formed through secondary diffusion, the outer PN junction forms a protection structure, the inner PN junction is subjected to circuit transient suppression, and the reliability of the chip is improved.
The technical scheme adopted by the invention for solving the technical problems is as follows:
a novel diffusion process of a TVS chip comprises the following steps:
a. after being cleaned, the silicon chip is oxidized, so that an oxide film is added on the surface of the silicon chip;
b. removing the area oxide film needing to be diffused by adopting a photoetching mode;
c. attaching a diffusion source to the region where the oxide film is removed, and diffusing to form a first PN junction;
d. removing the oxide film on the surface of the previous non-diffused area of the diffused silicon wafer;
e. and attaching a diffusion source on the surface of the previous non-diffusion area, and performing secondary diffusion to form a second PN junction.
Further, the oxide film is a silicon dioxide film.
Further, the diffusion source is a boron liquid source.
The invention has the following beneficial effects: through secondary diffusion, an inner PN junction and an outer PN junction are formed, the outer PN junction forms a protection structure, the inner PN junction is firm, the circuit transient state is restrained, and the reliability of the chip is improved. The invention adopts a new diffusion mode, which can increase resistance distribution, reduce leakage current distribution, increase passivation protection and improve VC capability.
Drawings
FIG. 1 is a schematic view of the process of the present invention.
Detailed Description
The following examples are provided to illustrate specific embodiments of the present invention.
The first embodiment is as follows:
a novel diffusion process of a TVS chip comprises the following steps:
a. after being cleaned, the silicon chip is oxidized, so that an oxide film is added on the surface of the silicon chip;
b. removing the area oxide film needing to be diffused by adopting a photoetching mode;
c. attaching a diffusion source to the region where the oxide film is removed, and diffusing to form a first PN junction;
d. removing the oxide film on the surface of the previous non-diffused area of the diffused silicon wafer;
e. and attaching a diffusion source on the surface of the previous non-diffusion area, and performing secondary diffusion to form a second PN junction.
Further, the oxide film is a silicon dioxide film.
Further, the diffusion source is a boron liquid source.
According to the invention, through secondary diffusion, an inner PN junction and an outer PN junction are formed, the outer PN junction forms a protection structure, the inner PN junction is subjected to circuit transient suppression, and the reliability of the chip is improved.
The foregoing shows and describes the general principles, essential features, and advantages of the invention. The present invention is not limited to the above-described embodiments, which are described in the specification and illustrated only for illustrating the principle of the present invention, but various changes and modifications may be made within the scope of the present invention as claimed without departing from the spirit and scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (3)
1. A novel diffusion process of a TVS chip is characterized by comprising the following steps:
a. after being cleaned, the silicon chip is oxidized, so that an oxide film is added on the surface of the silicon chip;
b. removing the area oxide film needing to be diffused by adopting a photoetching mode;
c. attaching a diffusion source to the region where the oxide film is removed, and diffusing to form a first PN junction;
d. removing the oxide film on the surface of the previous non-diffused area of the diffused silicon wafer;
e. and attaching a diffusion source on the surface of the previous non-diffusion area, and performing secondary diffusion to form a second PN junction.
2. The novel diffusion process of TVS chip as claimed in claim 1, wherein: the oxide film is a silicon dioxide film.
3. The novel diffusion process of TVS chip as claimed in claim 1, wherein: the diffusion source is a boron liquid source.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911364166.0A CN111128698A (en) | 2019-12-26 | 2019-12-26 | Novel diffusion process of TVS chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911364166.0A CN111128698A (en) | 2019-12-26 | 2019-12-26 | Novel diffusion process of TVS chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111128698A true CN111128698A (en) | 2020-05-08 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911364166.0A Withdrawn CN111128698A (en) | 2019-12-26 | 2019-12-26 | Novel diffusion process of TVS chip |
Country Status (1)
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| CN (1) | CN111128698A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023045393A1 (en) * | 2021-09-27 | 2023-03-30 | 安徽芯旭半导体有限公司 | Tvs chip and production method therefor |
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| US5882986A (en) * | 1998-03-30 | 1999-03-16 | General Semiconductor, Inc. | Semiconductor chips having a mesa structure provided by sawing |
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| CN104810281A (en) * | 2015-03-11 | 2015-07-29 | 苏州启澜功率电子有限公司 | Transient voltage suppression diode array chip according to mesa trench isolation method and production technology thereof |
| CN105489657A (en) * | 2016-02-24 | 2016-04-13 | 江苏捷捷微电子股份有限公司 | One-way low-voltage TVS device and manufacturing method thereof |
| US20170213815A1 (en) * | 2006-11-30 | 2017-07-27 | Alpha And Omega Semiconductor Incorporated | Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (tvs) |
| CN109192727A (en) * | 2018-09-04 | 2019-01-11 | 深圳市诚朗科技有限公司 | Transient voltage suppressor and preparation method thereof |
| CN110010675A (en) * | 2019-04-09 | 2019-07-12 | 捷捷半导体有限公司 | A punch-through type medium and low voltage planar TVS chip and preparation method thereof |
-
2019
- 2019-12-26 CN CN201911364166.0A patent/CN111128698A/en not_active Withdrawn
Patent Citations (14)
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| US5882986A (en) * | 1998-03-30 | 1999-03-16 | General Semiconductor, Inc. | Semiconductor chips having a mesa structure provided by sawing |
| US20040070029A1 (en) * | 2001-05-04 | 2004-04-15 | Robb Francine Y. | Low voltage transient voltage suppressor and method of making |
| JP2006032923A (en) * | 2004-06-14 | 2006-02-02 | Tyco Electronics Corp | Diode with improved energy impulse rating |
| US20170213815A1 (en) * | 2006-11-30 | 2017-07-27 | Alpha And Omega Semiconductor Incorporated | Optimized configurations to integrate steering diodes in low capacitance transient voltage suppressor (tvs) |
| CN101621002A (en) * | 2009-08-05 | 2010-01-06 | 百圳君耀电子（深圳）有限公司 | Manufacturing method of low-voltage transient voltage suppression diode chip |
| CN101916786A (en) * | 2010-06-22 | 2010-12-15 | 南通明芯微电子有限公司 | High-power planar junction bidirectional TVS diode chip and production method thereof |
| CN103972305A (en) * | 2014-04-18 | 2014-08-06 | 苏州固锝电子股份有限公司 | Method for manufacturing low-voltage transient voltage suppression diode chip |
| CN103956324B (en) * | 2014-04-30 | 2017-01-18 | 天津中环半导体股份有限公司 | Production technology for transient voltage suppressor chip with channeling effect |
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| CN105489657A (en) * | 2016-02-24 | 2016-04-13 | 江苏捷捷微电子股份有限公司 | One-way low-voltage TVS device and manufacturing method thereof |
| CN109192727A (en) * | 2018-09-04 | 2019-01-11 | 深圳市诚朗科技有限公司 | Transient voltage suppressor and preparation method thereof |
| CN110010675A (en) * | 2019-04-09 | 2019-07-12 | 捷捷半导体有限公司 | A punch-through type medium and low voltage planar TVS chip and preparation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023045393A1 (en) * | 2021-09-27 | 2023-03-30 | 安徽芯旭半导体有限公司 | Tvs chip and production method therefor |
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Application publication date: 20200508 |
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