CN111106801A - Monolithic reconfigurable gallium arsenide low noise amplifier and preparation method thereof - Google Patents
Monolithic reconfigurable gallium arsenide low noise amplifier and preparation method thereof Download PDFInfo
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Abstract
The invention belongs to the technical field of low-noise amplifiers, and relates to a monolithic reconfigurable gallium arsenide low-noise amplifier and a preparation method thereof. The circuit comprises: an off-chip input matching circuit and a gallium arsenide monolithic amplifying circuit; the input end of the off-chip input matching circuit is used as the input end of the single-chip reconfigurable gallium arsenide low noise amplifier, the matching end of the off-chip input matching circuit is connected with the input end of the gallium arsenide single-chip amplifying circuit, and the output end of the gallium arsenide single-chip amplifying circuit is used as the output end of the single-chip reconfigurable gallium arsenide low noise amplifier; and the off-chip input matching circuit and the gallium arsenide monolithic amplifying circuit are subjected to impedance matching to obtain a monolithic reconfigurable gallium arsenide low-noise amplifier with a preset noise coefficient. The invention moves the input matching network of the gallium arsenide monolithic amplifying circuit from the chip to the outside of the chip, thereby realizing the improvement of the Q value of the input matching network according to the working requirement and reducing the noise coefficient of the low noise amplifier.
Description
Technical Field
The invention belongs to the technical field of low noise amplifiers, and particularly relates to a monolithic reconfigurable gallium arsenide low noise amplifier and a preparation method thereof.
Background
At present, there are two ways to realize the manufacturing process of gallium arsenide (GaAs) low noise amplifier, namely a GaAs low noise amplifier single chip manufactured by Microwave Monolithic Integrated Circuit (MMIC) process; the other gallium arsenide low noise amplifier is designed by adopting a microwave thin film hybrid integrated circuit process. However, the gallium arsenide low noise amplifier manufactured by the microwave monolithic integrated circuit process has a high monolithic noise coefficient, and the gallium arsenide low noise amplifier designed by the microwave thin film hybrid integrated circuit process has a large circuit size.
Disclosure of Invention
In view of this, the embodiment of the present invention provides a monolithic reconfigurable gallium arsenide low noise amplifier and a manufacturing method thereof, so as to solve the problems of a gallium arsenide low noise amplifier in the prior art that the noise coefficient is high and the circuit size is large.
A first aspect of an embodiment of the present invention provides a monolithic reconfigurable gallium arsenide low noise amplifier, including: an off-chip input matching circuit and a gallium arsenide monolithic amplifying circuit; the input end of the off-chip input matching circuit is used as the input end of the single-chip reconfigurable gallium arsenide low noise amplifier, the matching end of the off-chip input matching circuit is connected with the input end of the gallium arsenide single-chip amplifying circuit, and the output end of the gallium arsenide single-chip amplifying circuit is used as the output end of the single-chip reconfigurable gallium arsenide low noise amplifier;
and the off-chip input matching circuit and the gallium arsenide monolithic amplifying circuit are subjected to impedance matching to obtain a monolithic reconfigurable gallium arsenide low-noise amplifier with a preset noise coefficient.
Further, the off-chip input matching circuit includes: the inductor comprises a first inductor, a second inductor and a dielectric substrate;
the first end of the second inductor is used as the input end of the off-chip input matching circuit, the first end of the second inductor is also connected with the first end of the first inductor, and the second end of the second inductor is used as the matching end of the off-chip input matching circuit; the second end of the first inductor is connected with the grounding end of the off-chip input matching circuit;
the second inductor and the first inductor are both arranged on the dielectric substrate;
the medium substrate comprises at least two circular through holes with preset radiuses, and the circular through holes are grounding ends of the off-chip input matching circuit.
Further, the second inductor comprises at least two gold wires;
the first end of a first gold wire of the at least two gold wires is used as the first end of the second inductor, the second end of the first gold wire is connected with the first end of a second gold wire of the at least two gold wires, and the second end of the second gold wire is used as the second end of the second inductor.
Furthermore, the at least two gold wires are all phi 25 μm bonding gold wires.
Further, the first inductor comprises a planar spiral inductor and a third gold wire;
and the first end of the third gold wire is used as the first end of the second inductor, the second end of the third gold wire is connected with the first end of the planar spiral inductor, and the second end of the planar spiral inductor is connected with the grounding end of the off-chip input matching circuit.
Further, the first inductor is a bonding gold wire with the diameter of phi 25 mu m;
and the first end of the phi 25 μm gold bonding wire is used as the first end of the first inductor, and the second end of the phi 25 μm gold bonding wire is connected with the grounding end of the off-chip input matching circuit.
Further, the medium substrate is an alumina ceramic substrate with the thickness ranging from 0.343mm to 0.419 mm.
The second aspect of the embodiments of the present invention provides a method for preparing a monolithic reconfigurable gallium arsenide low noise amplifier, including:
preparing an off-chip input matching circuit, wherein the off-chip input matching circuit comprises an input end and a matching end;
preparing a gallium arsenide monolithic amplifying circuit, wherein the gallium arsenide monolithic amplifying circuit is not provided with an input matching network and comprises an input end and an output end;
and performing impedance matching on the off-chip input matching circuit and the gallium arsenide monolithic amplifying circuit to obtain a preset noise coefficient, wherein the matching end of the off-chip input matching circuit is bonded with the input end of the gallium arsenide monolithic amplifying circuit.
Further, preparing an off-chip input matching circuit includes:
preparing at least two circular through holes with preset radiuses on one side of a medium substrate;
sputtering a metal layer on the front surface of the dielectric substrate with the through hole;
forming a patterned mask layer on the front surface of the dielectric substrate sputtered with the metal layer by utilizing a photoetching process;
electroplating the front surface of the medium substrate on which the graphical mask layer is formed to obtain a connection point of the grounded planar spiral inductor and the array, and removing the mask layer on the front surface of the medium substrate and the metal layer below the mask layer;
and bonding a second inductor on the connection point of the array through at least two gold wires, and connecting the second inductor with the planar spiral inductor through a third gold wire.
Further, sputtering a metal layer on the front surface of the dielectric substrate provided with the through hole, wherein the metal layer comprises:
sputtering a titanium-tungsten layer on the front surface of the medium substrate with the through hole;
and sputtering a gold layer on the titanium-tungsten layer of the medium substrate.
Compared with the prior art, the monolithic reconfigurable gallium arsenide low-noise amplifier and the preparation method thereof in the embodiment of the invention have the beneficial effects that: the circuit mainly comprises an off-chip input matching circuit and a gallium arsenide monolithic amplifying circuit, and an input matching network of the gallium arsenide monolithic amplifying circuit is moved from the chip to the outside of the chip, so that the Q value of the input matching network is improved, and the noise of the low-noise amplifier is reduced; the input end of the off-chip input matching circuit is used as the input end of the single-chip reconfigurable gallium arsenide low-noise amplifier, the matching end of the off-chip input matching circuit is connected with the input end of the gallium arsenide single-chip amplifying circuit, the output end of the gallium arsenide single-chip amplifying circuit is used as the output end of the single-chip reconfigurable gallium arsenide low-noise amplifier, the off-chip input matching circuit and the gallium arsenide single-chip amplifying circuit are subjected to impedance matching to obtain the single-chip reconfigurable gallium arsenide low-noise amplifier with the preset noise coefficient, namely the noise coefficient between the off-chip input matching circuit and the gallium arsenide single-chip amplifying circuit can be adjusted or constructed according to working requirements, the noise.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed for the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a monolithic reconfigurable gallium arsenide low noise amplifier provided in an embodiment of the present invention;
FIG. 2 is a schematic diagram of an off-chip input matching circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a dielectric substrate including a planar spiral inductor and an array of connection points according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a gallium arsenide monolithic amplifier circuit according to an embodiment of the present invention;
fig. 5 is a schematic flow chart of a method for manufacturing a monolithic reconfigurable gallium arsenide low noise amplifier according to an embodiment of the present invention;
fig. 6 is a detailed flowchart of step S501 in fig. 5.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1, an embodiment of the present invention provides a monolithic reconfigurable gallium arsenide low noise amplifier, which mainly includes: an off-chip input matching circuit 100 and a gallium arsenide monolithic amplifying circuit 200; the input end of the off-chip input matching circuit 100 is used as the input end IN of the single-chip reconfigurable gallium arsenide low noise amplifier, the matching end of the off-chip input matching circuit 100 is connected with the input end of the gallium arsenide single-chip amplifying circuit 200, and the output end of the gallium arsenide single-chip amplifying circuit 200 is used as the output end OUT of the single-chip reconfigurable gallium arsenide low noise amplifier. The off-chip input matching circuit 100 and the gallium arsenide monolithic amplifying circuit 200 perform impedance matching to obtain a monolithic reconfigurable gallium arsenide low noise amplifier with a preset noise coefficient. Wherein the gallium arsenide monolithic amplifier circuit 200 is a gallium arsenide monolithic amplifier circuit without an input matching network.
The gallium arsenide low noise amplifier is manufactured by microwave monolithic integrated circuit process or microwave film mixed integrated circuit process, and the gallium arsenide low noise amplifier manufactured by the above two processes has advantages and disadvantages in the aspects of external dimension and noise coefficient.
The input end and the output end of the gallium arsenide low-noise amplifier single chip manufactured by utilizing the microwave single chip integrated circuit process are matched to 50 ohm impedance, when the gallium arsenide low-noise amplifier single chip is used, a user only needs to design a peripheral microwave circuit according to the 50 ohm impedance, the peripheral microwave circuit and the 50 ohm impedance are directly cascaded, the matching of a 50 ohm impedance system is realized, and the high-efficiency transmission of microwave signals is completed, so the quality of the noise coefficient of the whole gallium arsenide low-noise amplifier single chip is completely determined by the noise coefficient level of the gallium arsenide low-noise amplifier single chip, and the noise coefficient index cannot be further optimized by the peripheral.
In practical application, the noise coefficient of the gaas lna is mainly determined by the Q value of the matching network at the input end, and the higher the Q value is, the smaller the loss is, the lower the noise coefficient is. At present, due to the limitation of the development level of semiconductor processing materials and processing technologies, the Q value of the gallium arsenide low noise amplifier manufactured by the microwave monolithic integrated circuit technology is not as high as that of the gallium arsenide low noise amplifier designed by the microwave thin film hybrid integrated circuit technology, which results in that the noise coefficient of the gallium arsenide low noise amplifier monolithic cannot reach the noise coefficient level of the gallium arsenide low noise amplifier designed by the microwave thin film hybrid integrated technology.
However, the overall dimension of the gallium arsenide low noise amplifier manufactured by the microwave monolithic integrated circuit process is far smaller than the circuit dimension of the gallium arsenide low noise amplifier designed by the microwave thin film hybrid integrated process, that is, the gallium arsenide low noise amplifier monolithic manufactured by the microwave monolithic integrated circuit process can realize smaller circuit dimension but larger noise coefficient, and the gallium arsenide low noise amplifier manufactured by the microwave thin film hybrid integrated circuit process can realize lower noise coefficient but larger circuit dimension.
Therefore, the invention moves the input matching network of the GaAs low noise amplifier from the chip to the outside of the chip to improve the Q value of the input matching network. The off-chip input matching circuit 100 is implemented using microwave thin-film hybrid integrated circuit technology, such as in aluminum oxide (AL)2O3) The input matching of the gallium arsenide low noise amplifier is completed by using a bonding gold wire with a high Q value on the ceramic circuit substrate, the Q value of an input matching network of the gallium arsenide low noise amplifier can be obviously improved, the noise coefficient of the gallium arsenide low noise amplifier can be reduced, and the overall dimension of the gallium arsenide monolithic amplifying circuit 200 is reduced. The reconfigurable gallium arsenide low noise amplifier of the embodimentThe amplifier is used with the off-chip input matching circuit 100, and the noise coefficient performance of the low noise amplifier can be reconstructed, so that the noise coefficient of the reconfigurable gallium arsenide low noise amplifier single chip is superior to that of the low noise amplifier single chip adopting the full on-chip matching.
According to the single-chip reconfigurable gallium arsenide low-noise amplifier, the input matching network of the gallium arsenide single-chip amplifying circuit 200 is moved from the chip to the outside of the chip, so that the size of the low-noise amplifier is reduced, and the Q value of the input matching network is improved; the off-chip input matching circuit 100 is cascaded with the gallium arsenide monolithic amplifying circuit 200, and a user adjusts or constructs the noise coefficient between the off-chip input matching circuit 100 and the gallium arsenide monolithic amplifying circuit 200 according to the working requirement, so that the reconstruction of the noise coefficient of the gallium arsenide low-noise amplifier is realized, and the applicability is strong.
All circuit parts of the gallium arsenide monolithic amplification circuit 200 of the present embodiment except the input matching network are integrated and prepared on a monolithic by using a gallium arsenide microwave monolithic integrated circuit process, the specific structure is not limited, referring to fig. 4, the gallium arsenide monolithic amplification circuit 200 includes an input end and an output end, and the output end is matched to a preset impedance. Exemplarily, the GaAs monolithic amplifier circuit 200 uses a microwave monolithic integrated circuit process to process a wafer on a 4-inch GaAs PHEMT process platform, uses a 0.13 μm electron beam lithography technique, and reasonably designs the length of the single finger gate, the width of the single finger gate, and the length of the single cell active region of the amplifier die according to the working frequency, gain, noise factor, and output 1dB compression point power; in order to obtain better noise performance, in the design of the planar structure of the amplifying die, the gate length and the gate-source spacing of the amplifying die are reduced to reduce the influence of parasitic parameters on the noise coefficient as much as possible, so as to reduce the intrinsic noise, and a 'reconfigurable' gallium arsenide monolithic amplifying circuit 200 can be seen in fig. 4, wherein the length of the monolithic is 1.9mm, and the width of the monolithic is 0.9 mm.
In one embodiment, referring to fig. 2, the off-chip input matching circuit 100 includes: a second inductor L2, a first inductor L1 and a dielectric substrate 110; a first end Port1 of the second inductor L2 is used as an input end of the off-chip input matching circuit 100, a first end of the second inductor L2 is further connected with a first end of the first inductor L1, and a second end Port2 of the second inductor L2 is used as a matching end of the off-chip input matching circuit 100; a second terminal of the first inductor L1 is connected to the ground terminal of the off-chip input matching circuit 100.
Referring to fig. 1, the second inductor L2 and the first inductor L1 are both disposed on the dielectric substrate 110; the dielectric substrate 110 includes at least two circular vias 120 with a predetermined radius R, and the circular vias 120 are grounded terminals of the off-chip input matching circuit 100. In the off-chip input matching circuit 100, the second inductor L2 as the branch 1 and the first inductor L1 as the branch 2 are determined by the circuit form of impedance matching, and a user can set the sizes of the second inductor L2 and the first inductor L1 according to the work requirement.
In one embodiment, the second inductor L2 includes at least two gold wires; the first end of the first gold wire of the at least two gold wires is used as the first end of the second inductor L2, the second end of the first gold wire is connected with the first end of the second gold wire of the at least two gold wires, and the second end of the second gold wire is used as the second end of the second inductor L2.
Optionally, at least two gold wires are phi 25 μm bonding gold wires. Referring to fig. 1, the second inductor L2 may include 4 gold wires, i.e., gold wire L1Gold wire L2Gold wire L3And gold wire L4Gold wire L4As the first terminal of the second inductor L2, gold wire L1As the second terminal of the second inductor L2. The length of the bonding gold wire with the high Q value of phi 25 mu m determines the inductance of the bonding gold wire as an inductor, so that the setting of parameters such as the torsion degree, the torsion distance, the arc height and the like of the bonding gold wire with the high Q value of phi 25 mu m can be automatically completed by a bonding procedure operator, and the length of the bonding gold wire with the high Q value of phi 25 mu m can be set according to the product requirement.
In one embodiment, the first inductor L1 may include: a planar spiral inductor and a third gold wire; the first terminal of the third gold wire is used as the first terminal of the second inductor L2, the second terminal of the third gold wire is connected to the first terminal of the planar spiral inductor, and the second terminal of the planar spiral inductor is connected to the ground terminal of the off-chip input matching circuit 100.
Optionally, the dielectric substrate 110 is an alumina ceramic substrate having a thickness ranging from 0.343mm to 0.419mm, and the alumina ceramic substrate has a dielectric constant ranging from 9.8 to 10.0.
Illustratively, the planar spiral inductor is fabricated by microwave thin film hybrid integrated circuit (microwave-ic) technology on a 0.381mm alumina ceramic substrate, which is part of the off-chip input matching circuit 100. Referring to fig. 1, the second inductor L2 and the first inductor L1 may be implemented on a 0.381mm alumina ceramic substrate by a microwave thin film hybrid integrated circuit process, wherein the second inductor L2 is implemented by a gold bonding wire with a high Q value, and the first inductor L1 is implemented by combining a planar spiral inductor manufactured by the microwave thin film hybrid integrated process and the gold wire because the inductance of the frequency band is relatively large.
Illustratively, referring to fig. 3, a length L1 of the dielectric substrate 110 is 1.9mm, a width W1 of the dielectric substrate 110 is 1.5mm, a length L2 of a connection point of the array on the dielectric substrate 110 is 0.15mm, a width W2 of the connection point is 0.15mm, a spiral interval L3 of the planar spiral inductor is 0.04mm, a length L5 of a first end of the planar spiral inductor is 0.11mm, a total structural length L6 of the planar spiral inductor is 1.19mm, a spiral length L7 of the planar spiral inductor is 1.08mm, a transverse spiral line W3 of the planar spiral inductor is 0.04mm, a width W5 of the first end of the planar spiral inductor is 0.1mm, a width L4 of a ground terminal of the off-chip matching circuit 100 is 0.5mm, a length W4 of the ground terminal of the planar spiral inductor is 0.83mm, and a radius R of the circular through hole is 0.15 mm.
Further, an off-chip input matching circuit 100 incorporating gold bond wires is shown in fig. 1. For example, the second inductor L2 may be made of gold wire L1Gold wire L2Gold wire L3And gold wire L44 bonding gold wires with the diameter of 25 mu m; the first inductor L1 is composed of gold wire L5And a planar spiral inductor, a gold wire L5Is the third gold wire.
Optionally, the first inductor L1 may also be a gold bonding wire of Φ 25 μm; the first end of the phi 25 μm gold bond wire is used as the first end of the first inductor L1, and the second end of the phi 25 μm gold bond wire is connected to the ground terminal of the off-chip input matching circuit 100.
After the off-chip input matching circuit 100 and the gallium arsenide monolithic amplifying circuit 200 are cascaded, the actual test result meets the design expectation, and a better actual effect is obtained, specifically, see table 1, the noise coefficient is 0.2dB lower than that of a traditional low noise amplifier monolithic adopting the whole-chip matching, and the size of the whole circuit is 2/3 smaller than that of a low noise amplifier totally adopting the microwave thin film hybrid integration process design. The technical indexes of the monolithic reconfigurable gallium arsenide low noise amplifier are as follows in table 1:
table 1: technical indexes reached by the single-chip reconfigurable gallium arsenide low-noise amplifier
| Serial number | Parameter name | Typical value | Unit of |
| 1 | Frequency range | 2.0～4.0 | |
| 2 | Gain of | 25 | dB |
| 3 | Standing wave ratio | 1.5 | — |
| 4 | Outputting 1dB of compressed power | 13 | dBm |
| 5 | Noise figure | 0.55 | dB |
| 6 | Operating current | 50 | mA |
In the above embodiment, the monolithic reconfigurable gallium arsenide low noise amplifier mainly includes the off-chip input matching circuit 100 and the gallium arsenide monolithic amplifying circuit 200, and the input matching network of the gallium arsenide monolithic amplifying circuit 200 is moved from the chip to the outside of the chip, so that the size of the low noise amplifier is reduced, and the Q value of the input matching network is improved; the input end of the off-chip input matching circuit 100 is used as the input end IN of the single-chip reconfigurable gallium arsenide low-noise amplifier, the matching end of the off-chip input matching circuit 100 is connected with the input end of the gallium arsenide single-chip amplifying circuit 200, the output end of the gallium arsenide single-chip amplifying circuit 200 is used as the output end OUT of the single-chip reconfigurable gallium arsenide low-noise amplifier, the off-chip input matching circuit 100 and the gallium arsenide single-chip amplifying circuit 200 are subjected to impedance matching to obtain the single-chip reconfigurable gallium arsenide low-noise amplifier with the preset noise coefficient, namely the noise coefficient between the off-chip input matching circuit 100 and the gallium arsenide single-chip amplifying circuit 200 can be adjusted or constructed according to working requirements, the reconstruction of the.
The embodiment also provides a method for manufacturing the monolithic reconfigurable gallium arsenide low noise amplifier, and referring to fig. 5, a specific implementation flow of the method for manufacturing the monolithic reconfigurable gallium arsenide low noise amplifier provided by the embodiment is mainly as follows:
step S501, an off-chip input matching circuit is prepared, and the off-chip input matching circuit comprises an input end and a matching end. And the input end of the off-chip input matching circuit is used as the input end of the single-chip reconfigurable gallium arsenide low noise amplifier.
Step S502, a gallium arsenide monolithic amplifying circuit is prepared, the gallium arsenide monolithic amplifying circuit is not provided with an input matching network, and the gallium arsenide monolithic amplifying circuit comprises an input end and an output end. The output end of the gallium arsenide monolithic amplifying circuit is used as the output end of the monolithic reconfigurable gallium arsenide low noise amplifier.
Step S503, the off-chip input matching circuit and the gallium arsenide monolithic amplifying circuit are subjected to impedance matching to obtain a preset noise coefficient, and the matching end of the off-chip input matching circuit is bonded with the input end of the gallium arsenide monolithic amplifying circuit.
In one embodiment, referring to fig. 6, the specific implementation flow of preparing the off-chip input matching circuit in step S501 includes:
step S601, preparing at least two circular through holes with preset radiuses on one side of the medium substrate.
Step S602, a metal layer is sputtered on the front surface of the dielectric substrate with the through hole.
Step S603, a patterned mask layer is formed on the front surface of the dielectric substrate on which the metal layer is sputtered by using a photolithography process.
Step S604, electroplating the front surface of the dielectric substrate on which the patterned mask layer is formed to obtain a connection point between the grounded planar spiral inductor and the array, and removing the mask layer on the front surface of the dielectric substrate and the metal layer under the mask layer.
And step S605, bonding a second inductor on the connection point of the array through at least two gold wires, and connecting the second inductor with the planar spiral inductor through a third gold wire.
Optionally, the specific implementation process of sputtering the metal layer on the front surface of the dielectric substrate with the through hole includes:
and sputtering a titanium-tungsten layer on the front surface of the medium substrate with the through hole.
And sputtering a gold layer on the titanium-tungsten layer of the medium substrate.
Illustratively, 0.381mm thick oxidation is usedAn aluminum ceramic substrate, and at least two circular through holes with preset radiuses are prepared on one side of the alumina ceramic substrate with the thickness of 0.381 mm. Sputtering a titanium Tungsten (TiW) layer (with the thickness) on the back of the ceramic substrate with the round through hole by a magnetron sputtering platform
) And then sputtering a gold (Au) layer (thickness) on the titanium-tungsten layer
) And finally, electroplating gold (with the thickness of 3-4 mu m) on the back surface of the ceramic substrate with the gold layer. Sputtering titanium-tungsten layer (thickness) on the front surface of the ceramic substrate with the circular through hole by a magnetron sputtering platform
) Then sputtering a gold layer (thickness)
) And then, forming a patterned mask layer on the front surface of the dielectric substrate with the gold layer sputtered thereon by a one-time photoetching process, electroplating the front surface of the dielectric substrate with the patterned mask layer to obtain a connection point (with the thickness of 4-5 μm) of the grounded planar spiral inductor and the array, removing the mask layer on the front surface of the dielectric substrate and a metal layer below the mask layer, finally manufacturing a circuit pattern of the grounded planar spiral inductor and the connection point of the array by a two-time photoetching process and a three-time photoetching process, finally bonding a second inductor on the connection point of the array through at least two gold wires, and connecting the second inductor with the planar spiral inductor through a third gold wire to obtain an off-chip input matching circuit.
In the embodiment, the off-chip input matching circuit is independently prepared, the input matching network of the gallium arsenide monolithic amplifying circuit is moved from the chip to the outside of the chip, the Q value of the input matching network is improved, a user can adjust or construct the noise coefficient between the off-chip input matching circuit and the gallium arsenide monolithic amplifying circuit according to the working requirement, the reconstruction of the noise coefficient of the gallium arsenide low-noise amplifier is realized, and the applicability is strong.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. A monolithic reconfigurable gallium arsenide low noise amplifier comprising: an off-chip input matching circuit and a gallium arsenide monolithic amplifying circuit; the input end of the off-chip input matching circuit is used as the input end of the single-chip reconfigurable gallium arsenide low noise amplifier, the matching end of the off-chip input matching circuit is connected with the input end of the gallium arsenide single-chip amplifying circuit, and the output end of the gallium arsenide single-chip amplifying circuit is used as the output end of the single-chip reconfigurable gallium arsenide low noise amplifier;
and the off-chip input matching circuit and the gallium arsenide monolithic amplifying circuit are subjected to impedance matching to obtain a monolithic reconfigurable gallium arsenide low-noise amplifier with a preset noise coefficient.
2. The monolithic reconfigurable gallium arsenide low noise amplifier of claim 1 wherein the off-chip input matching circuit comprises: the inductor comprises a first inductor, a second inductor and a dielectric substrate;
the first end of the second inductor is used as the input end of the off-chip input matching circuit, the first end of the second inductor is also connected with the first end of the first inductor, and the second end of the second inductor is used as the matching end of the off-chip input matching circuit; the second end of the first inductor is connected with the grounding end of the off-chip input matching circuit;
the second inductor and the first inductor are both arranged on the dielectric substrate;
the medium substrate comprises at least two circular through holes with preset radiuses, and the circular through holes are grounding ends of the off-chip input matching circuit.
3. The monolithic reconfigurable gallium arsenide low noise amplifier of claim 2 wherein the second inductor comprises at least two gold wires;
the first end of a first gold wire of the at least two gold wires is used as the first end of the second inductor, the second end of the first gold wire is connected with the first end of a second gold wire of the at least two gold wires, and the second end of the second gold wire is used as the second end of the second inductor.
4. The monolithic reconfigurable gallium arsenide low noise amplifier of claim 3 wherein the at least two gold wires are each a Φ 25 μm gold bonding wire.
5. The monolithic reconfigurable gallium arsenide low noise amplifier of claim 2 wherein the first inductor comprises a planar spiral inductor and a third wire;
and the first end of the third gold wire is used as the first end of the second inductor, the second end of the third gold wire is connected with the first end of the planar spiral inductor, and the second end of the planar spiral inductor is connected with the grounding end of the off-chip input matching circuit.
6. The monolithic reconfigurable gallium arsenide low noise amplifier of claim 2 wherein the first inductor is a Φ 25 μm gold bond wire;
and the first end of the phi 25 μm gold bonding wire is used as the first end of the first inductor, and the second end of the phi 25 μm gold bonding wire is connected with the grounding end of the off-chip input matching circuit.
7. The monolithic reconfigurable gallium arsenide low noise amplifier of any of claims 2 to 6 wherein the dielectric substrate is an alumina ceramic substrate having a thickness in the range of 0.343mm to 0.419 mm.
8. A preparation method of a monolithic reconfigurable gallium arsenide low noise amplifier is characterized by comprising the following steps:
preparing an off-chip input matching circuit, wherein the off-chip input matching circuit comprises an input end and a matching end;
preparing a gallium arsenide monolithic amplifying circuit, wherein the gallium arsenide monolithic amplifying circuit is not provided with an input matching network and comprises an input end and an output end;
and performing impedance matching on the off-chip input matching circuit and the gallium arsenide monolithic amplifying circuit to obtain a preset noise coefficient, wherein the matching end of the off-chip input matching circuit is bonded with the input end of the gallium arsenide monolithic amplifying circuit.
9. The method of manufacturing a monolithic reconfigurable gallium arsenide low noise amplifier as claimed in claim 8 wherein the step of manufacturing an off-chip input matching circuit comprises:
preparing at least two circular through holes with preset radiuses on one side of a medium substrate;
sputtering a metal layer on the front surface of the dielectric substrate with the through hole;
forming a patterned mask layer on the front surface of the dielectric substrate sputtered with the metal layer by utilizing a photoetching process;
electroplating the front surface of the medium substrate on which the graphical mask layer is formed to obtain a connection point of the grounded planar spiral inductor and the array, and removing the mask layer on the front surface of the medium substrate and the metal layer below the mask layer;
and bonding a second inductor on the connection point of the array through at least two gold wires, and connecting the second inductor with the planar spiral inductor through a third gold wire.
10. The method for preparing the single-chip reconfigurable gallium arsenide low noise amplifier as claimed in claim 8 or 9, wherein sputtering a metal layer on the front surface of the dielectric substrate prepared with the through hole comprises:
sputtering a titanium-tungsten layer on the front surface of the medium substrate with the through hole;
and sputtering a gold layer on the titanium-tungsten layer of the medium substrate.
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