CN111106214A

CN111106214A - Light emitting diode chip and preparation method thereof

Info

Publication number: CN111106214A
Application number: CN201911425195.3A
Authority: CN
Inventors: 杨凯; 李有群; 杨明涛; 林洪剑; 甄炯炯; 张振龙
Original assignee: Xiamen Silan Advanced Compound Semiconductor Co Ltd
Current assignee: Xiamen Silan Advanced Compound Semiconductor Co Ltd
Priority date: 2019-12-31
Filing date: 2019-12-31
Publication date: 2020-05-05
Anticipated expiration: 2039-12-31
Also published as: CN111106214B

Abstract

The application discloses a light emitting diode chip and a preparation method thereof. The light emitting diode chip includes: the transfer substrate comprises a transfer substrate, and a bonding layer, a dielectric film layer, a P-type ohmic contact layer, a P-type current expansion layer, a P-type limiting layer, an active layer, an N-type limiting layer, an N-type coarsening layer and an N-type ohmic contact layer which are sequentially stacked on the upper part of the transfer substrate; the upper electrode is positioned on the N-type ohmic contact layer; a lower electrode positioned under the transfer substrate; and a stress gradient layer is also arranged between the N-type coarsened layer and the N-type limiting layer, and the components of the aluminum element in the stress gradient layer are smaller than those of the aluminum element in the N-type coarsened layer so as to reduce the lattice mismatch degree and further reduce the stress. The light-emitting diode can effectively avoid the problems of electrode digging and electrode failure in the wire welding process, and improves the reliability and brightness of products.

Description

Light emitting diode chip and preparation method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to a light emitting diode chip and a preparation method thereof.

Background

The Light Emitting Diode (LED) emits light in the form of light by utilizing the energy difference between the N-type semiconductor and the P-type semiconductor. With its good color rendering capability, it has been widely used in public fields such as display indication, traffic sign, urban lightening, etc. Meanwhile, as an excellent semiconductor lighting source, the LED has the advantages of low energy consumption, long service life, no maintenance, environmental protection and the like. The LED backlight source can be widely applied to the fields of various indications, displays, decorations, backlight sources, general illumination and the like.

The epitaxial wafer of the quaternary system aluminum gallium indium phosphide light-emitting diode (AlGaInPLED) chip of the traditional transfer substrate is a combination of a plurality of layers, and stress can be generated due to lattice difference between the layers, so that the problem that the light-emitting diode chip is dug and broken is solved, and the product reliability risk and the customer maintenance cost are increased.

Disclosure of Invention

In view of the above problems, an object of the present invention is to provide a light emitting diode chip and a method for manufacturing the same, which can prevent the problems of electrode digging and electrode dropping during wire bonding.

According to a first aspect of the present invention, there is provided a light emitting diode chip comprising:

the transfer substrate comprises a transfer substrate, and a bonding layer, a dielectric film layer, a P-type ohmic contact layer, a P-type current expansion layer, a P-type limiting layer, an active layer, an N-type limiting layer, an N-type coarsening layer and an N-type ohmic contact layer which are sequentially stacked on the transfer substrate; and the number of the first and second groups,

the upper electrode is positioned on the N-type ohmic contact layer;

a lower electrode positioned under the transfer substrate;

and a stress gradient layer is further arranged between the N-type coarsened layer and the N-type limiting layer, and the components of the aluminum element in the stress gradient layer are smaller than those of the aluminum element in the N-type coarsened layer.

Preferably, the first and second electrodes are formed of a metal,

the material of the N-type coarsening layer is aluminum gallium indium phosphorus compound (Al)_xGa_(1-x))_0.5In_0.5P；

The N-type limiting layer is made of an aluminum indium phosphide (AlInP) compound;

the stress gradient layer is made of aluminum gallium indium phosphorus compound (Al)_yGa_(1-y))_0.5In_0.5P。

Preferably, the N-type roughened layer includes aluminum having a composition satisfying 0.4< x < 0.9.

Preferably, the stress-grading layer comprises aluminum having a composition satisfying 0.4< y < x.

Preferably, wherein the upper electrode radius is greater than 30 microns.

Preferably, the upper electrode includes a plurality of metal layers.

Preferably, the upper electrode includes a first gold layer, a gold-germanium-nickel alloy layer, a second gold layer, a platinum layer, and an aluminum layer, which are stacked in sequence, and the first gold layer is in contact with the N-type ohmic contact layer.

Preferably, the light emitting diode chip is an aluminum gallium indium phosphide light emitting diode chip.

According to another aspect of the present invention, there is provided a method for manufacturing a light emitting diode chip, including:

providing a substrate and a transfer substrate;

sequentially forming an etch stop layer, an N-type ohmic contact layer, an N-type roughened layer, an N-type limiting layer, an active layer, a P-type limiting layer, a P-type current spreading layer and a P-type ohmic contact layer on a substrate;

wherein, before forming the N-type limiting layer, a stress gradient layer is also formed on the N-type rough layer.

Preferably, the material of the N-type roughened layer is Al-ga-in-p compound (Al)_xGa_(1-x))_0.5In_0.5P, the composition of aluminum satisfies 0.4<x<0.9, and doping with silicon ions or tellurium ions;

the material of the N-type limiting layer is an aluminum indium phosphide compound AlInP;

the stress gradient layer is made of aluminum gallium indium phosphorus compound (Al)_yGa_(1-y))_0.5In_0.5P, the composition of aluminum satisfies 0.4<y<x。

Preferably, the method further comprises the following steps:

sequentially forming a dielectric film layer and a first metal layer on the P-type ohmic contact layer, and sequentially annealing the dielectric film layer and the first metal layer;

forming a second metal layer on the transfer substrate;

bonding the first metal layer on the medium film layer with the second metal layer on the transfer substrate to form a bonding layer;

removing the substrate and the corrosion stop layer to expose the N-type ohmic contact layer, manufacturing an upper electrode on the N-type ohmic contact layer and annealing the upper electrode;

and manufacturing a lower electrode under the transfer substrate and annealing the lower electrode.

Preferably, fabricating the upper electrode includes:

coating positive photoresist on the N-type ohmic contact layer, exposing for 5-15 seconds, developing for 1 minute and drying, baking for 30 minutes at 100 ℃, corroding part of the N-type ohmic contact layer by using a mixed solution of phosphoric acid and hydrogen peroxide in a volume ratio of 1:30 to expose part of the N-type roughened layer, removing the photoresist by using a degumming solution, coating negative photoresist on the part of the N-type roughened layer and the surface of the N-type ohmic contact layer, exposing for 5-15 seconds, baking for 30 minutes at 120 ℃, developing for 1 minute and drying, and manufacturing an upper electrode by using an electron beam evaporation or ion sputtering mode.

Preferably, the upper electrode is annealed by adopting a tube furnace or a rapid annealing furnace, and the annealing temperature is 290-330 ℃.

Preferably, the upper electrode radius is greater than 30 microns.

Preferably, the substrate is coated with ammonium hydroxide and hydrogen peroxide in a volume ratio of 1: 5 of the mixed solution.

Preferably, the etch stop layer is removed using a mixed solution of hydrochloric acid and phosphoric acid.

Preferably, the processing the transfer substrate includes: and carrying out treatment by using a grinding wheel or large-disc grinding equipment or carrying out corrosion treatment by using a chemical solution, so that the thickness of the transfer substrate is reduced to 100-200 microns.

Preferably, the sequentially forming a dielectric film layer and a first metal layer on the P-type ohmic contact layer includes: and sequentially cleaning the P-type ohmic contact layer and the formed dielectric film layer by using an organic or acid-base solution.

Preferably, the dielectric film layer and the first metal layer are annealed by a tube furnace at the temperature of 400-480 ℃.

Preferably, the lower electrode is annealed by adopting a tube furnace or a rapid annealing furnace, and the annealing temperature is 180-250 ℃.

Preferably, the step of forming the N-type roughened layer further includes:

coating photoresist on the surface of an N-type rough layer, exposing for 5-15 seconds, baking at 120 ℃ for 30 minutes, developing for 1 minute, cleaning and drying, etching a cutting path by using dry etching equipment, wherein the etching depth is 3-9 micrometers, and immersing in photoresist removing liquid to remove the photoresist;

after the first step is completed, coating a positive photoresist on the surface of the N-type roughened layer, exposing for 5-15 seconds, baking for 30 minutes at 120 ℃, developing for 1 minute, cleaning and drying, immersing in a roughening solution, roughening the surface, immersing in a degumming solution to remove the positive photoresist, and manufacturing a passivation layer on the side wall of the cutting channel by using a vapor deposition method.

According to the light emitting diode chip and the preparation method thereof provided by the embodiment of the invention, the stress gradient layer is arranged between the N-type coarsened layer and the N-type limiting layer, and the component of the aluminum element in the stress gradient layer is smaller than that of the aluminum element in the N-type coarsened layer, so that the gradual change of the material from the N-type coarsened layer to the N-type limiting layer is realized, and the lattice mismatch degree in the epitaxial wafer is reduced to reduce the stress. The problems of electrode digging and electrode falling in the wire welding process are solved, and the reliability of the chip is improved.

Meanwhile, the radius of the upper electrode is larger than 30 microns, the power supply area is sufficient, the brightness is high, the pressure in the wire welding process is reduced, and the possibility of electrode digging is reduced.

Moreover, the upper electrode comprises a first gold layer, a gold-germanium-nickel alloy layer, a second gold layer, a platinum layer and an aluminum layer which are stacked, wherein the first gold layer is in contact with the N-type ohmic contact layer, the conductivity is excellent, and the light emitting performance of the light emitting diode chip is further improved by combining the characteristics.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1 shows a schematic diagram of a conventional led chip structure.

Fig. 2 is a schematic diagram illustrating a structure of a light emitting diode chip according to an embodiment of the invention.

Fig. 3 is a flowchart illustrating a method for manufacturing a light emitting diode chip according to an embodiment of the invention.

Fig. 4a to 4f are schematic structural diagrams illustrating a manufacturing process of a light emitting diode chip according to an embodiment of the invention.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.

It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, article, or apparatus.

Fig. 1 is a schematic diagram illustrating a conventional vertical led chip structure. As shown in fig. 1, the conventional vertical type light emitting diode chip structure includes: the semiconductor device comprises a transfer substrate 111, an adhesive layer 110, a dielectric film layer 109, a P-type ohmic contact layer 108, a P-type current spreading layer 107, a P-type limiting layer 106, an active layer 105, an N-type limiting layer 104, an N-type coarsening layer 103, an N-type ohmic contact layer 102, an upper electrode 101 positioned on the N-type ohmic contact layer 102, and a lower electrode 112 positioned under the transfer substrate 111, which are sequentially laminated on the transfer substrate 111.

The transfer substrate 111 may be a silicon substrate, or may be another substrate (e.g., silicon carbide, zinc oxide, etc.), the adhesive layer 110 is made of Au, for example, and the dielectric film layer 109 is made of silicon dioxide or magnesium fluoride, for example; the P-type ohmic contact layer 108 is GaP, for example; the P-type current spreading layer 107 is made of GaP, for example; the P-type confinement layer 106 is made of, for example, AlInP; the N-type confinement layer 104 is made of, for example, AlInP; the N-type roughened layer 103 is made of (Al)_xGa_(1-x))_0.5In_0.5P) and doping with silicon ions or tellurium ions, the composition of aluminum being such that0.4<x<0.9; the N-type ohmic contact layer 102 is made of GaAs, for example.

The upper electrode 101 includes: a gold layer 11, a gold-germanium-nickel alloy layer 12, a gold layer 13, a platinum layer 14, and an aluminum layer 15 are sequentially stacked on the N-type ohmic contact layer 102.

Alternatively, the gold-germanium-nickel alloy layer 12 in the upper electrode may also be made of a gold-germanium alloy material; the platinum layer 14 may be made of titanium; the aluminum layer 15 may be made of gold.

The P-type ohmic contact 108, the P-type current spreading layer 107, the P-type confinement layer 106, the active layer 105, the N-type confinement layer 104, the N-type roughening layer 103 and the N-type ohmic contact layer 102 are structures in an epitaxial wafer. Because the epitaxial wafer is a combination of a plurality of layers, stress can be generated due to the lattice difference between the layers, the stress can change along with the external condition, and the larger the stress is, the larger the risk of digging an electrode and breaking the electrode is.

Fig. 2 is a schematic structural diagram of a vertical light emitting diode chip according to an embodiment of the invention. The chip structure will be used to illustrate the light emitting diode chip according to the embodiment of the present invention, and is not to be taken as a limitation to the light emitting diode of the present invention.

As shown in fig. 2, the vertical type light emitting diode chip 100 of the present invention includes: a transfer substrate 111, and an adhesive layer 110, a dielectric film layer 109, a P-type ohmic contact layer 108, a P-type current spreading layer 107, a P-type confinement layer 106, an active layer 105, an N-type confinement layer 104, a stress gradient layer S0, an N-type coarsening layer 103, and an N-type ohmic contact layer 102 which are sequentially laminated on the transfer substrate; and an upper electrode 101 on the N-type ohmic contact layer 102; and a lower electrode 112 positioned under the transfer substrate 111.

The transfer substrate 111 may be a silicon substrate, or may be another substrate (e.g., silicon carbide, zinc oxide, etc.), the adhesive layer 110 is made of Au, for example, and the dielectric film layer 109 is made of silicon dioxide or magnesium fluoride, for example; the P-type ohmic contact layer 108 is GaP, for example; the P-type current spreading layer 107 is made of GaP, for example; the P-type confinement layer 106 is made of, for example, AlInP; the N-type ohmic contact layer 102 is made of GaAs, for example.

A stress gradient layer S0 is provided between the N-type rough layer 103 and the N-type confinement layer 104,the component of the aluminum element in the stress gradient layer is smaller than that of the aluminum element in the N-type coarsened layer, so that the gradual change of the material from the N-type coarsened layer to the N-type limiting layer is realized, and the lattice mismatch degree is reduced so as to reduce the stress. Specifically, the material of the N-type roughened layer 103 is (Al)_xGa_(1-x))_0.5In_0.5P) and doped with silicon ions or tellurium ions, wherein the composition of aluminum satisfies 0.4<x<0.9, the stress gradient layer S0 is made of (Al)_yGa_(1-y))_0.5In_0.5P wherein the composition of aluminum satisfies 0.4<y<The material of the x, N type confinement layer 104 is AlInP.

It should be noted that the above descriptions of the N-type rough layer 103, the stress gradient layer S0, the N-type confinement layer 104, and the components are only for illustrative purposes, and are not intended to limit the scope of the present invention, and modifications and substitutions that can be made by those skilled in the art should fall within the scope of the present invention.

Alternatively, the gold-germanium-nickel alloy layer 12 in the upper electrode 101 may also be made of a gold-germanium alloy material; the platinum layer 14 may be made of titanium; the aluminum layer 15 may be made of gold.

The radius of the upper electrode 101 is larger than 30 microns, so that the pressure in the wire welding process is reduced, and the possibility of electrode digging is reduced.

The invention is suitable for products with vertical electrode and horizontal electrode structures.

Fig. 4a to 4f are schematic structural diagrams illustrating a manufacturing process of a light emitting diode chip according to an embodiment of the invention. The following describes a method for manufacturing a light emitting diode chip according to an embodiment of the present invention with reference to fig. 3 to 4 f.

According to a second aspect of the present invention, a method for manufacturing a light emitting diode chip is provided, which is used for manufacturing the light emitting diode chip 100 shown in fig. 2.

In step S301, an etch stop layer S2, an N-type ohmic contact layer 102, an N-type roughened layer 103, a stress gradient layer S0, an N-type confinement layer 104, an active layer 105, a P-type confinement layer 106, a P-type current spreading layer 107, and a P-type ohmic contact layer 108 are sequentially grown on a substrate S1 by an organometallic vapor phase epitaxy method, and as shown in fig. 4a, step S301 is also referred to as preparation of an epitaxial wafer.

Specifically, the substrate S1 in this embodiment may be a GaAs (gallium arsenide) substrate, and the material of the etch stop layer S2 is GaInP or Al_xGa_(1-x)InP; the N-type ohmic contact layer 102 is made of GaAs; the N-type roughened layer 103 is made of (Al)_xGa_(1-x))_0.5In_0.5P), wherein the composition of aluminum satisfies 0.4<x<0.9; the stress gradient layer S0 is made of (Al)_yGa_(1-y))_0.5In_0.5P, wherein the composition of aluminum satisfies 0.4<y<x; the N-type confinement layer 104 is made of AlInP; the P-type confinement layer 106 is made of AlInP; the P-type current spreading layer 107 is made of GaP; the P-type ohmic contact layer 108 is GaP.

In step S302, the dielectric film layer 109 and the first metal layer S3 are formed on the P-type ohmic contact layer 108 and are sequentially annealed. Specifically, the P-type ohmic contact layer 108 on the upper surface of the epitaxial wafer is cleaned by an organic or acid-base solution, a silicon dioxide or magnesium fluoride dielectric film layer 202 is formed on the P-type ohmic contact layer 108, the dielectric film layer 202 is annealed by a tube furnace at a temperature of 400-480 ℃, the surface of the dielectric film layer 202 is cleaned by the organic or acid-base solution to form a first metal layer S3, the first metal layer S3 is annealed by the tube furnace at a temperature of 400-480 ℃, and the annealing temperature is shown in fig. 4 b.

The annealing temperature of the dielectric film layer 202 and the first metal layer S3 is 400-480 ℃, so that the best effect of the invention can be achieved. And cleaning the P-type ohmic contact layer 108 by using an organic or acid-base solution to remove impurities on the P-type ohmic contact layer 108, so that the formed dielectric film layer 109 is more uniform and firmer. The dielectric film layer 109 is cleaned by organic or acid-base solution to remove impurities on the dielectric film layer 109, so that the formed first metal layer S3 is more uniform and firmer.

In step S303, a transfer substrate 111 is provided, and the front surface of the transfer substrate 111 is cleaned with an organic or acid-base solution to form a second metal layer S4, as shown in fig. 4 c.

Wherein, the front surface of the transfer substrate 111 is cleaned by organic or acid-base solution to remove impurities on the front surface of the transfer substrate 111, so that the formed second metal layer S4 is uniform and stable.

In step S304, the transfer substrate 111 is bonded to the structure shown in fig. 4b, specifically, the second metal layer S4 and the first metal layer S3 are bonded by a bonding apparatus, and the bonding layer 110 is formed after bonding. As shown in fig. 4 d.

In step S305, the substrate S1 and the etch stop layer S2 are removed, and the upper electrode 101 is fabricated and annealed, as shown in FIG. 4 e.

Specifically, ammonium hydroxide and hydrogen peroxide are used in a volume ratio of 1: 5, the substrate S1 is removed, and the etching stopper S2 is removed with a mixed solution of hydrochloric acid and phosphoric acid.

The substrate S1 and the corrosion stop layer S2 are removed respectively more thoroughly by the two mixed solutions, and the effect is better.

Coating a positive photoresist on the N-type ohmic contact layer 102, exposing for 5-15 seconds, developing for 1min, drying, baking at 100 ℃ for 30 min, corroding part of the N-type ohmic contact layer 102 by using a mixed solution of phosphoric acid and hydrogen peroxide in a volume ratio of 1:30 to expose part of the region of the N-type roughened layer 103, removing the photoresist by using a degumming solution, coating a negative photoresist on the surfaces of the N-type roughened layer 103 and the N-type ohmic contact layer 102, exposing for 5-15 seconds, baking at 120 ℃ for 30 min, developing for 1min, drying, and manufacturing the upper electrode 101 by using electron beams in an evaporation or ion sputtering mode.

The upper electrode 101 is annealed by adopting a tube furnace or a rapid annealing furnace, the annealing temperature is 290-330 ℃, and compared with the traditional electrode annealing condition of 380 ℃, the annealing temperature is obviously reduced, so that the phenomenon that crystal lattices are damaged due to serious diffusion between metal and an epitaxial wafer is avoided, and the bearing capacity of the bonding wire and the reliability of products are improved.

In step S306, the N-type roughened layer is etched to form an etching track, the N-type roughened layer is roughened, a passivation layer is formed on the side wall of the cutting track, the transfer substrate is processed, then a lower electrode is formed under the transfer substrate, the lower electrode is annealed, and cutting is performed along the etching track, as shown in fig. 4 f.

Specifically, coating photoresist on the surface of the N-type rough layer 103 (the photoresist is used for protection of subsequent dry etching), exposing for 5-15 seconds, baking for 30 minutes at 120 ℃, developing for 1 minute, cleaning and blow-drying, etching a cutting channel (a separating device) by using dry etching equipment, wherein the etching depth is 3-9 microns, and immersing into photoresist removing liquid to remove the photoresist; after the steps are completed, coating positive photoresist on the surface of the N-type roughened layer 103, exposing for 5-15 seconds, baking at 120 ℃ for 30 minutes, developing for 1 minute, cleaning and blow-drying, immersing in RH07 roughening solution, roughening the surface, and immersing in photoresist removing solution to remove the positive photoresist. And forming a passivation layer on the side wall of the cutting channel by using a vapor deposition method (PECVD).

The transfer substrate 111 is processed to form the lower electrode 112. Specifically, the thickness of the transfer substrate 111 is reduced to 100-200 microns by treatment with a grinding wheel or large-disc grinding equipment or corrosion treatment with a chemical solution; the lower electrode 112 is manufactured by immersing the substrate in an organic solution for cleaning, and performing electron beam evaporation or ion sputtering. The lower electrode 112 is annealed by a tube furnace or a Rapid Thermal Processing (RTP), and the annealing temperature is between 180 and 250 ℃.

Wherein the annealing temperature of the lower electrode is 180-250 ℃, so that the best effect of the invention can be achieved.

The light emitting diode chip is formed after laser cutting, testing, splitting and visual inspection.

Therefore, the preparation of the light emitting diode chip 100 is completed, the prepared light emitting diode chip 100 can effectively prevent the problems of electrode digging and electrode failure, and the reliability is enhanced.

According to the light emitting diode chip and the preparation method thereof provided by the embodiment of the invention, the stress gradient layer is arranged between the N-type coarsened layer and the N-type limiting layer, and the component of the aluminum element in the stress gradient layer is smaller than that of the aluminum element in the N-type coarsened layer, so that the gradual change of the material from the N-type coarsened layer to the N-type limiting layer is realized, and the lattice mismatch degree in the epitaxial wafer is reduced to reduce the stress. The problems of electrode digging and electrode falling in the wire welding process are prevented, and the reliability of the chip is enhanced.

In the above description, the details of the patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the invention, and these alternatives and modifications are intended to fall within the scope of the invention.

Claims

1. A light-emitting diode chip, comprising:

A transfer substrate and an adhesive layer, a dielectric film layer, a P-type ohmic contact layer, a P-type current spreading layer, a P-type confinement layer, an active layer, an N-type confinement layer, and an N-type roughening layer sequentially laminated on the transfer substrate layer, an N-type ohmic contact layer; and,

an upper electrode, located on the N-type ohmic contact layer;

a lower electrode, located under the transfer substrate;

Wherein, a stress gradient layer is further arranged between the N-type roughening layer and the N-type confinement layer, and the composition of the aluminum element in the stress gradient layer is smaller than the composition of the aluminum element in the N-type roughening layer .

2. The light emitting diode chip of claim 1, wherein,

The material of the N-type roughening layer is aluminum gallium indium phosphorus compound (Al _x Ga _(1-x) ) _0.5 In _0.5 P;

The material of the N-type confinement layer is aluminum indium phosphorus compound AlInP;

The material of the stress gradient layer is aluminum gallium indium phosphorus compound ( _AlyGa _(1-y) ) _0.5 In _0.5 P.

3. The light emitting diode chip of claim 2, wherein,

The N-type roughening layer includes aluminum whose composition satisfies 0.4<x<0.9.

4. The light emitting diode chip of claim 3, wherein,

The stress gradient layer includes aluminum whose composition satisfies 0.4<y<x.

5. The light emitting diode chip of claim 1, wherein the upper electrode has a radius greater than 30 microns.

6. The light emitting diode chip of claim 1, wherein,

The upper electrode includes multiple metal layers.

7. The light emitting diode chip of claim 6, wherein,

The upper electrode includes a first gold layer, a gold-germanium-nickel alloy layer, a second gold layer, a platinum layer and an aluminum layer which are stacked in sequence, and the first gold layer is in contact with the N-type ohmic contact layer.

8. The light emitting diode chip of claim 1, wherein,

The light emitting diode chip is an aluminum gallium indium phosphide light emitting diode chip.

9. A method for preparing a light-emitting diode chip, comprising:

Provide substrates and transfer substrates;

An etching stop layer, an N-type ohmic contact layer, an N-type roughening layer, an N-type confinement layer, an active layer, a P-type confinement layer, a P-type current spreading layer, and a P-type ohmic contact layer are sequentially formed on the substrate;

Wherein, before forming the N-type confinement layer, a stress gradient layer is also formed on the N-type roughened layer.

10. The method for manufacturing a light-emitting diode chip according to claim 9, wherein,

The material of the N-type roughening layer is an aluminum gallium indium phosphorus compound (Al _x Ga _(1-x) ) _0.5 In _0.5 P, the composition of aluminum satisfies 0.4<x<0.9, and is doped with silicon ions or tellurium ions;

The material of the N-type confinement layer is AlInP compound AlInP;

The material of the stress gradient layer is aluminum gallium indium phosphorus compound ( _AlyGa _(1-y) ) _0.5 In _0.5 P, and the composition of aluminum satisfies 0.4<y<x.

11. The method for manufacturing a light-emitting diode chip according to claim 9, further comprising:

forming a dielectric film layer and a first metal layer on the P-type ohmic contact layer in sequence, and sequentially annealing the dielectric film layer and the first metal layer;

forming a second metal layer on the transfer substrate;

bonding the first metal layer on the dielectric film layer with the second metal layer on the transfer substrate to form an adhesive layer;

removing the substrate and the etch stop layer to expose the N-type ohmic contact layer, forming an upper electrode on the N-type ohmic contact layer and annealing the upper electrode;

A lower electrode is fabricated and annealed under the transfer substrate.

12. The method for fabricating a light-emitting diode chip according to claim 11, wherein fabricating the upper electrode comprises:

Coat positive photoresist on the N-type ohmic contact layer, expose for 5 to 15 seconds, develop for 1 minute, blow dry, bake at 100 degrees Celsius for 30 minutes, and mix phosphoric acid and hydrogen peroxide with a volume ratio of 1:30 The solution etched a part of the N-type ohmic contact layer to expose a part of the N-type roughened layer, and removed the photoresist with a stripper solution, and the N-type roughened layer was in a part of the region with the N-type roughened layer. The surface of the ohmic contact layer is then coated with negative photoresist, exposed for 5-15 seconds, baked at 120 degrees for 30 minutes, developed for 1 minute, cleaned and dried, and the upper electrode is fabricated by electron beam evaporation or ion sputtering.

13 . The method for manufacturing a light-emitting diode chip according to claim 11 , wherein the upper electrode is annealed in a tubular furnace or a rapid annealing furnace, and the annealing temperature is between 290 and 330 degrees Celsius. 14 .

14. The manufacturing method of a light-emitting diode chip according to claim 11, wherein the radius of the upper electrode is greater than 30 microns.

15 . The method for manufacturing a light-emitting diode chip according to claim 11 , wherein the substrate is removed by using a mixed solution of ammonium hydroxide and hydrogen peroxide in a volume ratio of 1:5. 16 .

16. The manufacturing method of a light-emitting diode chip according to claim 11, wherein the etching stop layer is removed by a mixed solution of hydrochloric acid and phosphoric acid.

17 . The method for manufacturing a light-emitting diode chip according to claim 11 , wherein the processing of the transfer substrate comprises: processing with a grinding wheel or a large disc grinding device or etching with a chemical solution to reduce the thickness of the transfer substrate. 18 . to 100 to 200 microns.

18 . The method for manufacturing a light-emitting diode chip according to claim 11 , wherein sequentially forming a dielectric film layer and a first metal layer on the P-type ohmic contact layer comprises: sequentially cleaning the P-type ohmic contact layer with an organic or acid-base solution. 19 . type ohmic contact layer and the formed dielectric film layer.

19 . The method for manufacturing a light-emitting diode chip according to claim 18 , wherein the dielectric film layer and the first metal layer are annealed in a tube furnace, and the annealing temperature is between 400 and 480 degrees Celsius. 20 .

20 . The method for manufacturing a light-emitting diode chip according to claim 11 , wherein the lower electrode is annealed in a tubular furnace or a rapid annealing furnace, and the annealing temperature is between 180 and 250 degrees Celsius. 21 .

21. The method for manufacturing a light-emitting diode chip according to claim 11, wherein the step of forming the N-type roughening layer further comprises:

The first step is to coat the surface of the N-type roughened layer with photoresist, expose for 5 to 15 seconds, bake at 120 degrees Celsius for 30 minutes, develop for 1 minute, clean and blow dry, and use dry etching equipment to etch the scribe line, with an etching depth of 3 ~9 microns, immersed in glue remover to remove photoresist;

After the first step is completed, positive photoresist is coated on the surface of the N-type roughening layer, exposed for 5-15 seconds, baked at 120 degrees Celsius for 30 minutes, developed for 1 minute, washed and dried, immersed in the roughening solution, The surface is roughened, the positive photoresist is removed by immersion in a degumming solution, and a passivation layer is formed on the sidewall of the scribe line by vapor deposition.