CN111077428A - Wafer testing method - Google Patents
Wafer testing method Download PDFInfo
- Publication number
- CN111077428A CN111077428A CN201911231807.5A CN201911231807A CN111077428A CN 111077428 A CN111077428 A CN 111077428A CN 201911231807 A CN201911231807 A CN 201911231807A CN 111077428 A CN111077428 A CN 111077428A
- Authority
- CN
- China
- Prior art keywords
- test
- probe
- temperature
- testing
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 172
- 239000000523 sample Substances 0.000 claims abstract description 74
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 15
- 239000013078 crystal Substances 0.000 claims abstract description 12
- 238000013101 initial test Methods 0.000 claims abstract description 4
- 238000012790 confirmation Methods 0.000 claims abstract 2
- 238000000034 method Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000010998 test method Methods 0.000 claims description 4
- 238000003825 pressing Methods 0.000 claims description 3
- 238000004806 packaging method and process Methods 0.000 claims description 2
- 238000005299 abrasion Methods 0.000 claims 1
- 230000006872 improvement Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
- G01R31/2874—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
- G01R31/2887—Features relating to contacting the IC under test, e.g. probe heads; chucks involving moving the probe head or the IC under test; docking stations
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Environmental & Geological Engineering (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention discloses a wafer testing method, which comprises the following steps: step one, setting an electronic silicon wafer classification chart, trend parameters and an initial test temperature T0 on a probe test machine, and marking the name of a variety parameter as Tmap; step two, writing a test program, and marking a corresponding test Flow of the test at the initial temperature T0 as Flow 0; in a test program, temperature points T1-Tn and corresponding test flows Flow 1-Flow; the test program is recorded as Tprog; thirdly, calling a variety parameter Tmap by a probe test machine to carry out grain pricking position alignment confirmation; step four, calling a test program Tprog; step five, executing a test Flow0 on all test areas; step six, after the T0 test is finished, setting the test temperature to T1; step seven, the probe card corresponds to the coordinate position of the first crystal grain again; step eight, testing; step nine, the test program Tprog tests Flow1 on all test areas according to the areas required by the electronic silicon wafer classification chart; step ten, when the temperature Tn condition needs to be tested, the operations from the step six to the step nine are repeated.
Description
Technical Field
The invention relates to the field of manufacturing and testing of semiconductor devices, in particular to a method for testing a wafer.
Background
In the manufacturing process of the semiconductor device, testing is an important link for ensuring the delivery quality of the device, and through the testing, some defective products or products with unqualified performance generated in the manufacturing process can be selected, or through the testing, performance parameters of the device can be obtained, and the products can be classified.
Probe testing, which uses a probe card to contact pads (pads) on a wafer to transmit electrical signals, is a very important test item in silicon wafer testing. A typical probe card is a printed circuit board with many fine pins that make physical and electrical contact with the device under test, and the probes transmit voltage and current to and from the pads of the wafer test structure.
In the semiconductor chip testing industry, when testing wafer-level products or IP, testing or verification under multiple temperature conditions is often required.
As shown in fig. 1, when a plurality of temperature condition tests are performed, at present, a probe station is generally set with corresponding variety parameters, one temperature corresponds to one parameter, and when each temperature condition is tested, a parameter test needs to be manually called again, which is time-consuming, inflexible, and much manual intervention.
Disclosure of Invention
The invention aims to provide a wafer testing method, which can realize the testing of a wafer under the condition of multiple temperatures only by one basic probe station variety parameter.
In order to solve the above problems, the method for testing a wafer according to the present invention, which uses a test probe machine to test a chip on the wafer, comprises the following steps:
step one, setting an electronic silicon wafer classification chart and trend parameters of a crystal grain to be tested and an initial test temperature T0 on a probe test machine, and marking the name of a variety parameter as Tmap.
Step two, writing a test program, and marking the corresponding test Flow of the initial temperature T0 test as Flow 0.
In a test program, setting temperature conditions and corresponding test flows as Flow 1-Flow according to temperature points T1-Tn to be tested; the test procedure was denoted as Tprog.
And step three, installing a probe card for testing the wafer, placing the wafer to be tested on a probe testing machine, and calling a variety parameter Tmp by the probe testing machine to confirm the grain pricking position.
And step four, calling a test program Tprog on the probe test machine.
And step five, pressing a test starting button on the probe test machine, and executing a test Flow0 on all test areas by the test program according to the test areas given by the electronic silicon wafer classification chart.
Step six, when the temperature of T0 is tested to the end of the last die, the test program transmits a conditional command to the probe tester to set the test temperature to T1.
And step seven, the test program sends a command to move the tray of the probe test machine table, so that the probe card corresponds to the first crystal grain coordinate position required to be tested by the electronic silicon wafer classification chart.
And step eight, the test program sends a needle inserting and lifting command to the probe test machine for testing.
And step nine, the test program Tprog tests Flow1 on all test areas according to the areas required by the electronic silicon wafer classification chart.
Step ten, when the temperature Tn condition needs to be tested, the operations from the step six to the step nine are repeated until all the temperature points are tested.
The wafer testing device is characterized in that the probe card is provided with a probe card, the probe card is provided with a plurality of test contact pads, the probe card is provided with a plurality of probes, and the probes are arranged on the probe card.
In the sixth step, after the temperature T1 is set, the tester sends a temperature reading command to the tester to obtain the read temperature Tget, and the difference between the Tget and the temperature T1 is within a certain range, so as to determine that the temperature T1 required by the test is set completely.
In the eighth step, the overdrive amount OD (over drive) needs to be determined before the test, the OD amount is set from small to large within a certain range, when the program obtains information that the probe is in good contact with the die, the OD amount is recorded as Tod, and all chips are tested according to the OD amount under the temperature condition of T1.
In a further improvement, the testing method further comprises a remote test, wherein a test control command is sent to the test probe machine on the remote control terminal to control the test probe machine to test the wafer.
According to the wafer testing method, the testing program is arranged on the probe testing machine, so that the automatic setting of the testing temperature of the wafer under the multi-temperature testing condition is realized, the testing process at the corresponding temperature is automatically called, the wafer is automatically transferred to the next temperature point for testing after the testing at one temperature point is completed, the manual intervention is reduced, the time consumption is low, the control is flexible, and the remote control can be realized.
Drawings
Fig. 1 is a schematic flow chart of a conventional wafer test.
FIG. 2 is a flow chart illustrating a wafer testing method according to the present invention.
Detailed Description
The invention provides improvement according to the problems of the current testing mode, and the wafer can be tested under the condition of multiple temperatures only by one basic probe station variety parameter. The manual intervention is reduced, the time consumption is low, the control is flexible, and the remote control can be realized.
The wafer testing method uses a probe testing machine to test chips on a wafer, the probe testing machine is contacted with a testing contact pad on the wafer through a probe on a probe card, and the testing machine sends a testing electric signal to a crystal grain on the wafer through the probe and obtains testing data. The method specifically comprises the following steps:
step one, setting an electronic silicon wafer classification chart (mapping) and a trend parameter of a grain to be tested and an initial test temperature T0 on a probe test machine, and marking the name of a variety parameter as Tmap.
Step two, writing a test program, and marking the corresponding test Flow of the initial temperature T0 test as Flow 0.
In a test program, setting temperature conditions and corresponding test flows as Flow 1-Flow according to temperature points T1-Tn to be tested; the test procedure was denoted as Tprog.
And step three, installing a probe card for testing the wafer, placing the wafer to be tested on a probe testing machine, and calling a variety parameter Tmp by the probe testing machine to confirm the grain pricking position.
And step four, calling a test program Tprog on the probe test machine.
And step five, pressing a test starting button on the probe test machine, and executing a test Flow0 on all test areas by the test program according to the test areas given by the electronic silicon wafer classification chart.
Step six, when the T0 temperature is tested to the end of the last crystal grain, the test program transmits a conditional command for setting the test temperature to T1 to the probe test machine; after the T1 temperature is set, the tester sends a temperature reading command to the tester to obtain the read temperature Tget, and the difference between the Tget and the T1 is within a certain range, so that the T1 temperature required by the test is judged to be set completely. The difference range between the Tget and the T1 can be determined according to actual test requirements and previous test data, and if the requirement on the accuracy of the test result is not high or the previous test result is not sensitive to temperature change, the difference range can be properly widened to improve the test efficiency; if the requirement for the accuracy of the test result is high or the past test result shows sensitivity to temperature variation, the gap range needs to be properly narrowed so that the Tget is as close as possible to T1 to improve the test accuracy.
And step seven, the test program sends a command to move the tray of the probe test machine table, so that the probe card corresponds to the first crystal grain coordinate position required to be tested by the electronic silicon wafer classification chart.
And step eight, the test program sends a needle inserting and lifting command to the probe test machine for testing. The OD (over drive) quantity is set in a certain range from small to large, the selection of the OD quantity is an important link and is also a link which is easy to ignore, and the selection of the OD quantity is too small, so that the contact resistance is too large, and the yield is reduced in mass production test; the OD is too large, which not only increases the wear of the probe (prober needle) and reduces the service life thereof, but also increases the pin mark (probermark) and affects the difficulty of the subsequent packaging (package).
When the program obtained information that the probe was in good contact with the die, the OD was recorded as Tod, and all chips were tested according to the OD under the temperature condition of T1.
And step nine, the test program Tprog tests Flow1 on all test areas according to the areas required by the electronic silicon wafer classification chart.
Step ten, when the temperature Tn condition needs to be tested, the operations from the step six to the step nine are repeated until all the temperature points are tested. That is, after the T1 test is completed, the conditional command to set the test temperature to T2 is sent again, the probe card is reset, the test is performed, then the probe card is set to T3 … …, and so on until Tn, the test is completed.
The testing method provided by the invention can also realize remote testing, and the testing control command is sent to the testing probe machine on the remote control end to control the testing probe machine to test the wafer.
Aiming at the defects that the traditional test method is time-consuming and labor-consuming, the invention provides a better solution, and the wafer can be tested under the condition of multiple temperatures only by one basic probe station variety parameter. The automatic test system has the advantages of reducing manual intervention, consuming less time, being flexible to control, realizing remote control, realizing automatic continuous test, improving test efficiency and reducing test cost.
The above are merely preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A test method of a wafer uses a test probe machine to test chips on the wafer, and is characterized in that:
step one, setting an electronic silicon chip classification chart and trend parameters of a crystal grain to be tested and an initial test temperature T0 on a probe test machine, and marking the name of a variety parameter as Tmap;
step two, writing a test program, and marking a corresponding test Flow of the test at the initial temperature T0 as Flow 0;
in a test program, setting temperature conditions and corresponding test flows as Flow 1-Flow according to temperature points T1-Tn to be tested; the test program is recorded as Tprog;
step three, installing a probe card for testing a wafer, placing the wafer to be tested on a probe testing machine, and calling a variety parameter Tmp by the probe testing machine to carry out grain pricking position alignment confirmation;
step four, calling a test program Tprog on the probe test machine;
step five, pressing a test starting button on the probe test machine, and executing a test Flow0 in all test areas according to the test areas given by the electronic silicon wafer classification chart by the test program;
step six, when the T0 temperature is tested to the end of the last crystal grain, the test program transmits a conditional command for setting the test temperature to T1 to the probe test machine;
step seven, the probe card corresponds to the coordinate position of the first crystal grain again;
step eight, the test program sends a needle inserting and lifting command to the probe test machine for testing;
step nine, the test program Tprog tests Flow1 on all test areas according to the areas required by the electronic silicon wafer classification chart;
step ten, when the temperature Tn condition needs to be tested, the operations from the step six to the step nine are repeated until all the temperature points are tested.
2. The method for testing a wafer according to claim 1, wherein: the test machine is contacted with the test contact pad on the wafer through the probe on the probe card, and the test machine sends a test electric signal to be input to the crystal grain on the wafer through the probe and obtains test data.
3. The method for testing a wafer according to claim 1, wherein: in the sixth step, after the temperature T1 is set, the tester sends a temperature reading command to the tester to obtain the read temperature Tget, and the difference between the Tget and the temperature T1 is within a certain range, so that the completion of the temperature T1 set required by the test is determined.
4. The method for testing a wafer according to claim 3, wherein: the difference range between the read temperature Tget and the set temperature is comprehensively determined according to the test requirement and by referring to the data obtained by the previous test, and if the test data is sensitive to the temperature, the difference range is required to be narrowed.
5. The method for testing a wafer according to claim 1, wherein: and step seven, the test program sends a command to move the tray of the probe test machine, so that the probe card corresponds to the first crystal grain coordinate position required to be tested by the electronic silicon wafer classification chart.
6. The method for testing a wafer according to claim 1, wherein: in the step eight, the overdrive amount needs to be determined before the test, the overdrive amount is set within a certain range from small to large, when the program obtains information that the contact between the probe and the crystal grain is good, the overdrive amount at this time is recorded as Tod, and all chips are tested according to the overdrive amount under the temperature condition of T1.
7. The method for testing a wafer of claim 6, wherein: if the overdrive amount is too small, the contact resistance will be too large, and the yield will be reduced during mass production test; the excessive driving amount is selected too much, which not only increases the abrasion of the probe and reduces the service life of the probe, but also increases the needle mark and influences the difficulty of the subsequent packaging.
8. The method for testing a wafer according to claim 1, wherein: the testing method also comprises remote testing, wherein a testing control command is sent to the testing probe machine station on the remote control end to control the testing probe machine station to test the wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911231807.5A CN111077428A (en) | 2019-12-05 | 2019-12-05 | Wafer testing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911231807.5A CN111077428A (en) | 2019-12-05 | 2019-12-05 | Wafer testing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111077428A true CN111077428A (en) | 2020-04-28 |
Family
ID=70312926
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911231807.5A Pending CN111077428A (en) | 2019-12-05 | 2019-12-05 | Wafer testing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111077428A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113485157A (en) * | 2021-07-01 | 2021-10-08 | 杭州加速科技有限公司 | Wafer simulation test method and device and wafer test method |
| CN114166375A (en) * | 2022-01-11 | 2022-03-11 | 长鑫存储技术有限公司 | Method, device and electronic equipment for determining abnormal temperature test data |
| CN115575786A (en) * | 2022-09-22 | 2023-01-06 | 长鑫存储技术有限公司 | Probe test verification method and device, electronic equipment, storage medium |
| CN117438331A (en) * | 2023-12-20 | 2024-01-23 | 成都芯极客科技有限公司 | A mixed-version compatibility method for semiconductor CP test programs |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109596973A (en) * | 2018-12-29 | 2019-04-09 | 北京智芯微电子科技有限公司 | The test method of chip parameter under different temperatures |
| CN109613420A (en) * | 2019-01-30 | 2019-04-12 | 上海华虹宏力半导体制造有限公司 | The test method of chip |
| CN110470975A (en) * | 2019-08-29 | 2019-11-19 | 上海华虹宏力半导体制造有限公司 | Silicon wafer characteristic test system and method |
-
2019
- 2019-12-05 CN CN201911231807.5A patent/CN111077428A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109596973A (en) * | 2018-12-29 | 2019-04-09 | 北京智芯微电子科技有限公司 | The test method of chip parameter under different temperatures |
| CN109613420A (en) * | 2019-01-30 | 2019-04-12 | 上海华虹宏力半导体制造有限公司 | The test method of chip |
| CN110470975A (en) * | 2019-08-29 | 2019-11-19 | 上海华虹宏力半导体制造有限公司 | Silicon wafer characteristic test system and method |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113485157A (en) * | 2021-07-01 | 2021-10-08 | 杭州加速科技有限公司 | Wafer simulation test method and device and wafer test method |
| CN114166375A (en) * | 2022-01-11 | 2022-03-11 | 长鑫存储技术有限公司 | Method, device and electronic equipment for determining abnormal temperature test data |
| CN115575786A (en) * | 2022-09-22 | 2023-01-06 | 长鑫存储技术有限公司 | Probe test verification method and device, electronic equipment, storage medium |
| CN117438331A (en) * | 2023-12-20 | 2024-01-23 | 成都芯极客科技有限公司 | A mixed-version compatibility method for semiconductor CP test programs |
| CN117438331B (en) * | 2023-12-20 | 2024-04-12 | 武汉芯极客软件技术有限公司 | A mixed version compatibility method for semiconductor CP test program |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7511473B2 (en) | Pressing member and electronic component handling device | |
| CN111077428A (en) | Wafer testing method | |
| US8531202B2 (en) | Probe card test apparatus and method | |
| US4985676A (en) | Method and apparatus of performing probing test for electrically and sequentially testing semiconductor device patterns | |
| CN102426331A (en) | Needle tip position detection device and probe device | |
| CN114152858A (en) | Electrical test device and test method for cutting channel device | |
| US7719301B2 (en) | Testing method of semiconductor integrated circuit and information recording medium | |
| JP5438572B2 (en) | Probe card inspection apparatus, inspection method and inspection system | |
| CN110021334B (en) | Wafer testing method | |
| JPS6351651A (en) | Automatic wafer alignment in wafer prober | |
| CN209132315U (en) | Probe card for parallel testing technology based on pattern technology | |
| KR20050087301A (en) | Socket managing system and test system having the socket managing system | |
| CN112201644B (en) | Semiconductor device and inspection method thereof | |
| TWI714457B (en) | Testing system and its testing platform | |
| CN111157868B (en) | Wafer retesting method and testing equipment | |
| TWI735915B (en) | A wafer probe card integrated with a light source facing a device under test side and method of manufacturing | |
| US7163829B2 (en) | Method of integration testing for packaged electronic components | |
| KR20040054904A (en) | Socket and managing system for test results of semiconductor device using the socket | |
| JP4817830B2 (en) | Prober, probe contact method and program therefor | |
| KR20100073584A (en) | Probe equipment of semiconductor inspection equipment | |
| TWI844179B (en) | Testing device | |
| JP2009259942A (en) | Inspecting method and inspecting device | |
| JP2006318965A (en) | Semiconductor device inspection method and semiconductor device inspection apparatus | |
| JPH11264839A (en) | Probe card | |
| JPS5918864B2 (en) | Semiconductor wafer inspection equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200428 |