CN111029407A

CN111029407A - Field effect transistor and method of making the same

Info

Publication number: CN111029407A
Application number: CN201911166151.3A
Authority: CN
Inventors: 李争刚; 袁刚; 彭楠; 杨帅
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2019-11-25
Filing date: 2019-11-25
Publication date: 2020-04-17
Anticipated expiration: 2039-11-25
Also published as: CN111029407B

Abstract

A field effect transistor and a manufacturing method thereof are disclosed. The field effect transistor comprises: a semiconductor substrate; a fin extending along the surface of the semiconductor substrate in a first direction; a source region and a drain region of the semiconductor surface respectively located on both sides of the fin; The gate stack extending in the second direction on the surface of the semiconductor substrate, wherein the sidewall of the fin has a concave-convex pattern, and the concave-convex pattern is in contact with the gate stack. The sidewall of the fin portion of the field effect transistor has a concave-convex pattern, including nanowires with a circular cross-sectional shape, so that when the volume is the same, the contact area between the fin portion of the transistor of the present application and the gate stack is larger, and can be formed With a larger saturation current, at the same saturation current, the transistor volume of the present application is smaller, which is beneficial to reduce the chip area.

Description

Field effect transistor and method for manufacturing the same

Technical Field

The invention relates to the technical field of semiconductor devices, in particular to a field effect transistor and a manufacturing method thereof.

Background

MOSFETs are one of the most common field effect transistors in the semiconductor industry. With the progress of manufacturing, when the distance between the source and drain terminals is short, a short channel effect occurs and a leakage current is formed when the distance is developed to about 22 nm. In addition, since the contact area between the gate and the lower surface of the channel is reduced, the control Effect of the gate on the channel is reduced, and the switching characteristic is poor, a Fin-Field-Effect Transistor (FinFET) is developed. In the conventional transistor structure, a gate for controlling the current to pass through can only control the on and off of a circuit on one side of the gate, and belongs to a planar structure. In the FinFET structure, the gate is formed in a fork-shaped 3D structure similar to a fin, and can control the on and off of the circuit on both sides of the circuit. The design can greatly improve circuit control and reduce leakage current, and can also greatly shorten the gate length of the transistor.

The MOSFET with the traditional 2D structure is developed into the FinFET with the 3D structure, so that after the length L of the grid electrode is reduced to a certain manufacture procedure, the grid electrode still has a larger contact area with a channel, the channel current is better controlled, the saturation current is increased, and the leakage current and the dynamic power loss are reduced. But the channel width boost is not large enough and a better performing FinFET can be obtained by further increasing the channel width W by changing the shape of the fin.

Disclosure of Invention

In view of the above problems, an object of the present invention is to provide a field effect transistor and a method for manufacturing the same, in which a side surface of a fin in the field effect transistor has a concave-convex pattern, so that a contact area between the fin and a gate stack is increased, and a larger saturation current is formed.

According to an aspect of the present invention, there is provided a field effect transistor including: a semiconductor substrate; the fin part extends along the first direction of the surface of the semiconductor substrate; the source region and the drain region are respectively positioned on the semiconductor surface on two sides of the fin part; and the grid lamination layer is positioned above the fin part and extends along the second direction of the surface of the semiconductor substrate, wherein the side wall of the fin part is provided with a concave-convex pattern, and the concave-convex pattern is in contact with the grid lamination layer.

Preferably, the fin portion comprises a plurality of nanowires stacked in a vertical direction, and two adjacent nanowires stacked form arc surface contact.

Preferably, the cross-sectional shape of the nanowire comprises a circle.

Preferably, the fin includes a plurality of nanowires stacked in a vertical direction, and two of the nanowires stacked adjacent to each other form a planar contact.

Preferably, the cross-sectional shape of the fin portion includes a shape formed by overlapping and intersecting a plurality of circles.

Preferably, the gate stack includes a gate dielectric layer and a gate conductor, and the gate dielectric layer is used for separating the gate conductor and the fin portion.

Preferably, the gate dielectric layer material is a high-K dielectric oxide.

According to another aspect of the present invention, there is provided a method of manufacturing a field effect transistor, including: forming a fin part on a semiconductor substrate along a first direction of the surface of the semiconductor substrate; forming a grid dielectric layer covering the surface of the fin part; forming a gate conductor on the gate dielectric layer along a second direction of the surface of the semiconductor substrate; and forming a source region and a drain region on the semiconductor surface on two sides of the fin part, wherein the side wall of the fin part is provided with a concave-convex pattern, and the concave-convex pattern is contacted with the gate stack.

Preferably, the cross-sectional shape of the nanowire comprises a circle.

Preferably, the method for forming the fin portion includes: forming a first nanowire on the semiconductor substrate along a first direction; depositing a first oxide layer on the semiconductor substrate, covering the first nanowire; forming a second nanowire in the first direction on the first oxide layer; depositing a second oxide layer on the first oxide layer, covering the second nanowire; forming a third nanowire on the second oxide layer along the first direction; and depositing a third oxide layer on the second oxide layer to cover the third nanowire, wherein the cross sections of the first nanowire, the second nanowire and the third nanowire are the same in shape and size, and forming the nanowire by adopting a plasma chemical vapor deposition process.

Preferably, the gate dielectric layer material is a high-K dielectric oxide.

According to the field effect transistor, the side part of the fin part is provided with the concave-convex pattern, specifically, the plurality of cylindrical nanowires stacked in the vertical direction are used as the fin part, and under the condition that the semiconductor structure has the same volume, the larger effective channel area can be obtained, and larger saturation current is formed; under the condition of obtaining the same saturation current, the size of the device can be reduced, and the size of a chip is further reduced.

According to the manufacturing method of the field effect transistor, the oxide layer is deposited in the process of forming the fin part, the oxide layer has certain supporting and protecting effects on the fin part, the probability of damage to the fin part is reduced, and the yield is improved.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

FIG. 1 shows a schematic perspective view of a field effect transistor;

fig. 2 is a schematic perspective view of a field effect transistor according to a first embodiment of the present invention;

FIGS. 3a to 3g are sectional views of stages in a method of manufacturing a field effect transistor according to an embodiment of the present invention;

fig. 4 is a schematic cross-sectional view of a field effect transistor according to a second embodiment of the present invention.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.

The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.

It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.

If for the purpose of describing the situation directly above another layer, another area, the expression "directly above … …" or "above and adjacent to … …" will be used herein.

Fig. 1 shows a perspective view of a field effect transistor, which is a fin field effect transistor, and as shown, the fin field effect transistor 100 includes a semiconductor substrate 110, a source region 121, a drain region 122, a fin (channel layer) 123, and a gate conductor 130 and a gate dielectric layer (not shown). The contact surfaces of the gate conductor 130 and the fin 123 are the upper surface and two side surfaces of the fin 123, so that the gate conductor 130 has a large contact area with the channel, so that the channel current can be better controlled, the saturation current is increased, and the leakage current and the dynamic power loss are reduced. However, since the rise in the channel width is not sufficiently large, better performance cannot be obtained.

The inventor of the application pays attention to the problem and provides a field effect transistor with better performance and a manufacturing method thereof, under the condition that the semiconductor structure has the same volume, a larger effective channel area can be obtained, and larger saturation current is formed; under the condition of obtaining the same saturation current, the area of the device can be reduced, and the size of the chip is further reduced.

The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.

Fig. 2 shows a schematic perspective view of a field effect transistor according to an embodiment of the present invention, and as shown, the field effect transistor 200 includes: semiconductor substrate 210, source region 221, drain region 222, fin 223, and a gate stack including a gate dielectric layer 224 and a gate conductor 230.

The semiconductor substrate 210 serves to support the fin 223, the source region 221, the drain region 222, and the like. The fin portion 223 extends along a first direction parallel to the surface of the semiconductor substrate 210, the sidewall of the fin portion 223 has a concave-convex pattern for increasing the contact area between the fin portion 223 and the gate stack, the source region 221 and the drain region 222 are respectively located on the semiconductor substrate 210 on two sides of the fin portion 223, electrical communication is achieved between the source region 221 and the drain region 222 through the fin portion 223, and the gate stack is located on the fin portion 223 and extends along a second direction of the surface of the semiconductor substrate 210. The fin 223 includes a plurality of nanowires stacked in the vertical direction, two adjacent nanowires stacked are in arc contact, and the cross-sectional shape of the nanowire is, for example, circular, so that the effective release area between the fin 223 and the gate stack is larger, and a larger saturation current can be formed.

Fig. 4 is a schematic cross-sectional view illustrating a field effect transistor according to a second embodiment of the present invention, which is different from the field effect transistor according to the first embodiment in that the shape of the fin 323 is different, and the description of the same parts is omitted.

Referring to fig. 4, a portion of the fin 232 in contact with the gate stack has a concave-convex pattern for increasing a contact area of the fin 323 with the gate stack. Specifically, the cross-sectional shape of the fin 323 is similar to a shape formed by a plurality of circles arranged in a vertical direction in an intersecting manner, and a contact portion with the gate stack is, for example, an arc surface contact. In other embodiments, the shape of the fin portion may be other shapes that may increase the contact area with the gate stack.

Fig. 3a to 3g are sectional views at stages of a manufacturing method of a field effect transistor according to an embodiment of the present invention, for example, sectional views obtained by taking a partial structure of a 3D memory device along directions indicated by AA and BB lines in fig. 2. Not only the plurality of semiconductor and/or conductive structures but also an interlayer insulating layer that separates the plurality of semiconductor and/or conductive structures from each other is shown in the sectional view.

The method begins with a semiconductor substrate 210, which semiconductor substrate 210 may be silicon oxide, silicon, or silicon-on-insulator (SOI).

In this embodiment, the fin 223 of the field effect transistor 200 is formed to include three nanowires, and in other embodiments, the number of nanowires may be set as desired.

As shown in fig. 3a, a first nanowire 2231 is formed on a surface of the semiconductor substrate 210 along a first direction.

In this step, the first nanowires 2231 are deposited on the surface of the semiconductor substrate 210 along the first direction using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method.

In this embodiment, the cross-sectional shape of the first nanowire 2231 is, for example, a circle, and the material is, for example, a silicon single crystal.

Further, a first oxide layer 201 is deposited on the surface of the semiconductor substrate 210, as shown in fig. 3 b.

In this step, an oxide is deposited on the surface of the semiconductor substrate 210 using a deposition process, such as a physical vapor deposition, a chemical vapor deposition, or the like, to form the first oxide layer 201, and an etch back is performed to expose the surface of the first nanowire 2231.

In this embodiment, the first oxide layer 201 has a certain supporting effect on the first nanowires 2231 in the subsequent steps, and the first oxide layer 201 wraps the first nanowires 2231, so that the probability of damage to the first nanowires 2231 is reduced, and the yield of the device is improved.

Further, second nanowires 2232 and a second oxide layer are formed on the surface of the semiconductor structure, as shown in fig. 3 c.

In this step, a second nanowire 2232 is deposited on the surface of the semiconductor structure along a first direction by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, and the second nanowire 2232 and the first nanowire 2231 are located on the same axis in a vertical direction and have the same radius. Then, a deposition process, such as a physical vapor deposition process, a chemical vapor deposition process, or the like, is used to deposit an oxide on the surface of the semiconductor structure, so as to form a second oxide layer, and an etch back process is performed, so that the surface of the second nanowire 2232 is exposed.

The two-time deposited oxide is shown in its entirety as oxide layer 201 in fig. 3 c. However, the invention is not so limited and oxides deposited using multiple independent deposition steps may be shown as multiple oxide layers. In this embodiment, the oxide layer 201 has a certain supporting effect on the first nanowire 2231 and the second nanowire 2232 in the subsequent steps, and the oxide layer 201 wraps the first nanowire 2231 and the second nanowire 2232, so that the probability of damage to the first nanowire 2231 and the second nanowire 2232 is reduced, and the yield of the device is improved.

Further, a third nanowire 2233 and a third oxide layer are formed at the surface of the semiconductor structure, as shown in fig. 3 d.

In this step, a third nanowire 2233 is deposited on the surface of the semiconductor structure along the first direction by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, and the third nanowire 2233, the first nanowire 2231, and the second nanowire 2232 are located on the same axis in the vertical direction and have the same radius. Then, a deposition process, such as physical vapor deposition, chemical vapor deposition, etc., is used to deposit an oxide on the surface of the semiconductor structure to form a third oxide layer.

In this embodiment, the three deposited oxides are shown in their entirety as oxide layer 201 in fig. 3 d. The oxide layer 201 has a certain supporting effect on the first nanowire 2231, the second nanowire 2232 and the third nanowire 2233 in subsequent steps, and the oxide layer 201 wraps the first nanowire 2231, the second nanowire 2232 and the third nanowire 2233, so that the probability of damage to the first nanowire 2231, the second nanowire 2232 and the third nanowire 2233 is reduced, and the yield of the device is improved. In this embodiment, the first nanowire 2231, the second nanowire 2232, and the third nanowire 2233 make up the fin 223 of the field effect transistor 200.

Further, the oxide layer 201 is removed, and a gate dielectric layer 224 is formed on the surface of the semiconductor structure, as shown in fig. 3 e.

In this step, the oxide layer 201 in the semiconductor structure is removed using an etching process, such as dry etching, including ion milling etching, plasma etching, reactive ion etching, laser ablation, or wet etching or vapor phase etching. A layer of high-K material is then deposited on the surface of the semiconductor structure by chemical vapor deposition to form a gate dielectric layer 224.

In this embodiment, the gate dielectric layer 224 is made of a material such as an oxide of a high-K dielectric, and the gate dielectric layer 224 covers the surface of the fin for separating the fin from a subsequently formed gate conductor.

Further, a gate conductor 230 is deposited on the surface of the semiconductor structure in a second direction, as shown in fig. 3 f.

At this step, a deposition process, such as physical vapor deposition, chemical vapor deposition, or the like, is used to deposit polysilicon (Poly Si) in a second direction on the surface of the semiconductor structure to form the gate conductor 230.

In this embodiment, the gate conductor 230 and the gate dielectric layer 224 are gate stack structures for controlling channel current in the nanowires, and the fin portion is shaped as a plurality of stacked nanowires, so that the gate stack structure and the fin portion have a larger contact area, control over the channel current is better, and a larger saturation current can be formed.

Further, a source region 221 and a drain region 222 are respectively formed along the second direction of the semiconductor structure on both sides of the fin portion, as shown in fig. 3 g.

In this step, a deposition process, such as a physical vapor deposition process, a chemical vapor deposition process, or the like, is used to deposit a conductive material on both sides of the fin along the second direction of the semiconductor structure, so as to form the source region 221 and the drain region 222, respectively.

In this embodiment, the source region 221 and the drain region 222 are electrically alternating through the fin.

According to the field effect transistor, the plurality of nanowires stacked in the vertical direction are used as the fin portion, and under the condition that the semiconductor structure has the same volume, a larger effective channel area can be obtained, and a larger saturation current is formed; under the condition of obtaining the same saturation current, the size of the device can be reduced, and the size of a chip is further reduced.

While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A field effect transistor, comprising:

a semiconductor substrate;

the fin part extends along the first direction of the surface of the semiconductor substrate;

the source region and the drain region are respectively positioned on the semiconductor surface on two sides of the fin part;

a gate stack over the fin extending in a second direction along the surface of the semiconductor substrate,

and the side wall of the fin part is provided with a concave-convex pattern, and the concave-convex pattern is contacted with the gate stack.

2. The FET of claim 1, wherein the fin comprises a plurality of vertically stacked nanowires, two of the nanowires of adjacent stacks forming an arcing contact.

3. The field effect transistor of claim 2, wherein the cross-sectional shape of the nanowire comprises a circle.

4. The FET of claim 1, wherein the fin comprises a plurality of vertically stacked nanowires, two of the nanowires of adjacent stacks forming a planar contact.

5. The FET of claim 4, wherein a cross-sectional shape of the fin comprises a shape formed by a plurality of circular overlapping intersections.

6. The FET of claim 1, wherein the gate stack comprises a gate dielectric layer and a gate conductor, the gate dielectric layer separating the gate conductor and the fin.

7. The field effect transistor of claim 1 wherein the gate dielectric layer material is a high-K dielectric oxide.

8. A method of manufacturing a field effect transistor, comprising:

forming a fin part on a semiconductor substrate along a first direction of the surface of the semiconductor substrate;

forming a grid dielectric layer covering the surface of the fin part;

forming a gate conductor on the gate dielectric layer along a second direction of the surface of the semiconductor substrate;

forming a source region and a drain region on the semiconductor surface at two sides of the fin portion,

9. The method of manufacturing of claim 8, wherein the fin comprises a plurality of nanowires stacked in a vertical direction, two of the nanowires stacked adjacent to form an arcing contact.

10. The method of manufacturing of claim 9, wherein the cross-sectional shape of the nanowire comprises a circle.

11. The method of manufacturing of claim 8, wherein the fin comprises a plurality of nanowires stacked in a vertical direction, two of the nanowires stacked adjacent forming a planar contact.

12. The method of manufacturing of claim 11, wherein the fin has a cross-sectional shape that includes a plurality of circular overlapping intersections.

13. The method of manufacturing of claim 8, wherein the fin formation method comprises:

forming a first nanowire on the semiconductor substrate along a first direction;

depositing a first oxide layer on the semiconductor substrate, covering the first nanowire;

forming a second nanowire in the first direction on the first oxide layer;

depositing a second oxide layer on the first oxide layer, covering the second nanowire;

forming a third nanowire on the second oxide layer along the first direction;

depositing a third oxide layer on the second oxide layer, covering the third nanowire,

the first nanowire, the second nanowire and the third nanowire are identical in cross-sectional shape and size, and the nanowires are formed by adopting a plasma chemical vapor deposition process.

14. The method of manufacturing of claim 8, wherein the gate dielectric layer material is a high-K dielectric oxide.