CN111029312A - A kind of hermetic packaging device and hermetic packaging method - Google Patents
A kind of hermetic packaging device and hermetic packaging method Download PDFInfo
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- CN111029312A CN111029312A CN201911155125.0A CN201911155125A CN111029312A CN 111029312 A CN111029312 A CN 111029312A CN 201911155125 A CN201911155125 A CN 201911155125A CN 111029312 A CN111029312 A CN 111029312A
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Abstract
本发明公开了一种气密封装器件及气密封装方法，气密封装器件包括：下封装结构包括第一陶瓷基板，第一陶瓷基板设有第一通孔，第一通孔内的金属记为第一金属柱；第一芯片，设置在第一陶瓷基板上，第一芯片的焊盘与第一金属柱相连；中间封装结构，设置在下封装结构上，包括第二陶瓷基板，第二陶瓷基板设有第二通孔，第二通孔内的金属记为第二金属柱；第二芯片，设置在第二陶瓷基板上，第二芯片的焊盘与第二金属柱相连，连接第二芯片的第二金属柱通过导电结构与第一芯片或所述第一金属柱相连；上封装结构，设置在中间封装结构上。本发明形成垂直的两个封装腔，敏感元件单独存放，避免了二次封装，提高了集成度。
The invention discloses an airtight packaging device and a hermetic packaging method. The airtight packaging device comprises: a lower packaging structure includes a first ceramic substrate, the first ceramic substrate is provided with a first through hole, and a metal mark in the first through hole is formed. is the first metal column; the first chip is arranged on the first ceramic substrate, and the pad of the first chip is connected to the first metal column; the intermediate packaging structure is arranged on the lower packaging structure, including the second ceramic substrate, the second ceramic The substrate is provided with a second through hole, and the metal in the second through hole is marked as the second metal column; the second chip is arranged on the second ceramic substrate, and the pad of the second chip is connected with the second metal column, which is connected to the second metal column. The second metal column of the chip is connected with the first chip or the first metal column through the conductive structure; the upper package structure is arranged on the middle package structure. The invention forms two vertical encapsulation cavities, and the sensitive elements are stored separately, thus avoiding secondary encapsulation and improving the integration degree.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to an airtight packaging device and an airtight packaging method.
Background
From a cellular communication network of hundreds of megameters, to the current 4G communication and 5G communication which is popularized immediately and has the working frequency of dozens of gigahertz, and to the THz field, the working frequency band of the radio frequency microwave circuit is higher and higher. Although the corresponding chip package is upgraded by multiple iterations, the corresponding chip package has many defects.
Along with the improvement of the integration level of chip functions and the reduction of the size of devices, the integrated design of chips, chip adapter plates and shells is more critical, and in order to meet different use requirements among the chips when the chips are packaged and used at present, sensitive chips are often required to be packaged independently, and then the independently packaged chips are connected with the chips in the airtight packaging devices for use, so that the integration level of the airtight packaging devices is reduced.
Disclosure of Invention
The embodiment of the invention provides an airtight packaging device and an airtight packaging method, and aims to solve the problem that the existing airtight packaging device is low in integration level.
A first aspect of an embodiment of the present invention provides a hermetically sealed device, including:
the lower packaging structure adopts a first ceramic substrate as a mounting baseplate, the first ceramic substrate is provided with a first through hole penetrating through the upper surface and the lower surface of the first ceramic substrate, metal is filled in the first through hole, and the metal in the first through hole is marked as a first metal column;
the first chip is arranged on the first ceramic substrate, and a bonding pad of the first chip is connected with the first metal column through a first bonding wire;
the middle packaging structure is arranged on the lower packaging structure, a second ceramic substrate is adopted as a middle mounting plate in the middle packaging structure, a second through hole penetrating through the upper surface and the lower surface of the second ceramic substrate is formed in the second ceramic substrate, metal is filled in the second through hole and marked as a second metal column, and the lower packaging structure and the middle packaging structure form a first packaging cavity for containing a first chip;
the second chip is arranged on the second ceramic substrate, a bonding pad of the second chip is connected with a second metal column through a second bonding wire, and the second metal column connected with the second chip is connected with the first chip or the first metal column through a conductive structure;
and the upper packaging structure is arranged on the middle packaging structure, and the middle packaging structure and the upper packaging structure form a second packaging cavity for accommodating the second chip.
In an embodiment of the present application, the conductive structure is a spring column, a first end of the spring column is connected to the first chip or the first metal column, and a second end of the spring column is connected to the second metal column connected to the second chip.
In an embodiment of the present application, the lower package structure includes:
a first ceramic substrate;
the first metal enclosure frame is arranged on the first ceramic substrate and used for arranging the first metal enclosure frame;
the intermediate package structure includes:
a second ceramic substrate;
the front metal enclosure frame is arranged on the front side of the second ceramic substrate and used for arranging the front metal enclosure frame;
the back metal enclosure frame is arranged on the back of the second ceramic substrate and used for arranging the back metal enclosure frame, and the lower surface of the back metal enclosure frame is connected with the upper surface of the first metal enclosure frame;
the upper package structure includes:
a cover plate;
the second metal encloses the frame, sets up be used for setting up the position that the frame was enclosed to the second metal under the apron, the lower surface that the frame was enclosed to the second metal with the upper surface that the frame was enclosed to the front metal links to each other.
In an embodiment of the present application, an isolation layer is disposed on a lower surface of the second ceramic substrate.
In an embodiment of the present application, the hermetically sealed device further comprises:
and the copper heat-conducting columns are arranged on the back surface of the first ceramic substrate, wherein at least a preset number of copper heat-conducting columns are used as input and output pins of the airtight packaging device and are connected with the first metal columns.
In the embodiment of the application, the first metal column connected with the bonding pad connected with the first chip is a conduction column, and a circle of signal shielding structures formed by the first metal column is further arranged on the periphery of the conduction column.
A second aspect of an embodiment of the present invention provides a hermetic packaging method, including:
mounting a first chip on the prepared lower package structure;
mounting a second chip on the prepared intermediate packaging structure;
welding the middle packaging structure above the lower packaging structure, and connecting a second metal column connected with a second chip with the first chip through a conductive structure to form a first packaging cavity for accommodating the first chip;
and welding the prepared upper packaging structure above the middle packaging structure to form a second packaging cavity for containing a second chip.
In an embodiment of the present application, a specific preparation method of the lower package structure includes:
preparing a first through hole on a first ceramic substrate, wherein the first through hole penetrates through the upper surface and the lower surface of the first ceramic substrate;
filling metal in the first through hole to form a first metal column penetrating through the upper surface and the lower surface of the first ceramic substrate;
manufacturing a first metal enclosure frame at a position, reserved on the first ceramic substrate, for manufacturing the first metal enclosure frame;
correspondingly, the mounting of the first chip on the prepared lower package structure is as follows:
and mounting a first chip in the first metal frame on the first ceramic substrate, and connecting a bonding pad of the first chip with the first metal column through a first bonding wire.
In an embodiment of the present application, a specific preparation method of the intermediate package structure includes:
preparing a second through hole on a second ceramic substrate, wherein the second through hole penetrates through the upper surface and the lower surface of the second ceramic substrate;
filling metal into the second through hole to form a second metal column penetrating through the upper surface and the lower surface of the second ceramic substrate;
preparing a front metal enclosure frame at a position, provided with the front metal enclosure frame, reserved on the front of the second ceramic substrate;
preparing a back metal enclosure frame at a position where the back metal enclosure frame is arranged and reserved on the back of the second ceramic substrate;
correspondingly, the step of mounting the second chip on the prepared intermediate packaging structure is as follows:
mounting a second chip in the metal enclosure frame on the front surface of the second ceramic substrate, and connecting a bonding pad of the second chip with a second metal column through a second bonding wire;
correspondingly, will middle packaging structure welds the packaging structure top down, and will connect the second metal post of second chip pass through conductive structure with first chip links to each other, and the first packaging cavity that forms and hold first chip does:
and welding the back metal enclosure frame above the first metal enclosure frame, and connecting a second metal column connected with a second chip with the first chip or the first metal column through a conductive structure to form a first packaging cavity for accommodating the first chip.
In an embodiment of the present application, before preparing the front metal enclosure frame at a position where the front metal enclosure frame is disposed and reserved on the front surface of the second ceramic substrate, the method further includes:
and preparing an isolation layer on the back surface of the second ceramic substrate.
According to the invention, the lower packaging structure and the middle packaging structure form a first packaging cavity for containing the first chip, and the middle packaging structure and the upper packaging structure form a second packaging cavity for containing the second chip, so that the airtight packaging device forms two independent packaging cavities which are vertically distributed, the sensitive chips can be respectively placed in the first packaging cavity and the second packaging cavity, and the sensitive elements are not required to be separately packaged and then connected with the airtight packaging device, so that secondary packaging is avoided, and the integration level of the airtight packaging device is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.
FIG. 1 is a schematic diagram of a hermetically packaged device according to an embodiment of the present invention;
FIG. 2 is a schematic flow chart of a hermetic packaging method according to an embodiment of the present invention;
FIG. 3 is a cross-sectional view of a first via hole formed in a first ceramic substrate according to an embodiment of the present invention;
FIG. 4 is a schematic top view of a first through hole formed in a first ceramic substrate according to an embodiment of the present invention;
FIG. 5 is a cross-sectional structure of a first front-side seed layer and a first back-side seed layer deposited according to an embodiment of the invention;
FIG. 6 is a cross-sectional structure of a first photoresist layer after being formed according to an embodiment of the present invention;
fig. 7 is a schematic cross-sectional view of a first front side conductor layer and a first back side conductor layer after being formed according to an embodiment of the invention;
FIG. 8 is a first cross-sectional view of a copper heat pillar according to one embodiment of the present invention;
FIG. 9 is a second cross-sectional structural view of a copper heat-conducting pillar according to an embodiment of the present invention;
FIG. 10 is a schematic cross-sectional view of a copper heat-conducting pillar according to an embodiment of the present invention;
fig. 11 is a schematic cross-sectional structural diagram of fabricating a first metal enclosure and a solder mask according to an embodiment of the present invention;
fig. 12 is a schematic cross-sectional view illustrating a first chip mounting structure according to an embodiment of the present invention;
fig. 13 is a schematic cross-sectional structure diagram illustrating a second front-side seed layer and a second back-side seed layer formed on a second ceramic substrate according to an embodiment of the present invention;
fig. 14 is a schematic cross-sectional structure diagram illustrating the fabrication of a second front side conductor layer and a second back side conductor layer according to an embodiment of the invention;
fig. 15 is a schematic cross-sectional view of the second front side conductor layer and the second back side conductor layer removed according to an embodiment of the invention;
fig. 16 is a schematic cross-sectional structural diagram illustrating the fabrication of the front metal frame, the back metal frame and the first coupling structure according to an embodiment of the present invention;
fig. 17 is a schematic structural diagram of an upper package structure according to an embodiment of the present invention.
Wherein: 1. a first ceramic substrate; 2. a first through hole; 3. a first front side seed layer; 4. a first photoresist layer; 5. a first metal pillar; 6. a first front-side conductor layer; 7. a first back side conductor layer; 8. a fifth photoresist layer; 9. a copper heat-conducting post; 10. a first metal enclosure frame; 11. a first chip; 12. a second ceramic substrate; 13. a solder resist layer; 14. a first partition wall; 15. a conductive structure; 16. a second through hole; 17. a second front side seed layer; 18. a second backside seed layer; 19. a second front-side conductor layer; 20. a second back side conductor layer; 21. a first coupling structure; 22. a front metal enclosure frame; 23. a back metal enclosure frame; 24. a cover plate; 25. a third front side seed layer; 26. a third back side conductor layer; 27. a third front-side conductor layer; 28. a second metal enclosure frame;
Detailed Description
In order to make the technical solution better understood by those skilled in the art, the technical solution in the embodiment of the present invention will be clearly described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is a part of the embodiment of the present invention, and not a whole embodiment. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present disclosure without any creative effort shall fall within the protection scope of the present disclosure.
The terms "include" and any other variations in the description and claims of this document and the above-described figures, mean "including but not limited to", and are intended to cover non-exclusive inclusions. Furthermore, the terms "first" and "second," etc. are used to distinguish between different objects and are not used to describe a particular order.
Implementations of the present invention are described in detail below with reference to the following detailed drawings:
as shown in fig. 1, a hermetically sealed device provided by an embodiment of the present invention includes:
the lower packaging structure adopts a first ceramic substrate 1 as a mounting baseplate, the first ceramic substrate 1 is provided with a first through hole 2 penetrating through the upper surface and the lower surface of the first ceramic substrate 1, metal is filled in the first through hole 2, and the metal in the first through hole 2 is marked as a first metal column 5;
the first chip 11 is arranged on the first ceramic substrate 1, and a bonding pad of the first chip 11 is connected with the first metal column 5 through a first bonding wire;
the middle packaging structure is arranged on the lower packaging structure, the middle packaging structure adopts a second ceramic substrate 12 as a middle mounting plate, the second ceramic substrate 12 is provided with a second through hole 16 penetrating through the upper surface and the lower surface of the second ceramic substrate 12, metal is filled in the second through hole 16, the metal in the second through hole 16 is marked as a second metal column, and the lower packaging structure and the middle packaging structure form a first packaging cavity for accommodating the first chip 11;
the second chip is arranged on the second ceramic substrate 12, a bonding pad of the second chip is connected with a second metal column through a second bonding wire, and the second metal column connected with the second chip is connected with the first chip 11 or the first metal column 5 through a conductive structure 15;
and the upper packaging structure is arranged on the middle packaging structure, and the middle packaging structure and the upper packaging structure form a second packaging cavity for accommodating the second chip.
In this embodiment, the present invention is not limited to two enclosures, and more than two enclosures may be vertically disposed. The metal slurry is a copper electroplating solution. The first chip 11 and the second chip may both be radio frequency chips. The first metal column 5 connected with the bonding pad of the first chip 11 is marked as a conduction column, and a circle of signal shielding structure formed by the first metal column 5 is further arranged on the periphery of the conduction column. And a circle of signal shielding structure formed by the second metal column is arranged on the periphery of the second metal column. The signal shielding structures may be coaxial-like signal shielding structures.
Since the conductive via needs to transmit a signal, a signal shielding structure needs to be provided for the conductive via. The signal shielding structure in the present application may be configured as follows: when the first through hole 2 corresponding to the conducting column is prepared, a circle of the first through hole 2 is prepared at the periphery of the first through hole 2, metal is also injected into the circle of the first through hole 2 to form a first metal column 5, and the first metal column 5 surrounding the conducting column can form a signal shielding structure.
In the present embodiment, the first ceramic substrate 1 and the second ceramic substrate 12 are previously sintered, and may be, for example, alumina ceramic, aluminum nitride ceramic, quartz, or the like. The diameter of the first through-hole 2 can be selected with reference to the following constraints: the ratio of the thickness of the first ceramic substrate 1 to the diameter of the first through hole 2 is 3:1 to 4:1, and the diameter of the first through hole 2 may be set to 70 to 125 μm depending on the thickness of the first ceramic substrate 1 at the time of actual packaging. The diameter of the second through-hole 16 may be selected with reference to the following constraints: the ratio of the thickness of the second ceramic substrate 12 to the diameter of the second via hole 16 is 3:1 to 4:1, and the diameter of the second via hole 16 may be set to 70 to 125 μm depending on the thickness of the second ceramic substrate 12 at the time of actual packaging.
In the embodiment of the invention, the lower packaging structure and the middle packaging structure form a first packaging cavity for containing the first chip 11, and the middle packaging structure and the upper packaging structure form a second packaging cavity for containing the second chip, so that the airtight packaging device forms two independent packaging cavities which are vertically distributed, the sensitive chips can be respectively placed in the first packaging cavity and the second packaging cavity, and the sensitive elements are not required to be separately packaged and then connected with the airtight packaging device, thereby avoiding secondary packaging and improving the integration level of the airtight packaging device. The invention arranges two independent packaging cavities to independently package the sensitive chip, thereby avoiding secondary packaging of the sensitive element and directly using the bare chip.
As shown in fig. 1, in the embodiment of the present invention, the conductive structure 15 is a spring pillar, a first end of the spring pillar is connected to the first chip 11 or the first metal pillar 5, and a second end of the spring pillar is connected to a lower surface of a second metal pillar connected to the second chip.
In this embodiment, the spring post may be prepared, or may be a spring post purchased from the market, and the spring post is made of a metal material. The spring post can transmit signals and also can buffer the micro deformation caused by heating to eliminate the expansion stress.
As shown in fig. 1, in an embodiment of the present invention, the hermetically sealed device further includes:
and the copper heat-conducting columns 9 are arranged on the back surface of the first ceramic substrate 1, wherein at least a preset number of copper heat-conducting columns 9 are used as input and output pins of the airtight packaging device and are connected with the first metal columns 5.
In the present embodiment, the copper heat-conducting pillars 9 on the back surface of the first ceramic substrate 1 satisfy the following constraint conditions: the height of the copper heat-conducting column 9 is 200 and 1000 microns, and the precision of the copper heat-conducting column 9 is +/-5 microns.
In the embodiment of the present invention, a part of the copper heat-conducting pillars 9 may be directly connected to the first ceramic substrate 1, and the copper heat-conducting pillars 9 connected to the first ceramic substrate 1 may dissipate heat on the first ceramic substrate 1, and may also support the entire package enclosure, so that the package enclosure is more stable when connected to other structures. The copper heat-conducting column 9 connected with the first metal column 5 serves as a packaging I/O leading-out end and can serve as a heat dissipation channel to help a packaging device dissipate heat, and on the other hand, the heat stress of the airtight packaging device and a PCB mounting mother board during mounting can be buffered, so that the airtight packaging device is prevented from cracking due to thermal mismatch when being connected with the PCB mounting mother board.
As shown in fig. 1, in an embodiment of the present invention, the lower package structure includes:
a first ceramic substrate 1;
a first metal enclosure frame 10 disposed at a position on the first ceramic substrate 1 for disposing the first metal enclosure frame 10;
the intermediate package structure includes:
a second ceramic substrate 12;
a front metal enclosure frame 22 disposed on the front surface of the second ceramic substrate 12, for disposing the front metal enclosure frame 22;
the back metal surrounding frame 23 is arranged on the back of the second ceramic substrate 12 and used for arranging the back metal surrounding frame 23, and the lower surface of the back metal surrounding frame 23 is connected with the upper surface of the first metal surrounding frame 10;
the upper package structure includes:
a cover plate 24;
and a second metal enclosure frame 28 disposed below the cover plate 24 and used for disposing the second metal enclosure frame 28, wherein the lower surface of the second metal enclosure frame 28 is connected with the upper surface of the front metal enclosure frame 22.
In this embodiment, the bottom of the second chip may also be connected to the front metal enclosure frame 22 through a second connection structure, the connection structure plays a role of transferring heat, the second connection structure transfers the heat of the second chip to the front metal enclosure frame 22, and the front metal enclosure frame 22 transfers the heat to the second metal enclosure frame 28 downward, so as to transfer the heat away.
In this embodiment, the upper surface of the first metal enclosure frame 10 is provided with a first engaging bump, the upper surface of the front metal enclosure frame 22 is provided with a front engaging bump, and the lower surface of the back metal enclosure frame 23 is provided with a back engaging bump matched with the front engaging bump; the lower surface of the second metal surrounding frame 28 is provided with a second engaging bump matched with the front engaging bump. In manufacturing, the first metal enclosure frame 10 and the back metal enclosure frame 23 are joined by a laser side welding technique. The front metal enclosure frame 22 and the second metal enclosure frame 28 are joined by a laser side fusion welding technique.
As shown in fig. 1, in an embodiment of the present invention, the hermetically sealed device further includes:
the first front seed layer 3 is positioned on the upper surface of the first ceramic substrate 1 and the inner side wall of the first through hole 2, and the metal is connected with the first through hole 2 through the first front seed layer 3;
the first front conductor layer 6 is located above the first front seed layer 3, a first area of the upper surface of the first front conductor layer 6 is used for arranging the first metal enclosure frame 10, a second area of the upper surface of the second front conductor layer 19 is used for thickening the first metal column 5, and a third area of the first front conductor layer 6 is used for mounting the first chip 11.
A first back seed layer located on the lower surface of the first ceramic substrate 1;
and the first back conductor layer 7 is positioned below the second back seed layer 18, a first area of the lower surface of the first back conductor layer 7 is used for thickening the first metal column 5, and a second area of the lower surface of the first back conductor layer 7 is used for preparing the copper heat conduction column 9.
The first front conductor layer is arranged above the first ceramic substrate and the first metal column, the first back conductor layer is arranged below the first ceramic substrate and the first metal column, and a complete cladding structure is formed between the first ceramic substrate and the first metal column, so that the air tightness is ensured.
As shown in fig. 1, in an embodiment of the present invention, the hermetically sealed device further includes:
a second front seed layer 17, which is located on the upper surface of the second ceramic substrate 12 and the inner sidewall of the second via hole 16, and the metal is connected to the second via hole 16 through the second front seed layer 17;
and a second front conductor layer 19 located above the second front seed layer 17, wherein a first region of the upper surface of the second front conductor layer 19 is used for setting a front metal enclosure frame 22, a second region of the upper surface of the second front conductor layer 19 is used for thickening the second metal column, and a third region of the upper surface of the second front conductor layer 19 is used for mounting a second chip.
A second back seed layer 18 located on the lower surface of the second ceramic substrate 12;
and a second back conductor layer 20 located below the second back seed layer 18, wherein a first region of a lower surface of the second back conductor layer 20 is used for manufacturing a back metal enclosure frame 23, and a second region of the lower surface of the second back conductor layer 20 is used for thickening the second metal pillar.
In this embodiment, the second front-side seed layer 17 and the second front-side conductor layer 19 may serve as a second connection structure to interconnect the second chip and the front-side metal frame 22. The second front conductor layer is arranged above the second ceramic substrate and the second metal column, the second back conductor layer is arranged below the second ceramic substrate and the second metal column, and a complete coating structure is formed between the second ceramic substrate and the second metal column, so that the air tightness is ensured.
As shown in fig. 1, in an embodiment of the present invention, the hermetically sealed device further includes:
a third backside seed layer disposed on the lower surface of the cap plate 24;
and a third back side conductor layer 26 disposed below the third back side seed layer, wherein a first region of a lower surface of the third back side conductor layer 26 is used for forming a second metal enclosure 28.
In this embodiment, the materials of the first front seed layer 3, the first back seed layer, the second front seed layer 17, the second back seed layer 18, and the third back seed layer may all be Ti or copper, the thicknesses may all be 50nm to 5000nm, or other thicknesses may be selected according to specific needs.
In the present embodiment, the thicknesses of the first front side conductor layer 6, the first back side conductor layer 7, the second front side conductor layer 19, the second back side conductor layer 20 and the third back side conductor layer 26 can be all between 15-20 μm, so that airtightness is realized, and the materials can all be copper.
In the embodiment of the present invention, a shielding layer is further disposed on the back surface of the cover plate 24, and the shielding layer may be disposed on the back surface of the entire cover plate 24 or only above the second chip, and the shielding layer functions to reduce interference of an external signal to the second chip. If the back surface of the cap plate 24 is provided with the third back surface seed layer, the shielding layer is provided in a region for providing the shielding layer on the lower surface of the third back surface seed layer, and if the back surface of the cap plate 24 is provided with the third back surface seed layer and the third back surface conductor layer 26, the shielding layer is provided in a region for providing the shielding layer on the lower surface of the third back surface conductor layer 26.
As shown in fig. 1, in the embodiment of the present invention, a third through hole may be formed in the cover plate 24, and the third through hole is filled with metal, and the metal in the third through hole is denoted as a third metal column. The third through hole formed in the cover plate 24 serves to keep the same manufacturing method as that of the first ceramic substrate 1 and the second ceramic substrate 12 during manufacturing, so that the manufacturing is more convenient and simpler, and on the other hand, to facilitate the continuous heightening of the cover plate 24 for manufacturing additional package cavities.
In the embodiment of the present invention, the lower surface of the second ceramic substrate 12 is provided with an isolation layer.
In this embodiment, the isolation layer may be a metal material, such as a metal copper material, and the isolation layer is disposed on the lower surface of the second ceramic substrate 12, and may cover all the back surfaces of the second ceramic substrate 12, or may be disposed only on the lower surface of the second ceramic substrate 12 corresponding to the upper side of the first chip 11, and the isolation layer functions to reduce the mutual influence of the radiation of the second chip and the first chip 11.
In practical applications, if the back surface of the second ceramic substrate 12 is provided with the second back surface seed layer 18, the isolation layer is disposed on the second back surface seed layer 18 in an area for preparing the isolation layer, and if the back surface of the second ceramic substrate 12 is provided with the second back surface seed layer 18 and the second back surface conductor layer 20, the isolation layer is disposed on the second back surface conductor layer 20 in an area for preparing the isolation layer.
As shown in fig. 1, in an embodiment of the present invention, the hermetically sealed device further includes:
and a first coupling structure 21 disposed on the lower surface of the second ceramic substrate 12 and above the first chip 11.
And a second coupling structure disposed on a lower surface of the cap plate 24 and above the second chip.
In this embodiment, the first coupling structure 21 and the second coupling structure may be both planar structures or stepped structures, the first coupling structure 21 may be disposed when the first chip 11 needs to be coupled to increase the coupling of the first chip 11, and the second coupling structure may be disposed when the second chip needs to be coupled to increase the coupling of the second chip.
As shown in fig. 1, in the embodiment of the present invention, when there are at least two first chips 11 and isolation is required between the first chips 11, the hermetically sealed device further includes: and a first isolation wall 14 disposed on the first ceramic substrate, wherein the plurality of first chips 11 to be isolated are located in different airtight spaces, and the airtight spaces are isolated from each other by the first isolation wall 14.
When the number of the second chips is at least two and the second chips need to be isolated from each other, the hermetically packaged device further includes: and the second isolation wall is arranged on the second ceramic substrate, a plurality of second chips to be isolated are positioned in different airtight spaces, and the airtight spaces are isolated by the second isolation wall.
In the present embodiment, the first chips 11 are separated by the first separation walls 14, so that the first chips 11 do not interfere with each other. The thickness of the first isolation wall 14 may be between 150 and 200 μm. The first partition wall 14 may be made of a metal material.
As shown in fig. 1, in an embodiment of the present invention, the hermetically sealed device further includes:
and a solder resist layer 13 provided on the back surface of the first ceramic substrate 1 in a region other than the region of the first metal stud 5.
In this embodiment, providing the solder resist layer 13 on the outer mounting surface on the back surface of the first ceramic substrate 1 can improve the reliability and the convenience of assembly of the hermetically packaged device.
If the back surface of the first ceramic substrate 1 is provided with the copper heat conduction post 9, the solder resist layer 13 is located in the other region than the region of the copper heat conduction post 9.
In the embodiment of the present invention, the front surface of the cover plate 24 may further be provided with heat dissipation fins, the bottom of the first chip 11 is connected to the first metal frame 10 through a first connection structure, the second chip is connected to the front surface metal frame 22 through a second connection structure, and the first connection structure may be the first front surface seed layer 3 and the first front surface conductor layer 6.
In the present embodiment, the heat dissipation fins are directly formed on the cover plate 24, which is beneficial to heat dissipation of the first chip 11 and the second chip. When the cover plate 24 is provided with heat dissipating fins.
In the embodiment of the present invention, a planar antenna may be further disposed on the front surface of the cover plate 24, the lower surface of the planar antenna is attached to the upper surface of the cover plate 24, a through hole of the cover plate 24 is disposed on the cover plate 24, the through hole of the cover plate 24 is filled with metal, and the metal in the through hole of the cover plate 24 is recorded as a metal pillar of the cover plate 24. The planar antenna is connected to the metal posts of the cover plate 24 within the through holes of the cover plate 24. The lower end of the metal column of the cover plate 24 is connected with the first end of a spring column, the second end of the spring column is connected with the second chip, and the cover plate can also be connected with the first chip 11 through the spring column and the second metal column.
In the present embodiment, the planar antenna is directly formed on the cover plate 24, and the lower surface of the planar antenna is attached to the upper surface of the cover plate 24.
As shown in fig. 2, a hermetic package method according to an embodiment of the present invention includes:
s101, mounting the first chip 11 on the prepared lower package structure.
In this embodiment, the first chip 11 needs to be packaged on the lower package structure, the first chip 11 may be mounted on the first ceramic substrate 1 of the lower package structure by surface mounting, and inside the first metal enclosure frame 10, the first chip 11 needs to be connected to the metal in the first through hole 2 of the first ceramic substrate 1 by a bonding wire. For convenience of description, the metal paste in the first via hole 2 of the first ceramic substrate 1 may be referred to as a first metal pillar 5.
And S102, mounting a second chip on the prepared intermediate packaging structure.
In this embodiment, a second chip needs to be packaged in the intermediate package structure, and the second chip can be mounted on the second ceramic substrate 12 of the lower package structure in a surface mount manner, and inside the front metal frame 22, the second chip needs to be connected to the metal in the second through hole 16 of the second ceramic substrate 12 through a bonding wire. For convenience of description, the metal in the second via hole 16 of the second ceramic substrate 12 may be referred to as a second metal pillar.
And S103, welding the middle packaging structure above the lower packaging structure, and connecting a second metal column connected with a second chip with the first chip 11 through a conductive structure 15 to form a first packaging cavity for accommodating the first chip 11.
In the present embodiment, the back metal frame 23 of the middle package structure is welded to the first metal frame 10 of the lower package structure, and laser welding may be adopted to ensure the air tightness of the package housing.
In order to ensure that the first chip 11 is grounded or the first chip 11 is connected to the second chip, the conductive structures 15 are used to communicate with each other, wherein the conductive structures 15 are spring columns. The spring posts may be commercially available or may be pre-prepared.
And S104, welding the prepared upper packaging structure above the middle packaging structure to form a second packaging cavity for containing a second chip.
In this embodiment, the second metal surrounding frame 28 of the upper package structure is welded to the back metal surrounding frame 23 of the middle package structure, and laser welding may be adopted to ensure the air tightness of the package housing.
Fig. 3 to fig. 17 are schematic structural diagrams corresponding to respective steps in another process flow for manufacturing a packaged device according to an embodiment of the present application.
First, a first through hole 2 is prepared on a first ceramic substrate 1 on a lower package structure, wherein the first through hole 2 penetrates through the upper surface and the lower surface of the first ceramic substrate 1. The cross-sectional view of the first ceramic substrate 11 after the first through-hole 2 is formed can be seen in fig. 3, and the top view of the first ceramic substrate 1 after the first through-hole 2 is formed can be seen in fig. 4, which is the same as step S101.
In this embodiment, the lower package structure is prepared in advance, the first ceramic substrate 1 in the lower package structure is sintered in advance, when the first through hole 2 is prepared on the first ceramic substrate 1, a picosecond cold laser machining drilling process may be adopted, and the processed first through hole 2 penetrates through the upper surface and the lower surface of the first ceramic substrate 1. The hole wall of the first through hole 2 prepared in the manner is smooth and has high verticality, the difference value of the hole diameters of the front surface and the back surface of the first ceramic substrate 1 is less than 5%, the metal slurry is injected into the first through hole 2 in the subsequent process to serve as a signal transmission line, and the transmission loss can be reduced after the metal slurry is injected into the first through hole 2 prepared in the manner.
Secondly, depositing metal on the upper surface of the first ceramic substrate 1 and the inner side wall of the first through hole 2 to form a first front seed layer 3, reserving a first metal enclosure frame 10 on the upper surface of the first ceramic substrate 1, and preparing the first metal enclosure frame 10 on the first front seed layer 3 by an electrochemical deposition method, which can be specifically shown in fig. 5.
In the present embodiment, the first ceramic substrate 1 and the first via hole 2 are subjected to a cleaning process before the first front side seed layer 3 is deposited. The first front seed layer 3 is deposited on the front surface of the first ceramic substrate 1 by physical vapor deposition or chemical vapor deposition. Of course, the thickness of the first front-side seed layer 3 may be set and the first front-side seed layer 3 may be set in other ways as needed.
In this embodiment, a position where the first chip 11 is disposed may be reserved on the first front-side seed layer 3. The first chip 11 may be disposed at a position where the first chip 11 is reserved.
Thirdly, injecting metal into the first through hole 2 of the first ceramic substrate 1 provided with the first front-side seed layer 3 to form a first metal column 5 penetrating through the upper surface and the lower surface of the first ceramic substrate 1.
In practical application, the first front-side conductor layer 6 can be prepared on the first front-side seed layer 3 while injecting metal into the first through hole 2. As shown with particular reference to fig. 6-10.
Preparing a first front conductor layer 6 on the first front seed layer 3 by an electrochemical deposition method, wherein a first area of the first front conductor layer 6 is used for preparing a first metal enclosure frame 10, a second area of the first front conductor layer 6 is used for surface mounting of a first chip 11 to be packaged, and a third area of the first front conductor layer 6 is used for thickening the conduction column and a signal shielding structure at the periphery of the conduction column.
If the first front-side conductor layer 6 needs to be prepared, correspondingly, the step of preparing the first metal enclosure frame 10 on the first front-side seed layer 3 by an electrochemical deposition method, where the step of preparing the first metal enclosure frame 10 is reserved on the upper surface of the first ceramic substrate 1, includes:
and preparing a first metal enclosing frame 10 on a first area of the first front conductor layer 6 by an electrochemical deposition method at a position where the first metal enclosing frame 10 is reserved on the upper surface of the first ceramic substrate 1.
In the embodiment of the present application, the specific method for preparing the first front-side conductor layer 6 and the first metal stud 5 is as follows: coating a first photoresist layer 4 on the first front-side seed layer 3 by spin coating or film-coating hot pressing, then performing standard photolithography processes such as exposure and development on the position of the first photoresist layer 4 where the first front-side conductor layer 6 is to be prepared to obtain a conductor layer through hole for preparing the first front-side conductor layer 6, finally depositing metal in the position of the conductor layer through hole on the first photoresist layer 4 and the first through hole 2 of the first ceramic substrate 1 on which the first front-side seed layer 3 is deposited by an electrochemical deposition method, wherein the metal in the first through hole 2 is higher than the first through hole 2, the metal filled in the first through hole 2 is marked as a first metal column 5, and finally removing the first photoresist layer 4 to obtain the first front-side conductor layer 6 on the first front-side seed layer 3 and above the first metal column 5. The metal slurry filling during the preparation of the first front conductor layer 6 and the first metal column 5 adopts an electroplating method, and the combination of pulse plating and direct current plating is adopted during electroplating, so that the efficiency can be improved under the condition that no cavity exists in copper deposition in the first through hole 2.
The material of the first photoresist layer 4 can be high-viscosity photoresist or high-resolution photosensitive dry film, and the first photoresist layer 4 satisfies the constraint condition: the thickness is larger than 15 microns, the line resolution is smaller than 10 microns, and the inner side wall of the conductor layer through hole obtained after the first photoresist layer 4 is exposed is steep.
After the first front-side conductor layer 6 is prepared, in order to obtain the first front-side conductor layer 6 with a preset thickness and also in order to obtain the first front-side conductor layer 6 with higher precision and lower surface roughness, thickness reduction and surface treatment can be performed on the first front-side conductor layer 6.
Specifically, during the manufacturing process, the first front-side conductor layer 6 may be thinned, and during the grinding process, there may be some scratches, and the first front-side conductor layer 6 needs to be polished to reduce the surface roughness of the first front-side conductor layer 6. When the first photoresist layer 4 needs to be preserved for manufacturing the metal enclosure frame conveniently, the surface of the first photoresist layer 4 is ground and polished to reduce the surface roughness, and the transmission loss of the packaging device can be reduced when the packaging device is used through the grinding and polishing.
Fourthly, preparing the copper heat-conducting columns 9 at the positions where the copper heat-conducting columns 9 are reserved on the back surface of the first ceramic substrate 1, wherein the positions where the copper heat-conducting columns 9 are reserved comprise: the back surface of the first ceramic substrate 1 corresponds to the position of the first metal stud 5, as shown in fig. 8-10.
The preparation method of the copper heat conduction column 9 comprises the following steps: coating a fifth photoresist layer 8 on the back surface of the first ceramic substrate 1, photoetching a copper heat conduction column 9 pattern on the fifth photoresist layer 8, filling metal in the copper heat conduction column 9 pattern, and finally stripping the fifth photoresist layer 8 to obtain the copper heat conduction column 9.
Specifically, when making, can carry out the attenuate to copper heat conduction post 9, at the in-process of grinding treatment, probably can have some mar, still need continue to carry out polishing treatment to copper heat conduction post 9 to reduce copper heat conduction post 9 roughness. The Z-phase height of the copper heat conduction column 9 is controlled within + -5 μm after grinding and polishing.
And fifthly, removing the first front seed layer 3 except the position corresponding to the first front conductor layer 6 on the first ceramic substrate 1.
In this embodiment, the method of removing the first front side seed layer 3 may be a chemical etching method. If the first front-side seed layer 3 adopts copper, the copper is removed by using acid etching solution; if titanium is used for the first front-side seed layer 3, it is removed by an oxide etching liquid.
Of course, in practical applications, if the first front-side conductor layer 6 is not fabricated, the first front-side seed layer 3 in the area for preparing the first metal enclosure frame 10, the area for surface-mounting the first chip 11 to be packaged, and the area other than the area for thickening the conductive via and the signal shielding structure at the periphery of the conductive via may be removed, as shown in fig. 11.
Sixthly, the first metal enclosure is welded to the first front conductor layer 6 at a position where the first metal enclosure frame 10 is reserved on the upper surface of the first ceramic substrate 1, as shown with reference to fig. 11. The upper surface of the first metal surrounding frame 10 may be further provided with a first engaging bump.
If the first front side conductor layer 6 is provided, the first metal enclosure frame 10 is welded to the first front side conductor layer 6.
In this embodiment, the first metal frame 10 is used as a sidewall of a packaged device, and when the first metal frame 10 is prepared, the first metal frame 10 prepared in advance may be reinforced on the first ceramic substrate 1, or may be formed by a semiconductor process: for example, the photoresist at the position where the first metal enclosure frame 10 is reserved on the first ceramic substrate 1 is removed by photolithography, and the photoresist is left in other regions of the first ceramic substrate 1; the first metal enclosure frame 10 can also be prepared by an electroplating method at a position where the first metal enclosure frame 10 is reserved on the surface of the first ceramic substrate 1. Of course, in practical applications, the first metal frame 10 may be prepared in other manners, for example, the first metal frame 10 may be prepared by an electrochemical deposition method. The first metal enclosure frame 10 is directly grown on the first ceramic substrate 1, the height of the first metal enclosure frame 10 is controllable, the height of the first metal enclosure frame 10 is precisely matched with the frequency of the first chip 11, the spatial coupling degree is controllable, and the radio frequency characteristic of the first chip 11 is improved.
In this embodiment, during actual manufacturing, the upper surface of the first metal enclosure frame 10 may also be thinned, during the grinding process, there may be some scratches, and it is further necessary to continue to perform a polishing process on the upper surface of the first metal enclosure frame 10 to reduce the surface roughness. In the present embodiment, the spatial coupling degree of the hermetically packaged device can be reduced by precisely controlling the height of the first metal enclosure 10 through electroplating thickening and CMP thinning processes.
Seventh, after preparing the copper heat conduction post 9 at the position where the copper heat conduction post 9 is reserved on the back surface of the first ceramic substrate 1, in order to improve the environmental resistance of the hermetically packaged device, a solder resist layer 13 is prepared on the back surface of the first ceramic substrate 1 and on other areas except the position where the copper heat conduction post 9 is reserved by using a nickel-gold electroless plating method, as shown in fig. 11.
Eighthly, mounting the first chip 11 to be packaged inside the first metal enclosure frame 10 on the first ceramic substrate 1, and leading out a pad of the first chip 11 to be packaged and the first metal column 5 on the first ceramic substrate 1 through a bonding wire, as shown in fig. 12.
In this embodiment, the first metal pillar 5 connected to the pad of the first chip 11 is referred to as a conductive pillar, and a signal shielding structure formed by a circle of the first metal pillar 5 is further disposed on the periphery of the conductive pillar.
Since the conductive via needs to transmit a signal, a signal shielding structure needs to be provided for the conductive via. The signal shielding structure in the present application may be configured as follows: when the first through hole 2 corresponding to the first conductive via is prepared, a circle of the first through hole 2 is prepared at the periphery of the first through hole 2, metal is also injected into the circle of the first through hole 2 to form a first metal column 5, and the first metal column 5 surrounding the conductive via can form a signal shielding structure.
By adopting the mode, the signal shielding structure does not need to be additionally prepared, and the conducting column is manufactured together when being prepared, so that the process cost is saved.
In this embodiment of the application, when the number of the first chips 11 to be packaged is at least two, and the first chips 11 to be packaged need to be isolated from each other, a first isolation wall 14 is further disposed in the first metal enclosure frame 10, the first chips 11 to be isolated are located in different airtight spaces, and the airtight spaces are isolated from each other by the first isolation wall 14. The first chips 11 are separated by the first separation walls 14, so that the first chips 11 do not interfere with each other.
The ninth preparation method of the middle packaging structure comprises the following steps:
and preparing a second through hole 16 on the second ceramic substrate 12 on the intermediate packaging structure, wherein the second through hole 16 penetrates through the upper surface and the lower surface of the second ceramic substrate 12. The specific preparation method is as shown in the preparation method of the first through hole 2 in the first embodiment.
And depositing metal on the upper surface of the second ceramic substrate 12 and the inner side wall of the second hole to form a second front seed layer 17, and depositing metal on the lower surface of the second ceramic substrate 12 to form a second back seed layer 18. The specific preparation method refers to the preparation method of the first front-side seed layer 3 in the second embodiment, as shown in fig. 13.
And injecting metal into the second through hole 16 of the second ceramic substrate 12 provided with the second front-side seed layer 17 to form a second metal column penetrating through the upper surface and the lower surface of the second ceramic substrate 12. See in particular the method for making the first metal pillar 5 in the third embodiment. The second front side conductor layer 19 and the second back side conductor layer 20 can also be prepared together when preparing the second metal pillar. An isolation layer may also be prepared on the lower surface of the second ceramic substrate 12 or the second back conductor layer 20. The specific preparation method of the isolation layer is to deposit a second photoresist layer on the back of the second ceramic substrate 12, etch an isolation layer pattern on the second photoresist layer, deposit metal in the isolation layer pattern, and finally strip the second photoresist layer to obtain the isolation layer, as shown in fig. 14.
A front metal surrounding frame 22 is prepared on the second front conductor layer 19, and a back metal surrounding frame 23 is prepared on the second back conductor layer 20, and the specific preparation method refers to the preparation method of the first metal surrounding frame 10 in the sixth embodiment. The upper surface of the front metal surrounding frame 22 is provided with front engaging protrusions, and the lower surface of the back metal surrounding frame 23 is provided with back engaging protrusions matched with the front engaging protrusions, as shown in fig. 16.
And removing the second front-side seed layer 17 except the position corresponding to the second front-side conductor layer 19 on the second ceramic substrate 12. And removing the second back seed layer 18 except the position corresponding to the second back conductor layer 20 under the second ceramic substrate 12. Specifically, reference may be made to a fifth method for removing the first front surface seed layer 3, as shown in fig. 15.
And mounting a second chip to be packaged in the front metal enclosure frame 22 on the second ceramic substrate 12, and leading out a pad of the second chip to be packaged and a second metal column on the second ceramic substrate 12 through a bonding wire. In this embodiment, when the number of the second chips to be packaged is at least two, and the second chips to be packaged need to be isolated, the second metal enclosure frame 28 is further provided with a first isolation wall, the second chips to be isolated are located in different airtight spaces, and the airtight spaces are isolated by the second isolation wall. And the second chips are separated by adopting a second isolation wall, so that the second chips are not interfered with each other.
Tenth, a method for manufacturing the upper package structure, as shown in fig. 17:
and depositing a third back seed layer on the lower surface of the cover plate 24 in the upper packaging structure, and arranging the third back seed layer below the third back seed layer to prepare a third back conductor layer 26, wherein the first area of the lower surface of the third back conductor layer 26 is used for preparing a second metal enclosure frame 28. The lower surface of the second metal surrounding frame 28 is provided with a second engaging bump matched with the front engaging bump.
For details, please refer to the preparation methods of the first front-side seed layer 3 and the first front-side conductor layer 6, which are not described herein again.
The second metal surrounding frame 28 is prepared under the third back conductor layer 26, and the specific preparation method refers to the preparation method of the first metal surrounding frame 10 in the sixth embodiment, which is not described herein again.
In practical application, a shielding layer may be further fabricated on the back surface of the cover plate 24, and the specific fabrication method of the shielding layer is the same as that of the isolation layer in the ninth embodiment, and is not described herein again.
In order to make the manufacturing process of the cap plate 24 the same as the manufacturing process of the first ceramic substrate 1, a through hole of the cap plate 24 may be formed in the cap plate 24, and a metal may be filled in the through hole of the cap plate 24 to form a third metal pillar. The process can be simplified and the cover plate 24 can be manufactured one by one when the first ceramic substrate 1 is manufactured.
Eleventh, the middle package structure is welded above the lower package structure, and a second metal pillar connected to a second chip is connected to the first chip 11 through a conductive structure 15, so as to form a first package cavity for accommodating the first chip 11.
As shown in fig. 1, please refer to S103 specifically.
And twelfth, welding the prepared upper packaging structure above the middle packaging structure to form a second packaging cavity for containing a second chip.
As shown in fig. 1, please refer to S104 specifically.
Of course, in practical applications, heat dissipation fins may also be fabricated on the front surface of the cover plate 24 before the upper package structure is sealed with the middle package structure.
Specifically, the method for manufacturing the heat dissipation fin includes the steps of manufacturing a third photoresist layer on the front surface of the cover plate 24 in a spin coating or film-coating hot pressing mode, etching through holes for manufacturing the heat dissipation fin on the third photoresist layer, depositing metal on the positions of the through holes for manufacturing the heat dissipation fin etched on the third photoresist layer, and removing the third photoresist layer to obtain the heat dissipation fin.
In a specific application, when the heat dissipation fin is manufactured, the bottom of the first chip 11 is connected to the first metal enclosure 10, the bottom of the second chip is connected to the front metal enclosure 22, if the first chip 11 is manufactured on the first front seed layer 3, the first front seed layer 3 under the first chip 11 is connected to the first metal enclosure 10, heat is transferred to the metal enclosure through the first front seed layer 3, and the heat is transferred upwards to the heat dissipation fin through the metal enclosure. If the first chip 11 is fabricated on the first front side conductor layer 6, the metal enclosure frame may be connected through the first front side conductor layer 6 and the first front side seed layer 3 under the first chip 11, or the first front side seed layer 3 may be connected to the metal enclosure frame. The second chip is also the same.
In an embodiment of the present invention, before the cover plate 24 is sealed on the upper surface of the metal enclosure, an antenna may be further fabricated on the front surface of the cover plate 24.
Specifically, the method for manufacturing the antenna includes manufacturing a fourth photoresist layer on the front surface of the cover plate 24 by spin coating or film-coating hot pressing, etching a pattern for manufacturing the antenna on the fourth photoresist layer, depositing metal on the position of the pattern for manufacturing the antenna etched on the fourth photoresist layer, and removing the fourth photoresist layer to obtain the antenna.
In specific application, when the antenna is manufactured, a picosecond cold laser machining drilling hole can be adopted on the cover plate 24, a through hole of the cover plate 24 is machined, metal is deposited in the through hole of the cover plate 24, the metal in the through hole of the cover plate 24 is marked as a metal column of the cover plate 24, and the antenna is connected with the metal column of the cover plate 24 in the through hole of the cover plate 24.
Correspondingly, spring columns are also arranged in the first packaging cavity and the second packaging cavity, and one ends of the spring columns in the first packaging cavity are connected with the first chip 11 through welding, or connected with the first front-side seed layer 3 or the first front-side conductor layer 6 below the first chip 11; the other end of the spring column is connected with the second metal column. One end of the spring column in the second packaging cavity is connected with the second chip through welding, or is connected with a second front seed layer 17 or a second front conductor layer 19 below the second chip; the other end of the spring post is connected to the cover plate 24 metal post.
In practical applications, the first coupling structure 21 may also be disposed on the lower surface of the second ceramic substrate 12 above the first chip 11, and the first coupling structure 21 may be a planar structure or a stepped structure. Above the second chip, the lower surface of the cover plate 24 is provided with a second coupling structure, which may be a planar structure or a stepped structure.
In practical application, the air tightness of the airtight packaging structure can be further verified, and whether the airtight packaging structure is qualified or not is further judged.
Specifically, the hermetic package structure is placed in a leak-tight vessel, which is filled with helium and pressurized at 0.5 Mpa. And after 4 hours, taking out the airtight packaging structure, performing rough detection by adopting a leakage detection liquid soaking method, and if no bubble is generated on the surface of the leakage detection liquid, determining that the airtight packaging structure is qualified, otherwise, determining that the airtight packaging structure is not qualified. And finally, performing fine inspection on the qualified airtight packaging structure by using a helium mass spectrometer, and if the leak detector shows that the helium flow is lower than 1 × 10-9pa.cm < 3 >/s, the airtight packaging structure is qualified, otherwise, the airtight packaging structure is not qualified.
The steps in the above first to eleventh may be deleted or recombined according to actual needs.
It should be noted that, in the above embodiment, the first front-side seed layer 3 and the first front-side conductor layer 6 are both disposed on the first ceramic substrate 1, in practical application, a first back-side seed layer may also be disposed on the back side of the first ceramic substrate 1, and the copper heat conduction pillars 9 are prepared at positions where the copper heat conduction pillars 9 are reserved under the first back-side seed layer, and the specific steps are the same as those of the step of preparing the first front-side seed layer 3.
The first back conductor layer 7 may also be disposed under the first back seed layer, and the first back conductor layer 7 may be obtained by depositing a first lower photoresist layer under the first back seed layer, and then performing photolithography, deposition and the like on the first lower photoresist layer, and the specific steps are the same as those of the step of preparing the first front conductor layer 6. And preparing the copper heat-conducting column 9 at the position of the copper heat-conducting column 9 reserved under the first back conductor layer 7.
A third front-side seed layer 25 and a third front-side conductor layer 27 may also be prepared on the upper surface of the cap plate 24.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
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| CN118588652A (en) * | 2024-06-27 | 2024-09-03 | 睿思微系统(烟台)有限公司 | Chip isolation packaging structure and method |
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| US6528875B1 (en) * | 2001-04-20 | 2003-03-04 | Amkor Technology, Inc. | Vacuum sealed package for semiconductor chip |
| KR20040107198A (en) * | 2003-06-13 | 2004-12-20 | 삼성전기주식회사 | A slim type crystal oscillator |
| US20070002521A1 (en) * | 2005-06-29 | 2007-01-04 | Masahiro Kimura | Ceramic structure, method for manufacturing ceramic structure, and nonreciprocal circuit device |
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| CN118588652A (en) * | 2024-06-27 | 2024-09-03 | 睿思微系统(烟台)有限公司 | Chip isolation packaging structure and method |
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