CN111026501A - Host computer graphics command generation and graphics processor command analysis joint simulation platform - Google Patents
Host computer graphics command generation and graphics processor command analysis joint simulation platform Download PDFInfo
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- CN111026501A CN111026501A CN201911147114.8A CN201911147114A CN111026501A CN 111026501 A CN111026501 A CN 111026501A CN 201911147114 A CN201911147114 A CN 201911147114A CN 111026501 A CN111026501 A CN 111026501A
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
- G06F9/45508—Runtime interpretation or emulation, e g. emulator loops, bytecode interpretation
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
- G06F9/45516—Runtime code conversion or optimisation
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Abstract
The invention belongs to the technical field of computer application, and particularly relates to a host graphics command generation and graphics processor command analysis joint simulation platform. The method comprises the following steps: the simulation system comprises a host computer graphic command generation module, a command analysis unit assembly drive analysis module, a graphic processor command analysis unit simulator modeling module, a command analysis unit execution simulation module and a simulation result verification module. The invention aims at command generation, analysis, modeling and simulation of the graphics processor, and efficiently and intuitively verifies the generation of the host graphics command and the analysis and processing correctness and completeness of the graphics processor command analysis unit before the design is finished and the hardware is realized by combining the generation and the analysis of the simulation graphics command, thereby laying a good foundation for the hardware realization and the verification.
Description
Technical Field
The invention belongs to the field of computer graphics, and particularly relates to a host graphics command generation and graphics processor command analysis joint simulation platform.
Background
The generation and the analysis of the graphics commands are key modules in the processing process of a Graphics Processing Unit (GPU), and the generation, the transmission and the analysis correctness and the processing rate of the graphics commands determine the drawing correctness and the execution efficiency of the GPU. However, since the generation and the parsing of the graphics commands are respectively completed by the host and the GPU device, the verification of each graphics command can only be performed before the GPU design is completed, and the accuracy and efficiency of the joint execution cannot be guaranteed.
Disclosure of Invention
The purpose of the invention is:
the invention provides a host computer graphic command generation and graphic processor command analysis joint simulation platform, which aims at the command generation, analysis, modeling and simulation of a graphic processor.
The specific scheme of the invention is as follows:
the invention provides a host graphical command generation and graphics processor command analysis joint simulation platform, which comprises a host graphical command generation module, a command analysis unit assembly drive analysis module, a graphics processor command analysis unit simulator modeling module, a command analysis unit execution simulation module and a simulation result verification module; the simulation platform receives OpenGL drawing commands and assembly drive, generates an execution structure tree through simulator modeling, finally obtains simulation results through simulation execution and compares the simulation results with expectation, and verifies the correctness of the host graphics command generation and graphics processor command analysis process.
Preferably: the host graphics command generation module is used for receiving the OpenGL drawing command, judging command state and parameter validity, generating a command data packet according to command type and storing the data packet in a command buffer Ringbuffer, and completing conversion from the OpenGL drawing command to the data packet.
Preferably: the command analysis unit assembly drive analysis module is used for receiving the assembly drive, performing drive lexical analysis and syntactic analysis according to the custom assembly designated programming model, generating an assembly drive execution structure tree and completing the conversion from the assembly drive to the drive execution structure tree.
Preferably: the graphic processor command analysis unit simulator modeling module is used for modeling simulation facing a graphic processor command analysis unit, comprises 4 parts of instruction modeling, execution unit modeling, storage system modeling and execution simulation, and carries out value decoding, scheduling, execution and data write-back according to an execution model on the basis of the instruction, the execution unit and the storage system modeling so as to complete the modeling of resources and an execution process of the command analysis unit.
Preferably: the command analysis unit execution simulation module is used for receiving command packet data generated by the host graphics command generation module, a driving execution structure tree generated by the command analysis unit assembly driving analysis module and an execution model generated by the graphics processor command analysis unit simulator modeling module, and executing simulation according to the driving execution structure tree by loading the execution model and the command packet data to complete the execution of graphics processor command analysis and simulation, wherein the execution result comprises a command code sending and a write-back storage system class 2.
Preferably: the simulation result verification module is used for comparing the command code generated by the command analysis unit executing simulation module and the write-back data with an expected value, verifying whether the sent command code is consistent with the expected value or not, verifying whether the value written back to the storage system is correct or not, and determining the correctness of the host graphics command generation and graphics processor command analysis processes.
The invention provides a host graphics command generation and graphics processor command analysis joint simulation platform, which aims at command generation, analysis, modeling and simulation of a graphics processor, efficiently and intuitively verifies the generation of the host graphics command and the analysis and processing correctness and completeness of a graphics processor command analysis unit before design completion and hardware realization through the generation and analysis of a joint simulation graphics command, and lays a good foundation for hardware realization and verification.
Drawings
FIG. 1 is a block diagram of a method of the present invention;
wherein: 1. a host graphics command generation module; 2. the command analysis unit assembles a driving analysis module; 3. the graphic processor command analysis unit simulator modeling module; 4. the command analysis unit executes the simulation module; 5. and a simulation result verification module.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The technical scheme of the invention is further described in detail by combining the drawings and the specific embodiments in the specification.
In an embodiment of the present invention, as shown in fig. 1, the present invention provides a host graphics command generation and graphics processor command parsing joint simulation platform, which includes a host graphics command generation module 1, a command parsing unit assembly drive parsing module 2, a graphics processor command parsing unit simulator modeling module 3, a command parsing unit execution simulation module 4, and a simulation result verification module 5; the simulation platform receives OpenGL drawing commands and assembly drive, generates an execution structure tree through simulator modeling, finally obtains simulation results through simulation execution and compares the simulation results with expectation, and verifies the correctness of the host graphics command generation and graphics processor command analysis process.
In one embodiment, the host graphics command generating module 1 is configured to receive an OpenGL graphics command, determine a command status and validity of parameters, generate a command packet according to a command type, store the command packet in a command buffer Ringbuffer, and complete conversion from the OpenGL graphics command to the command packet.
In an embodiment, the command parsing unit assembly driver parsing module 2 is configured to receive an assembly driver, perform driven lexical analysis and syntactic analysis according to a custom assembly specified programming model, generate an assembly driver execution structure tree, and complete conversion from the assembly driver to the driver execution structure tree.
In one embodiment, the graphics processor command parsing unit simulator modeling module 3 is used for modeling simulation facing the graphics processor command parsing unit, and includes 4 parts of instruction modeling, execution unit modeling, storage system modeling and execution simulation.
In one embodiment, the command parsing unit execution simulation module 4 is configured to receive the command packet data generated by the host graphics command generating module 1, the driver execution structure tree generated by the command parsing unit assembly driver parsing module 2, and the execution model generated by the graphics processor command parsing unit simulator modeling module 3, and perform simulation according to the driver execution structure tree by loading the execution model and the command packet data, so as to complete execution of graphics processor command parsing and simulation, where the execution result includes sending a command code and writing back to the storage system 2 class.
In one embodiment, the simulation result verification module 5 is configured to compare the command code generated by the command parsing unit executing the simulation module 4 and the written-back data with an expected value, verify whether the sent command code is consistent with the expected value, verify whether the value written back to the storage system is correct, and determine correctness of the host graphics command generation and graphics processor command parsing process.
Claims (6)
1. A host graphics command generation and graphics processor command parsing joint simulation platform, characterized by: the platform comprises a host graphics command generation module (1), a command analysis unit assembly drive analysis module (2), a graphics processor command analysis unit simulator modeling module (3), a command analysis unit execution simulation module (4) and a simulation result verification module (5); the simulation platform receives OpenGL drawing commands and assembly drive, generates an execution structure tree through simulator modeling, finally obtains simulation results through simulation execution and compares the simulation results with expectation, and verifies the correctness of the host graphics command generation and graphics processor command analysis process.
2. The host graphics command generation and graphics processor command parsing co-simulation platform of claim 1, wherein: the host graphics command generation module (1) is used for receiving the OpenGL drawing command, judging command state and parameter validity, generating a command data packet according to command type and storing the data packet in a command buffer Ringbuffer, and completing conversion from the OpenGL drawing command to the data packet.
3. The host graphics command generation and graphics processor command parsing co-simulation platform of claim 2, wherein: the command analysis unit assembly drive analysis module (2) is used for receiving assembly drive, performing drive lexical analysis and syntactic analysis according to a custom assembly designated programming model, generating an assembly drive execution structure tree, and completing conversion from the assembly drive to the drive execution structure tree.
4. The host graphics command generation and graphics processor command parsing co-simulation platform of claim 3, wherein: the graphic processor command analysis unit simulator modeling module (3) is used for modeling simulation facing a graphic processor command analysis unit, comprises 4 parts of instruction modeling, execution unit modeling, storage system modeling and execution simulation, and carries out value decoding, scheduling, execution and data write-back according to an execution model on the basis of the instruction, the execution unit and the storage system modeling so as to complete the modeling of resources and an execution process of the command analysis unit.
5. The host graphics command generation and graphics processor command parsing co-simulation platform of claim 4, wherein: the command analysis unit execution simulation module (4) is used for receiving command packet data generated by the host graphics command generation module (1), a driving execution structure tree generated by the command analysis unit assembly driving analysis module (2) and an execution model generated by the graphics processor command analysis unit simulator modeling module (3), executing simulation according to the driving execution structure tree by loading the execution model and the command packet data, and completing the execution of graphics processor command analysis and simulation, wherein the execution result comprises a command code sending and a write-back storage system 2 type.
6. The host graphics command generation and graphics processor command parsing co-simulation platform of claim 5, wherein: the simulation result verification module (5) is used for comparing the command code and the write-back data generated by the command analysis unit execution simulation module (4) with an expected value, verifying whether the sent command code is consistent with the expected value, verifying whether the value written back to the storage system is correct, and determining the correctness of the host graphics command generation and graphics processor command analysis process.
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| US20100214301A1 (en) * | 2009-02-23 | 2010-08-26 | Microsoft Corporation | VGPU: A real time GPU emulator |
| CN103970941A (en) * | 2014-04-23 | 2014-08-06 | 昆明理工大学 | Scattered bamboo rhizome parallel analog simulation method based on network cluster |
| CN104460670A (en) * | 2014-11-10 | 2015-03-25 | 华南理工大学 | SCARA robot motion simulation and remote control system and method |
| CN109669832A (en) * | 2018-12-11 | 2019-04-23 | 中国航空工业集团公司西安航空计算技术研究所 | One kind is towards GPU graphics chip pipeline unit performance verification method and platform |
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2019
- 2019-11-21 CN CN201911147114.8A patent/CN111026501A/en active Pending
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| US20100214301A1 (en) * | 2009-02-23 | 2010-08-26 | Microsoft Corporation | VGPU: A real time GPU emulator |
| CN103970941A (en) * | 2014-04-23 | 2014-08-06 | 昆明理工大学 | Scattered bamboo rhizome parallel analog simulation method based on network cluster |
| CN104460670A (en) * | 2014-11-10 | 2015-03-25 | 华南理工大学 | SCARA robot motion simulation and remote control system and method |
| CN109669832A (en) * | 2018-12-11 | 2019-04-23 | 中国航空工业集团公司西安航空计算技术研究所 | One kind is towards GPU graphics chip pipeline unit performance verification method and platform |
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Application publication date: 20200417 |