CN111026233A

CN111026233A - A high-speed parallel data receiving system based on clock driver and FPGA

Info

Publication number: CN111026233A
Application number: CN201911130076.5A
Authority: CN
Inventors: 倪建军; 富帅; 刘涛; 宋博; 荣鹏; 于双江; 王磊; 闫静纯; 王�华; 薄姝; 蔡帅; 苏浩航; 顾晨跃; 申一伟
Original assignee: Beijing Research Institute of Mechanical and Electrical Technology
Current assignee: Beijing Research Institute of Mechanical and Electrical Technology
Priority date: 2019-11-18
Filing date: 2019-11-18
Publication date: 2020-04-17
Anticipated expiration: 2039-11-18
Also published as: CN111026233B

Abstract

The invention discloses a high-speed parallel data receiving system based on a clock driver and an FPGA, comprising a clock driver, an FPGA and a radio frequency ADC. The quantized data output of the RF ADC is parallel LVDS, and the ADC output is divided into 2 (not less than 2) with the clock through the clock driver 1. After the clock driver, each separate clock signal is unified with each group of data signals of the high-speed ADC. Input into the same BANK of FPGA, use the Iserdes (input serial-to-parallel converter) primitive in the FPGA to receive high-speed parallel data. The present invention solves the difficulties encountered in high-speed parallel data reception of the FPGA by introducing a clock driver to create a "pseudo" clock and utilizing the Iserdes (input serial-to-parallel converter) primitive in the FPGA.

Description

High-speed parallel data receiving system based on clock driver and FPGA

Technical Field

The invention relates to the technical field of laser radar echo signal full-waveform acquisition, in particular to a high-speed parallel data receiving system based on a clock driver and an FPGA.

Background

The laser radar is an active remote sensing technology, the pulse width of laser emission is in ns level, the echo of the full-waveform laser radar carries the distance and characteristic information of a detected target, the pulse is narrow, and a very high sampling rate is needed during full-waveform recording.

The full-waveform laser radar performs digital quantization on the laser main echo signal by using a GHz sampling rate ADC. The detection of effective echo is realized after the full waveform data is processed, the current radio frequency ADC chip is high in quantization digit and large in data bandwidth and is limited by pins, working frequency and the like of a part of FPGA devices, and for the ADC devices with GHz sampling rate, high quantization digit and parallel LVDS (Low Voltage differential Signaling) digital output, the FPGA cannot reliably realize data receiving by adopting a data receiving scheme of a global clock, and cannot realize cross-BANK data acquisition operation by adopting a local clock. A new system is needed to solve the technical difficulties encountered at present, and the method has important significance for the data acquisition of the full-waveform laser radar.

Disclosure of Invention

The purpose of the invention is: the system overcomes the defects of the prior art, provides a high-speed parallel data receiving system based on a clock driver and an FPGA, and solves the problem that multi-path LVDS parallel data receiving of Iserdes (input serial-parallel converter) elements cannot be directly adopted under the working frequency limitation of part of FPGA high-speed data receiving and the limited constraint of BANK pins, so that the reliable receiving of the high-speed parallel data is realized.

The above object of the present invention can be achieved by the following means: a high-speed parallel data receiving system based on a clock driver and an FPGA comprises: the radio frequency ADC, the clock driver and the FPGA;

VinI +/-and VinQ +/-of the radio frequency ADC are differential signal input ends, digital signals and associated clock signals DCLKI +/-and DCLKQ +/-are respectively output after digital quantization of the ADC of an internal I channel ADC and the ADC of a Q channel, and differential data signals DI +/-11.0 and DId +/-11.0 are respectively output by data signals of the I channel through an internal data bit expansion module; the data signal of the Q channel respectively outputs differential data signals DQ +/- <11..0> and DQd +/- <11..0> through an internal data bit expansion module;

the clock driver 1 receives a differential accompanying clock DCLKI +/-, which is output by the radio frequency ADC, outputs 4 paths of differential clocks DCLKI1+/-, DCLKI2+/-, DCLKI3+/-, and DCLKI4+/-, and the clock driver 2 receives the differential accompanying clock DCLKQ +/-, which is output by the radio frequency ADC, outputs 4 paths of differential clocks DCLKQ1+/-, DCLKQ2+/-, DCLKQ3+/-, and DCLKQ4 +/-; the 8 paths of differential clocks are connected to the regional clock pins of the FPGA;

data DI <11..0> +/-, a clock DCLKI1+/-, which is output by a clock driver 1, and a clock DCLKQ3, which is output by a clock driver 2, are input into the same BANK of the FPGA; data DId <11..0> +/-, a clock DCLKI2+/-, which is output by a clock driver 1, and a clock DCLKQ4, which is output by a clock driver 2, are input into the same BANK of the FPGA as a group; data DQ <11..0> +/-, which are output by the radio frequency ADC, a clock DCLKI3+/-, which is output by the clock driver 1, and a clock DCLKQ1, which is output by the clock driver 2, are combined into a group and input into the same BANK of the FPGA; data DQd <11..0> +/-, a clock DCLKI2+/-, which is output by a clock driver 1, and a clock DCLKQ2, which is output by a clock driver 2, are input into the same BANK of the FPGA as a group; the FPGA is provided with Iserdes primitives, and serial data input and parallel data output are realized.

The radio frequency ADC quantizes the input differential signal and outputs a 12-bit digital signal, the 12-bit digital signal outputs 2 groups of 12-bit differential signals after passing through 1:2Demux, each bit of differential data signal realizes the conversion from high-speed serial data to low-speed parallel data through an Iserdes primitive in each BANK of the FPGA, each bit of differential data of each group of 12-bit data generates 48-bit data after being subjected to serial-parallel conversion according to 1:4 and is written into an FIFO, and when the FPGA outputs according to 1:2, the DI and DId of the FPGA respectively read the 48-bit data from the FIFO and convert the 48-bit data into 96-bit data; the operation of DQ and DQd of the FPGA is the same as DI and DId of the FPGA, when the radio frequency ADC is output according to 1:4 quantization, the radio frequency ADC is double-channel interleaved sampling, and the quantized associated clock can adopt DCLKI or DCLKQ to realize parallel LVDS data bit expansion processing according to the number combination in 4 BANKs.

The maximum sampling frequency of the radio frequency ADC is 1.6GHz, the quantization digit is 12 bits, and the radio frequency ADC supports single channels 1:1 and 1:2 and supports 1 under double-channel interleaved sampling: 4LVDS output.

The clock driver 1 has two differential clock inputs which can be selected, and 10 differential clock outputs are achieved.

The clock driver 2 has two differential clock inputs which can be selected, and 10 differential clock outputs are achieved.

Compared with the prior art, the invention has the advantages that:

(1) the invention creates a pseudo clock by introducing a clock driver and realizes the receiving of the multi-bit LVDS high-speed parallel data by utilizing an Iserdes primitive;

(2) according to the invention, a clock driver is introduced to create a pseudo clock, so that the problem that the operation of data cannot be realized across BANK by part of FPGA regional clocks is solved;

(3) the invention creates a pseudo clock by introducing a clock driver and can realize the cold backup design of high-speed data receiving by matching with a plurality of radio frequency ADCs;

drawings

FIG. 1 is a high-speed parallel LVDS data reception diagram of the present invention;

FIG. 2 is a schematic diagram of a clock driver;

FIG. 3 is a schematic diagram of Iserdes cell 1:4 data conversion;

fig. 4 is a schematic diagram of high-speed parallel LVDS data bit-expansion parallelization processing.

Detailed Description

The invention is described in further detail below with reference to the figures and specific embodiments.

As shown in fig. 1, the high-speed parallel data receiving system based on the clock driver and the FPGA provided by the invention includes a radio frequency ADC, a clock driver 1, a clock driver 2, and an FPGA.

The maximum sampling frequency of the radio frequency ADC is 1.6GHz, the quantization bit number is 12 bits, and the radio frequency ADC supports single channels 1:1 and 1:2 and supports 1 under double-channel interleaved sampling: 4LVDS output.

The clock driver 1 and the clock driver 2 have two-way differential clock input selectable, and 10-way differential clock output.

The FPGA (U4) has Iserdes primitives to implement serial data input and parallel data output.

The radio frequency ADC is a dual-channel high-performance analog-to-digital converter, the quantization output adopts an LVDS mode, as shown in fig. 1, VinI +/-and VinQ +/-of the radio frequency ADC are differential signal input ends, 12-bit digital signals and associated clock signals DCLKI +/-and DCLKQ +/-are respectively output after digital quantization of the ADC of the internal I channel ADC and the ADC of the Q channel, data streams and operations of the I channel and the Q channel are completely consistent, and the 12-bit data signal of the I channel respectively outputs differential data signals DI +/-11.0 and DId +/-11.0 through an internal data bit spreading module (1:2 Demux). The data signals of the Q channel pass through the internal data bit expansion module to output differential data signals DQ +/- <11..0> and DQd +/- <11..0> respectively.

The clock driver 1 receives a differential accompanying clock DCLKI +/-, which is output by the radio frequency ADC, outputs 4 paths of differential clocks DCLKI1+/-, DCLKI2+/-, DCLKI3+/-, and DCLKI4+/-, the clock driver 2 receives the differential accompanying clock DCLKQ +/-, which is output by the radio frequency ADC, outputs 4 paths of differential clocks DCLKQ1+/-, DCLKQ2+/-, DCLKQ3+/-, and DCLKQ4+/-, and the total 8 paths of clocks are connected to an area clock pin of the FPGA.

Data DI <11..0> +/-, a clock DCLKI1+/-, a clock DCLKQ3 and a clock driver 2 are inputted into the same BANK of the FPGA, data DId <11..0> +/-, a clock DCLKI2+/-, a clock driver 1 and a clock DCLKQ4 +/-are inputted into the same BANK of the FPGA, data DQ <11..0> +/-, a clock DCLKI3+/-, a clock DCLKQ1 and a clock DCLKQ1 are inputted into the same BANK of the FPGA, data DI DQd <11..0> +/-, a clock DCLKI2+/-, a clock driver 1 and a clock driver 2 are inputted into the same BANK of the FPGA, and data DCLKI2+/-, a clock driver 1 is inputted into the same BANK of the FPGA, The clock DCLKQ2 +/-output by the clock driver 2 is a set of inputs into the same BANK of the FPGA.

In the high-speed parallel data receiving system based on the clock driver and the FPGA, 12-bit digital signals are output after each sampling point is quantized, 2 groups of 12-bit differential signals are output after the 12-bit digital signals pass through 1:2Demux, and the conversion from high-speed serial data to low-speed parallel data is realized by passing each bit differential data signal through an Iserdes (input serial-parallel converter) element in each BANK of the FPGA; the operation of DQ and DQd of the FPGA is completely consistent with DI and DId of the FPGA, when the radio frequency ADC is quantized and output according to the ratio of 1:4, the radio frequency ADC is dual-channel interleaved sampling (namely two small ADCs inside the radio frequency ADC are synthesized into one for use), a quantized channel associated clock can adopt DCLKI or DCLKQ, the splicing processing mode of data is completely consistent with the ratio of 1:2, and the parallel LVDS data expanding processing is realized according to the combination of numbers in 4 BANKs.

The radio frequency ADC comprises 2 channels of ADCs, a single ADC can realize the highest sampling rate of 1.6Gsps, and 2 channels realize the highest sampling rate of 3.2Gsps through interleaved sampling. And (3) properly configuring a quantization output mode according to the working sampling rate of the radio frequency ADC, and when the sampling rate is more than 1GHz, the output of the radio frequency ADC can only be configured into an output mode of 1:2 or 1:4 due to the limitation of the working frequency of an FPGA interface. The high speed data receiving system emphasized by the present invention is also above 1GHz with a sampling rate, but is also applicable to sampling rates below 1 GHz. Meanwhile, as the principle of 1:2 and 1:4 data receiving is consistent, only the radio frequency ADC is detailed according to 1:2 output.

The radio frequency ADC can output in a mode of 1:1, 1:2, 1:4 and the like through setting, wherein 1:1 and 1:2 are realized by each small ADC in the radio frequency ADC, 1:4 is realized by 2 small ADC interleaved samples in the radio frequency ADC, the two small ADC interleaved samples can be combined into 1:4 output, and only one of DCLKI or DCLKQ can be used in a 1:4 mode, namely, the channel associated clock only has 1 channel no matter how the output mode is.

Data signals DI <11..0> +/-, DId <11..0> +/-, DQ <11..0> +/-, DQd <11..0> +/-output by the radio frequency ADC are connected with the FPGA; clock signals DCLKI +/-, DCLKQ +/-output by the radio frequency ADC are input into U2 and U3; the U2 and U3 output 4 clocks respectively, and are connected to local clock pins in different BANKs of the FPGA respectively. The data is received and processed by using Iserdes (input serial-parallel converter) primitives in the FPGA.

Fig. 2 is a schematic diagram of a clock driver, which can realize 1-way differential input and multiple-way differential signal output.

FIG. 3 is a schematic diagram of Iserdes cell 1:4 data conversion; the FPGA utilizes an Iserdes primitive to realize data receiving, data are written into an FIFO after being received according to the ratio of 1:2, the data are read out through the FIFO and then are spliced and input into the next stage, and FIG. 4 is a parallel LVDS data bit expansion parallelization processing schematic diagram.

The above description is only an embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.

Those skilled in the art will appreciate that those matters not described in detail in the present specification are well known in the art.

Claims

1. a high-speed parallel data receiving system based on clock driver and FPGA, is characterized in that, comprises: radio frequency ADC, clock driver, FPGA;

VinI+/- and VinQ+/- of the RF ADC are differential signal input terminals, which are digitally quantized by the internal I channel ADC and Q channel ADC respectively and output digital signals and accompanying clock signals DCLKI+/-, DCLKQ+/-. The data signal outputs differential data signals DI+/-<11..0> and DId+/-<11..0> respectively through the internal data expansion module; the data signal of Q channel respectively outputs differential data through the internal data expansion module Signals DQ+/-<11..0> and DQd+/-<11..0>;

The clock driver 1 receives the differential accompanying clock DCLKI+/- output by the RF ADC, and outputs four differential clocks DCLKI1+/-, DCLKI2+/-, DCLKI3+/-, DCLKI4+/-, and the clock driver 2 receives the differential accompanying clock DCLKQ+/- output by the RF ADC , Output 4 differential clocks DCLKQ1+/-, DCLKQ2+/-, DCLKQ3+/-, DCLKQ4+/-; 8 differential clocks are connected to the regional clock pins of the FPGA;

The data DI<11..0>+/- output by the RF ADC, the clock DCLKI1+/- output by the clock driver 1, and the clock DCLKQ3+/- output by the clock driver 2 are a group, which are input into the same bank of the FPGA; RF ADC The output data DId<11..0>+/-, the clock DCLKI2+/- output by the clock driver 1, and the clock DCLKQ4+/- output by the clock driver 2 are a group, which are input into the same bank of the FPGA; the RF ADC output Data DQ<11..0>+/-, clock DCLKI3+/- output by clock driver 1, and clock DCLKQ1+/- output by clock driver 2 are a group, which are input into the same bank of FPGA; data DQd output by RF ADC <11..0>+/-, the clock DCLKI2+/- output by the clock driver 1, and the clock DCLKQ2+/- output by the clock driver 2 are a group, which are input into the same bank of the FPGA; the FPGA has an Iserdes primitive, Realize serial data input and parallel data output.

2. a kind of high-speed parallel data receiving system based on clock driver and FPGA according to claim 1, is characterized in that, after radio frequency ADC carries out quantization to the differential signal of input, output 12bit digital signal, 12bit digital signal passes through 1:2Demux Then output 2 groups of 12-bit differential signals. The differential data signal of each bit is converted from high-speed serial data to low-speed parallel data through the Iserdes primitive in each bank of the FPGA. The differential data of each group of 12-bit data is 1 After the serial-to-parallel conversion of :4, 48bit data is generated and written into the FIFO. When the FPGA outputs 1:2, the DI and DId of the FPGA respectively read the 48bit data from the FIFO and combine them into 96bit data; the operation of the DQ and DQd of the FPGA is the same as that of the FPGA. The DI is consistent with DId. When the RF ADC quantizes the output according to 1:4, the RF ADC is a dual-channel interleaved sampling. The quantized channel-related clock can use DCLKI or DCLKQ, and realize parallelism according to the combination of the numbers in the 4 banks. LVDS data expansion processing.

3. a kind of high-speed parallel data receiving system based on clock driver and FPGA according to claim 1 and 2, is characterized in that, the maximum sampling frequency of described radio frequency ADC is 1.6GHz, the quantization number is 12bit, supports single channel 1:4 LVDS output under 1:1, 1:2 and dual-channel interleaved sampling.

4 . The high-speed parallel data receiving system based on a clock driver and FPGA according to claim 3 , wherein the clock driver 1 has dual differential clock input options, and reaches 10 differential clock outputs. 5 .

5 . A high-speed parallel data receiving system based on a clock driver and an FPGA according to claim 4 , wherein the clock driver 2 has dual differential clock inputs optional, and reaches 10 differential clock outputs. 6 .