CN111026221A - Voltage reference circuit working under low power supply voltage - Google Patents
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- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
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Abstract
The invention discloses a voltage reference circuit working under low power supply voltage, comprising: the device comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a first power supply and an operational amplifier driven by a substrate, wherein the first PMOS tube, the second PMOS tube and the third PMOS tube work in a subthreshold region. The invention forms deep negative feedback through the operational amplifier driven by the substrate, replaces the traditional operational amplifier with high voltage margin, utilizes the NMOS tube working in the subthreshold region to replace the traditional triode, utilizes the advantage that the threshold voltage of the NMOS tube becomes smaller along with the deep submicron process, and can be suitable for the deep submicron low power supply voltage.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuits, in particular to a voltage reference circuit working under low power supply voltage.
Background
BG (voltage reference circuit) is a general-purpose unit circuit, and plays a very important role in circuits such as an analog-to-digital/digital-to-analog converter and a temperature and pressure sensor. The traditional BG circuit structure is shown in fig. 1, the minimum required power voltage VCC is Vbg +2 × Vds, where Vbg is the output voltage of the bandgap reference, generally about 1.25V, Vds is the source-drain voltage difference of the PMOS transistor, generally above 100mV, and VCC generally needs to be above 1.6V in consideration of the process temperature change. Modern advanced technology power supply voltages are often lower than 1V, so that a voltage reference circuit capable of working under low power supply voltages is particularly critical.
Patent 1(CN103389764), as shown in fig. 2, two BJT branch currents are constructed, then a current with small temperature change is obtained through calculation, and then the current is poured onto an output resistor to generate a voltage close to 0 temperature coefficient, which solves the problem that a traditional BG circuit only can generate PTAT (current positively correlated with temperature) current, so that an output stage voltage summing circuit must consume a large voltage margin, however, for the structure shown in fig. 2, a core module generating two BJT branch currents still needs to satisfy VCC > Vbe +2 Vds, where Vbe is emitter-base voltage of a triode generally about 0.7-0.9V, and considering process temperature change, generally VCC needs to be greater than 1.2V, and therefore, it is still not suitable for a power supply voltage below 1V. Patent 2(CN101763138), as shown in fig. 3, a current with small temperature variation is generated in a manner similar to patent 1, and finally, a small reference voltage is generated across the output resistor, thereby reducing the requirement of the power supply voltage, and the core circuit only uses a 1-level current source, so that VCC > Vbe +1 × Vds is enough, but considering the process temperature variation, it is still difficult to work in the deep submicron process because the power supply voltage is often below 0.9V.
The patent 1 and the patent 2 both realize the voltage reference current under the low power supply voltage through the creative invention, but both have defects, and the invention adopts the structure shown in fig. 4 to provide a voltage reference circuit under the low power supply voltage, which can be suitable for the deep submicron process.
Disclosure of Invention
In view of the defects in the prior art, the present invention aims to provide a voltage reference circuit operating at a low power supply voltage, which can be applied to a deep submicron low power supply voltage by using an operational amplifier driven by a substrate and a device operating in a sub-threshold region.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a voltage reference circuit operating at a low supply voltage, the voltage reference circuit comprising: the transistor comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a first power supply and an operational amplifier driven by a substrate, wherein the first PMOS tube and the second PMOS tube work in a subthreshold region;
the source electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are connected with the first power supply, the grid electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are connected with the output end of the operational amplifier, the drain electrode of the first PMOS tube is connected with the inverting input end of the operational amplifier, the drain electrode of the second PMOS tube is connected with the non-inverting input end of the operational amplifier, the drain electrode of the third PMOS tube is connected with the output end of the voltage reference circuit, the source electrodes of the first NMOS tube and the second NMOS tube are grounded, the grid electrode and the drain electrode of the first NMOS tube are both connected with the inverting input end of the operational amplifier, the grid electrode and the drain electrode of the second NMOS tube are both connected with one end of the third resistor, the other end of the third resistor is connected with the non-inverting input end of the operational amplifier, one end of the first resistor is grounded, and the other end of the first resistor is connected with the inverting input end of the operational, one end of the second resistor is grounded, the other end of the second resistor is connected with the non-inverting input end of the operational amplifier, and one end of the fourth resistor is grounded, and the other end of the fourth resistor is connected with the output end of the voltage reference circuit.
Further, as the voltage reference circuit described above, the operational amplifier includes: a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a second power supply and a capacitor;
the source electrodes of the fourth, fifth, sixth, seventh and eighth PMOS transistors are connected to the second power supply, the gates of the fourth, fifth, sixth, seventh and eighth PMOS transistors are connected to a bias voltage, the drain electrode of the fourth PMOS transistor is connected to the gates of the fourth and fifth NMOS transistors, the drain electrode of the fifth PMOS transistor is connected to the source electrodes of the ninth and tenth PMOS transistors, the drain electrode of the sixth PMOS transistor is connected to the drain electrode of the fourth, sixth and seventh NMOS transistors, the drain electrode of the seventh PMOS transistor is connected to the drain electrode of the fifth NMOS transistor, the positive electrode of the capacitor and the gate of the eighth NMOS transistor, the drain electrode of the eighth PMOS transistor, the negative electrode of the capacitor and the drain electrode of the eighth NMOS transistor are connected to the output terminal of the operational amplifier, the grid electrode and the drain electrode of the third NMOS tube are connected with the drain electrode of the fourth PMOS tube, the source electrodes of the third NMOS tube, the sixth NMOS tube, the seventh NMOS tube and the eighth NMOS tube are grounded, the drain electrode of the ninth PMOS tube is connected with the source electrode of the fourth NMOS tube and the drain electrode of the sixth NMOS tube, the grid electrodes of the ninth PMOS tube and the tenth PMOS tube are grounded, the drain electrode of the tenth PMOS tube is connected with the source electrode of the fifth NMOS tube and the drain electrode of the seventh NMOS tube, the substrate of the ninth PMOS tube is connected with the inverting input end of the operational amplifier, and the substrate of the tenth PMOS tube is connected with the non-inverting input end of the operational amplifier.
Further, as the voltage reference circuit, the voltage difference Δ V between the first NMOS transistor and the second NMOS transistor is calculated by the following formulaGS：
Wherein T is temperature, K, N and q are all electrical constants, and N is the ratio of the width-to-length ratio of the first NMOS tube to the second NMOS tube.
Further, in the voltage reference circuit, a voltage difference between the first NMOS transistor and the second NMOS transistor is a negative temperature system, and the voltage difference is divided by the third resistor to obtain a current with a positive temperature coefficient.
Further, in the voltage reference circuit, a voltage difference between the first NMOS transistor and the second NMOS transistor is a negative temperature system, the voltage difference is divided by the first resistor to obtain a first current with a negative temperature coefficient, the voltage difference is divided by the second resistor to obtain a second current with a negative temperature coefficient, a sum of the first current and the second current forms a current with an approximately zero temperature coefficient, and the current is mirrored by the first PMOS transistor and the second PMOS transistor and then is input to the fourth resistor to form a reference voltage output.
Further, in the voltage reference circuit, a power supply voltage required for the operation of the operational amplifier is greater than the sum of the gate-source voltage of the third NMOS transistor and the drain-source voltage of the fourth PMOS transistor.
Further, in the voltage reference circuit, a power supply voltage required for the operation of the operational amplifier is greater than a sum of the drain-source voltage of the fourth PMOS transistor, the drain-source voltage of the ninth PMOS transistor, and the drain-source voltage of the sixth NMOS transistor.
The invention has the beneficial effects that: the invention forms deep negative feedback through the operational amplifier driven by the substrate, replaces the traditional operational amplifier with high voltage margin, utilizes the NMOS tube working in the subthreshold region to replace the traditional triode, utilizes the advantage that the threshold voltage of the NMOS tube becomes smaller along with the deep submicron process, and can be suitable for the deep submicron low power supply voltage.
Drawings
Fig. 1 is a structural diagram of a conventional BG circuit provided in an embodiment of the present invention;
fig. 2 is a structural diagram of a BG circuit in patent 1 provided in an embodiment of the present invention;
fig. 3 is a structural diagram of a BG circuit in patent 2 provided in an embodiment of the present invention;
FIG. 4 is a block diagram of a voltage reference circuit operating at a low supply voltage provided in an embodiment of the present invention;
fig. 5 is a structural diagram of an operational amplifier provided in an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and the detailed description.
The invention provides a voltage reference circuit working under low power supply voltage, comprising: the transistor comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a first power supply and an operational amplifier driven by a substrate, wherein the first PMOS tube and the second PMOS tube work in a subthreshold region;
the source electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are connected with a first power supply, the grid electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are connected with the output end of the operational amplifier, the drain electrode of the first PMOS tube is connected with the inverting input end of the operational amplifier, the drain electrode of the second PMOS tube is connected with the non-inverting input end of the operational amplifier, the drain electrode of the third PMOS tube is connected with the output end of the voltage reference circuit, the source electrodes of the first NMOS tube and the second NMOS tube are grounded, the grid electrode and the drain electrode of the first NMOS tube are both connected with the inverting input end of the operational amplifier, the grid electrode and the drain electrode of the second NMOS tube are both connected with one end of a third resistor, the other end of the third resistor is connected with the non-inverting input end of the operational amplifier, one end of the first resistor is grounded, the other end of the second, The other end is connected with the output end of the voltage reference circuit.
The operational amplifier includes: a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a second power supply and a capacitor;
the source electrodes of the fourth PMOS tube, the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube and the eighth PMOS tube are connected with a second power supply, the grid electrodes of the fourth PMOS tube, the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube and the eighth PMOS tube are connected with a bias voltage, the drain electrode of the fourth PMOS tube is connected with the grid electrodes of the fourth NMOS tube and the fifth NMOS tube, the drain electrode of the fifth PMOS tube is connected with the source electrodes of the ninth PMOS tube and the tenth PMOS tube, the drain electrode of the sixth PMOS tube is connected with the drain electrode of the fourth NMOS tube, the grid electrodes of the sixth NMOS tube and the seventh NMOS tube, the drain electrode of the seventh PMOS tube is connected with the drain electrode of the fifth NMOS tube, the positive electrode of the capacitor and the grid electrode of the eighth NMOS tube, the drain electrode of the eighth tube, the negative electrode of the capacitor and the drain electrode of the eighth NMOS tube are connected with the output end of the operational amplifier, the grid electrode and drain electrode of the third NMOS tube are connected with the drain electrode of the fourth PMOS tube, the drain electrode of the third NMOS tube, the drain electrode of the sixth NMOS tube, the seventh NMOS tube and the drain electrode of the, the grid electrodes of the ninth PMOS tube and the tenth PMOS tube are grounded, the drain electrode of the tenth PMOS tube is connected with the source electrode of the fifth NMOS tube and the drain electrode of the seventh NMOS tube, the substrate of the ninth PMOS tube is connected with the inverting input end of the operational amplifier, and the substrate of the tenth PMOS tube is connected with the non-inverting input end of the operational amplifier.
Calculating the voltage difference delta V between the first NMOS tube and the second NMOS tube by the following formulaGS：
T is temperature, K, N and q are all electrical constants, and N is the ratio of the width-length ratio of the first NMOS tube to the second NMOS tube.
The voltage difference between the first NMOS tube and the second NMOS tube is a negative temperature system, and the voltage difference is divided by the third resistor to obtain a current with a positive temperature coefficient.
The voltage difference between the first NMOS tube and the second NMOS tube is a negative temperature system, the voltage difference is divided by the first resistor to obtain a first current with a negative temperature coefficient, the voltage difference is divided by the second resistor to obtain a second current with a negative temperature coefficient, the sum of the first current and the second current forms a current with an approximately zero temperature coefficient, and the current is input into the fourth resistor after passing through the first PMOS tube and the second PMOS tube to form reference voltage output.
The power supply voltage required by the operation of the operational amplifier is greater than the sum of the gate-source voltage of the third NMOS tube and the drain-source voltage of the fourth PMOS tube. Or,
the power supply voltage required by the operation of the operational amplifier is greater than the sum of the drain-source voltage of the fourth PMOS tube, the drain-source voltage of the ninth PMOS tube and the drain-source voltage of the sixth NMOS tube.
Existing BG circuits typically must be implemented with transistors that are difficult to work at low supply voltages that match deep sub-micron processes. The invention forms deep negative feedback through the operational amplifier driven by the substrate, and replaces the traditional operational amplifier with high voltage margin; the NMOS tube working in the sub-threshold region is used for replacing the traditional triode, so that the advantage that the threshold voltage of the NMOS is reduced along with the deep submicron process is utilized, and the voltage reference circuit suitable for the deep submicron low power supply voltage can be finally obtained.
The invention uses NMOS tube working in sub-threshold region to construct current near 0 temperature coefficient, and uses substrate-driven operational amplifier to construct depth negative feedback circuit, thereby ensuring that the power supply voltage of each core module can work below 0.8V, and the invention is suitable for deep submicron low power supply voltage.
Example one
As shown in fig. 4, a voltage reference circuit operating at a low supply voltage, the voltage reference circuit comprising: PMOS tubes P1, P2 and P3, NMOS tubes N1 and N2, resistors R1, R2, R3 and R4, a power supply and an operational amplifier OPAM;
the source electrodes of P1, P2 and P3 are connected with a power supply, the grid electrodes of P1, P2 and P3 are connected with the output end of the OPAM, the drain electrode of P1 is connected with the inverting input end of the OPAM, the drain electrode of P2 is connected with the non-inverting input end of the OPAM, the drain electrode of P3 is connected with the output end, the source electrodes of N1 and N2 are grounded, the grid electrode and the drain electrode of N1 are connected with the inverting input end of the OPAM, the grid electrode and the drain electrode of N2 are connected with one end of R3, the other end of R3 is connected with the non-inverting input end of the OPAM, one end of R1 is grounded, the other end of the R2 is grounded, the other end of the R4 is grounded.
As shown in fig. 5, the operational amplifier OPAM includes: PMOS tubes P4, P5, P6, P7, P8, P9 and P10, NMOS tubes N3, N4, N5, N6, N7 and N8, and a power supply and a capacitor Cc;
the sources of P4, P5, P6, P7 and P8 are connected with a power supply, and the gates of P4, P5, P6, P7 and P8 are connected with a bias voltage VbThe drain of P4 is connected with the gates of N4 and N5, the drain of P5 is connected with the sources of P9 and P10, the drain of P6 is connected with the drain of N4, the gates of N6 and N7, the drain of P7 is connected with the drain of N5, the positive pole of capacitor Cc and the gate of N8, the drain of P8, the negative pole of capacitor Cc and the drain of N8 are connected with the output end,the grid and the drain of N3 are connected with the drain of P4, the sources of N3, N6, N7 and N8 are grounded, the drain of P9 is connected with the source of N4 tube and the drain of N6, the grids of P9 and P10 are grounded, the drain of P10 is connected with the source of N5 and the drain of N7, the substrate (b-) of P9 is connected with the inverting input end, and the substrate (b +) of P10 is connected with the non-inverting input end.
The invention uses NMOS tubes N1 and N2 working in a subthreshold region to replace a triode in the traditional BG. Wherein, the gate-source voltage corresponding to N1 and N2 is N1_ VGS、N2_VGSThe voltage difference between N1 and N2 follows the following equation:
wherein, is Δ VGS＝N1_VGS-N2_VGST is temperature, K, N and q are all electrical constants, and N is the ratio of the width-to-length ratio of N1 to N2.
The voltage difference Δ V of the two NMOS transistors working in the sub-threshold regionGSThe division by R3 constitutes a positive temperature coefficient of current, and Δ VGSIs itself a negative temperature coefficient, Δ VGS[ delta ] R1 and [ delta ] VGSthe/R2 forms negative temperature coefficient current, the sum of the two currents forms currents I1 and I2 with approximate 0 temperature coefficient, and the currents are mirrored into current I3 through current mirrors P1 and P2 and then flow to an output resistor R4 to form final reference voltage output. Since N1 and N2 working in subthreshold region are selected, their VGS(Gate-source Voltage) even considering the process temperature variation, it does not exceed 0.6V, and the V of P1 and P2DS(drain-source voltage), the whole core circuit can work below 0.8V, and is suitable for the current mainstream 16/14/12nm technology.
Since all modules must operate at low supply voltage, the substrate-driven operational amplifier of the present invention can also operate at low supply voltage. As shown in FIG. 5, the power source VCC required for the whole operational amplifier to work>N3_VGS+P4_VDSOr VCC>P4_VDS+P9_VDS+N6_VDSIt can be seen that both can be less than 0.8V in deep submicron processes.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is intended to include such modifications and variations.
Claims (7)
1. A voltage reference circuit operating at a low supply voltage, the voltage reference circuit comprising: the transistor comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a first power supply and an operational amplifier driven by a substrate, wherein the first PMOS tube and the second PMOS tube work in a subthreshold region;
the source electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are connected with the first power supply, the grid electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are connected with the output end of the operational amplifier, the drain electrode of the first PMOS tube is connected with the inverting input end of the operational amplifier, the drain electrode of the second PMOS tube is connected with the non-inverting input end of the operational amplifier, the drain electrode of the third PMOS tube is connected with the output end of the voltage reference circuit, the source electrodes of the first NMOS tube and the second NMOS tube are grounded, the grid electrode and the drain electrode of the first NMOS tube are both connected with the inverting input end of the operational amplifier, the grid electrode and the drain electrode of the second NMOS tube are both connected with one end of the third resistor, the other end of the third resistor is connected with the non-inverting input end of the operational amplifier, one end of the first resistor is grounded, and the other end of the first resistor is connected with the inverting input end of the operational, one end of the second resistor is grounded, the other end of the second resistor is connected with the non-inverting input end of the operational amplifier, and one end of the fourth resistor is grounded, and the other end of the fourth resistor is connected with the output end of the voltage reference circuit.
2. The voltage reference circuit of claim 1, wherein the operational amplifier comprises: a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a second power supply and a capacitor;
the source electrodes of the fourth, fifth, sixth, seventh and eighth PMOS transistors are connected to the second power supply, the gates of the fourth, fifth, sixth, seventh and eighth PMOS transistors are connected to a bias voltage, the drain electrode of the fourth PMOS transistor is connected to the gates of the fourth and fifth NMOS transistors, the drain electrode of the fifth PMOS transistor is connected to the source electrodes of the ninth and tenth PMOS transistors, the drain electrode of the sixth PMOS transistor is connected to the drain electrode of the fourth, sixth and seventh NMOS transistors, the drain electrode of the seventh PMOS transistor is connected to the drain electrode of the fifth NMOS transistor, the positive electrode of the capacitor and the gate of the eighth NMOS transistor, the drain electrode of the eighth PMOS transistor, the negative electrode of the capacitor and the drain electrode of the eighth NMOS transistor are connected to the output terminal of the operational amplifier, the grid electrode and the drain electrode of the third NMOS tube are connected with the drain electrode of the fourth PMOS tube, the source electrodes of the third NMOS tube, the sixth NMOS tube, the seventh NMOS tube and the eighth NMOS tube are grounded, the drain electrode of the ninth PMOS tube is connected with the source electrode of the fourth NMOS tube and the drain electrode of the sixth NMOS tube, the grid electrodes of the ninth PMOS tube and the tenth PMOS tube are grounded, the drain electrode of the tenth PMOS tube is connected with the source electrode of the fifth NMOS tube and the drain electrode of the seventh NMOS tube, the substrate of the ninth PMOS tube is connected with the inverting input end of the operational amplifier, and the substrate of the tenth PMOS tube is connected with the non-inverting input end of the operational amplifier.
3. The voltage reference circuit of claim 1, wherein the voltage difference Δ ν between the first NMOS transistor and the second NMOS transistor is calculated byGS：
Wherein T is temperature, K, N and q are all electrical constants, and N is the ratio of the width-to-length ratio of the first NMOS tube to the second NMOS tube.
4. The voltage reference circuit of claim 3, wherein a voltage difference between the first NMOS transistor and the second NMOS transistor is a negative temperature system, and the voltage difference is divided by the third resistor to obtain a positive temperature coefficient current.
5. The voltage reference circuit of claim 4, wherein a voltage difference between the first NMOS transistor and the second NMOS transistor is a negative temperature system, the voltage difference is divided by the first resistor to obtain a first current with a negative temperature coefficient, the voltage difference is divided by the second resistor to obtain a second current with a negative temperature coefficient, a sum of the first current and the second current forms a current with an approximately zero temperature coefficient, and the current is mirrored through the first PMOS transistor and the second PMOS transistor and then input to the fourth resistor to form a reference voltage output.
6. The voltage reference circuit of claim 5, wherein a supply voltage required for operation of the operational amplifier is greater than a sum of a gate-source voltage of the third NMOS transistor and a drain-source voltage of the fourth PMOS transistor.
7. The voltage reference circuit of claim 5, wherein a supply voltage required for the operation of the operational amplifier is greater than a sum of a drain-source voltage of the fourth PMOS transistor, a drain-source voltage of the ninth PMOS transistor, and a drain-source voltage of the sixth NMOS transistor.
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| CN112179528A (en) * | 2020-08-21 | 2021-01-05 | 武汉中航传感技术有限责任公司 | CMOS integrated circuit and pressure sensor |
| CN113162415A (en) * | 2021-05-08 | 2021-07-23 | 上海爻火微电子有限公司 | Input/output management circuit of power supply and electronic equipment |
| CN116414177A (en) * | 2023-02-17 | 2023-07-11 | 厦门凌阳华芯科技股份有限公司 | Band gap reference voltage circuit |
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| CN111580437B (en) * | 2020-05-28 | 2021-07-20 | 上海艾为电子技术股份有限公司 | Enabling control circuit and electronic equipment |
| CN112179528A (en) * | 2020-08-21 | 2021-01-05 | 武汉中航传感技术有限责任公司 | CMOS integrated circuit and pressure sensor |
| CN113162415A (en) * | 2021-05-08 | 2021-07-23 | 上海爻火微电子有限公司 | Input/output management circuit of power supply and electronic equipment |
| CN113162415B (en) * | 2021-05-08 | 2024-03-15 | 上海爻火微电子有限公司 | Input/output management circuit of power supply and electronic equipment |
| CN116414177A (en) * | 2023-02-17 | 2023-07-11 | 厦门凌阳华芯科技股份有限公司 | Band gap reference voltage circuit |
| CN116414177B (en) * | 2023-02-17 | 2025-12-12 | 厦门凌阳华芯科技股份有限公司 | A bandgap reference voltage circuit |
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