CN111009274B - Flash memory storage device and operation method thereof - Google Patents

Abstract

The present invention provides a flash memory storage device, which includes a memory cell array and a memory control circuit. The memory cell array includes a plurality of well regions. Each well area includes a plurality of memory blocks and recording blocks. The memory control circuit is coupled to the memory cell array. The memory control circuit is used for erasing the memory blocks of each well area, and recording the erasing times of each well area in the respective recording blocks. In addition, an operating method of a flash memory storage device is also proposed.

Description

Flash memory storage device and operating method thereof

technical field

The present invention relates to a memory storage device and its operating method, in particular to a flash memory storage device and its operating method.

Background technique

For flash memory storage devices, the cycling operation tends to generate interface states at the drain junction and oxide traps at the tunnel oxide layer. Generally speaking, cycle operations include erase operations and program operations. Flash memory cells are usually easily degraded after repeated cycles of operation, for example, the reliability of the memory block will decrease, or the erasing time and programming time will increase, that is, the operating speed will slow down. Also, after many cycles of operation, some of the bits in the unit cell will wear out prematurely and out of specification. These worn out bits are difficult to remove during the testing phase. Therefore, if the erasing times of each well area including multiple memory blocks in the memory cell array can be obtained, it will be helpful to evaluate the performance of the flash memory storage device in the subsequent application or manufacturing process.

Contents of the invention

The invention provides a flash memory storage device and its operation method, which can record the times of erasing of the well area.

The flash memory storage device of the present invention includes a memory cell array and a memory control circuit. The memory cell array includes a plurality of well regions. Each well area includes a plurality of memory blocks and recording blocks. The memory control circuit is coupled to the memory cell array. The memory control circuit is used for erasing the memory blocks in each well area, and recording the erasing times of each well area in respective recording blocks.

The operation method of the flash memory storage device of the present invention includes: performing an erasing operation on a plurality of memory blocks in the memory cell array; judging whether the number of times of erasing recorded in at least one record row reaches the upper limit; if at least one The number of erasing times recorded in the record row has reached the upper limit, and at least one record row is erased while performing the erase operation on the memory blocks in the memory cell array; and if at least one record row records The number of erasing times does not reach the upper limit, and the data of erasing times is recorded in at least one record column. The memory block and the recording block are located in the same well area.

Based on the above, in an exemplary embodiment of the present invention, the flash memory storage device can automatically record the number of times each well area is erased. The recorded data can be used for subsequent evaluation of the performance of the flash memory storage device.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

Description of drawings

FIG. 1 shows a schematic diagram of a flash memory storage device according to an embodiment of the present invention.

FIG. 2 shows a schematic diagram of a well area in the memory cell array of the embodiment of FIG. 1 .

FIG. 3 shows a schematic diagram of a recording block in the embodiment of FIG. 1 .

FIG. 4 shows a flow chart of the steps of the operation method of the flash memory storage device according to an embodiment of the present invention.

FIG. 5 shows a flowchart of steps of an operating method of a flash memory storage device according to another embodiment of the present invention.

FIG. 6 shows a detailed flowchart of step S200 in FIG. 5 .

【Symbol Description】

100: Flash memory storage device

110: memory cell array

111_1, 111_2, 111_3, 111_(N-1), 111_N: memory blocks

112: Well area

113: record block

120: memory control circuit

310_1, 310_2, 310_3, 310_M: record columns

312, 312_1, 312_2, 312_3, 312_4, 312_5: bytes

LSB: least significant bit

MSB: most significant bit

S100, S110, S120, S130, S200, S210, S220, S230, S240, S250, S300, S310, S320, S330, S340, S350, S360: steps

Detailed ways

FIG. 1 shows a schematic diagram of a flash memory storage device according to an embodiment of the present invention. FIG. 2 shows a schematic diagram of a well area in the memory cell array of the embodiment of FIG. 1 . Please refer to FIG. 1 and FIG. 2 , the flash memory storage device 100 of this embodiment includes a memory cell array 110 and a memory control circuit 120 . The memory control circuit 120 is coupled to the memory cell array 110 . In this embodiment, the flash memory storage device 100 is, for example, a coded flash memory (NOR Flash).

In this embodiment, the memory cell array 110 includes a plurality of well regions 112 as shown in FIG. 2 . FIG. 2 only shows one well region 112 in the memory cell array 110 , but the number thereof is not limited to the present invention. The well region 112 is, for example, a P well. The well area 112 includes a plurality of memory blocks 111_1 to 111_N and a recording block 113 , wherein N is a positive integer greater than 0. The memory blocks 111_1 to 111_N are used to store data. The recording block 113 is used to store the erasing times of the well area 112 .

In this embodiment, the memory control circuit 120 is configured to perform an erase operation on the memory blocks 111_1 to 111_N of the well area 112 , and record the erasing times of the well area 112 in the recording block 113 . For example, the memory control circuit 120 performs an erase operation on the target memory block 111_2 during the erase period. At this time, the well region 112 is applied with a positive high voltage (positive high voltage), the gate of the memory cell array in the target memory block 111_2 is applied with a negative high voltage (negative high voltage), and the remaining memory blocks 111_1, 111_3, 111_(N -1), the gate of the memory cell array in 111_N is applied with a positive voltage (positive voltage). In this embodiment, the memory block 111_2 is erased, and the erase count of the well region 112 is increased by one. Next, the memory control circuit 120 records the erasing times in the recording block 113 again. When any one of the memory blocks 111_1 to 111_N is erased, the erasing count of the well region 112 will be increased by one.

In the embodiment of multiple well areas, the memory control circuit 120 performs erasing operation on the memory blocks of each well area respectively, and records the erasing times of each well area in the respective recording blocks.

In this embodiment, the memory control circuit 120 can be implemented by any suitable circuit structure in the technical field, and the present invention is not limited thereto. Inspiration, recommendations and implementation notes.

FIG. 3 shows a schematic diagram of a recording block in the embodiment of FIG. 1 . Please refer to FIG. 3 , the recording block 113 of this embodiment includes a plurality of recording columns 310_1 to 310_M, wherein M is a positive integer greater than 0. Referring to FIG. The record columns 310_1 to 310_M include a plurality of bytes 312 . The number of bytes per record column can be the same or different. The record columns 310_1 to 310_M are used to store data of erasing times. For example, each record column is, for example, a word line, which is coupled to a plurality of memory cells (not shown), and some of the memory cells are used to store erasing data. For example, in one embodiment, a plurality of memory cells corresponding to storing two bytes of data in each record row are used to store the data of erasing times. In one embodiment, a plurality of memory cells corresponding to a data volume of four bytes in each record row are used to store erasure count data.

In this embodiment, the memory control circuit 120 starts from the first record row 310_1 and sequentially records the data of erasing times to the last record row 310_M. Taking the first recording column 310_1 including two bytes as an example, the memory control circuit 120 starts from the least significant bit LSB in the byte 312_1 , and sequentially records data of erasing times to the most significant bit MSB. For example, after the memory control circuit 120 performs an erase operation on any of the memory blocks 111_1 to 111_N in the well area 112, the least significant bit LSB in the byte 312_1 is programmed from a state “1” to a state “0” to indicate The erasure count of the well area 112 is increased by one, and is recorded in byte 312_1. In this manner, the memory control circuit 120 sequentially records the data of the erasure times into the MSB of the byte 312_1.

Next, the memory control circuit 120 starts from the least significant bit LSB in the byte 312_2 and sequentially records the data of the erasing times to the most significant bit MSB of the byte 312_2 . Therefore, when all the bits of the two bytes 312_1 and 312_2 in the record row 310_1 are programmed from the state “1” to the state “0”, it means that the number of erasing times of the well area 112 is 16 times. These 16 times are the upper limit of erasing times recorded in the record row 310_1. When the erasing times recorded in the record row 310_1 (the first record row) have reached the upper limit value of the record row 310_1, the memory control circuit 120 uses its next record row 310_2 (the second record row) to record the data in the record row 310_1. The number of times the record was erased.

For example, when the number of erasing times recorded in the recording column 310_1 has reached the upper limit of 16 times, the memory control circuit 120 performs an erasing operation on any memory block during the erasing period, and at the same time performs an erasing operation on the recording column 310_1. 310_1 performs an erase operation to erase all the bits of the two bytes 312_1 and 312_2 from state "0" to state "1" to re-record the number of erases. At this time, when the record column 310_1 is erased once, the memory control circuit 120 programs the least significant bit LSB in the byte 312_3 of the record column 310_2 from a state "1" to a state "0" to indicate that the record column 310_1 The erase count is 1, which means that the erase count of the well area 112 has accumulated 17 times, and is recorded in byte 312_3. In this manner, the memory control circuit 120 sequentially records the data of the erasure times into the MSB of the byte 312_3 .

In this embodiment, after the erasing operation is performed on the recording column 310_1, the memory control circuit 120 will re-record the data of the erasing times in the bytes 312_1 and 312_2 of the recording column 310_1, by reusing the recording words of the recording column 310_1 section, to increase the upper limit of recording times of the recording block 113.

Next, the memory control circuit 120 starts from the least significant bit LSB in the byte 312_4 and sequentially records the data of the erasing times to the most significant bit MSB of the byte 312_4 . Therefore, when all the bits of the two bytes 312_3 and 312_4 in the record row 310_2 are programmed from the state “1” to the state “0”, it means that the number of erasing times of the well area 112 is 256 times. The 256 times is the upper limit of erasing times recorded in the record row 310_2. If the erasing times recorded in the recording row 310_1 and the recording row 310_2 have reached the upper limit, the memory control circuit 120 simultaneously performs an erasing operation on the recording row 310_1 and the recording row 310_2 to re-record the erasing times. At this time, when the record column 310_1 and the record column 310_2 are erased, the memory control circuit 120 programs the least significant bit LSB in the byte 312_5 of the record column 310_3 from the state "1" to the state "0" to indicate the well The erasure count of the area 112 has accumulated 257 times, and is recorded in byte 312_5. In this way, the memory control circuit 120 sequentially records the data of the erasure times into the MSB of the byte 312_5 .

In this embodiment, after the erase operation is performed on the recording row 310_1 and the recording row 310_2, the memory control circuit 120 will re-record the data of the erasing times in the bytes 312_1 and 312_2 of the recording row 310_1 and the bytes of the recording row 310_2 In 312_3 and 312_4 , the upper limit of recording times of the recording block 113 is increased by reusing the recording bytes of the recording row 310_1 and the recording row 310_2 .

By analogy, if the erasing times of 100 thousand times (100k) are recorded as the goal, the recording block 113 includes 4 recording columns, and the first to the third recording columns correspond to the amount of data stored in two bytes. A plurality of memory cells are used to store the data of erasing times, and the fourth record row uses a plurality of memory cells corresponding to storing three bytes of data to store the data of erasing times. When the erasing times recorded in the last record column (such as 310_M) has reached the upper limit value of the record column, it is the upper limit value of the erasing times recorded in the recording block, and the memory control circuit 120 no longer The last record column is erased.

In another embodiment, the recording block 113 includes, for example, 4 recording columns, and the first to the third recording columns store the data of the number of times of erasing with a plurality of memory cells corresponding to a data amount of four bytes. , and the fourth record column stores data of erasing times in a plurality of memory cells corresponding to a data amount of one byte. Therefore, in this example, the recording block 113 can record approximately 256 thousand times (256k) of erasing times.

In this embodiment, each record row is, for example, a word line, which is coupled to a plurality of memory cells (not shown), and some of the memory cells are used to store erasing data. Compared with the word lines coupled to the memory blocks 111_1 to 111_N, the word lines coupled to the recording block 113 (i.e., the recording column) are additionally disposed in the well area 112 for recording the erasing times. Wire. When the memory control circuit 120 programs a valid bit in the byte of the record column 310_1 (LSB record column) from the state “1” to the state “0”, that is, the erasure count of the record well area 112 is increased by one. When the erasing times recorded in the recording column 310_1 reach the upper limit and are erased once, the memory control circuit 120 programs a valid bit in the byte of the next recording column 310_2 from the state "1" to the state "0". ", to indicate that the erasing count of the record row 310_1 is increased by one. When the erasing times recorded in the bytes of the recording columns 310_1 to 310_2 all reach the upper limit and are erased at the same time, the memory control circuit 120 changes a valid bit in the byte of the next recording column 310_3 from the state “1 ” is programmed into a state of “0” to indicate that the erasing count of the record row 310_2 is increased by 1. The number of times of erasure of the well area 112 can be obtained by counting data of different values in the bytes of each record row.

FIG. 4 shows a flow chart of the steps of the operation method of the flash memory storage device according to an embodiment of the present invention. The operation method of this embodiment is applicable to, for example, a NOR Flash storage device. Referring to FIG. 1 to FIG. 4 , in step S100 , the memory control circuit 120 performs an erase operation on the memory blocks 111_1 to 111_N located in the same well area 112 in the memory cell array 110 . In step S110 , the memory control circuit 120 determines whether the number of erasing times recorded in the recording column 310_1 in the recording block 113 reaches the upper limit. If yes, the memory control circuit 120 executes step S120 , performing an erasing operation on the record row 310_1 while performing an erase operation on the memory blocks 111_1 to 111_N, and recording data of erasing times in the record row 310_2 . If not, the memory control circuit 120 executes step S130 to record the erasing count data in the record row 310_1 .

In addition, the operation method of the flash memory storage device of the embodiment of the present invention can obtain sufficient enlightenment, suggestion and implementation description from the description of the embodiment in FIG. 1 to FIG. 3 .

FIG. 5 shows a flowchart of steps of an operating method of a flash memory storage device according to another embodiment of the present invention. The operation method of this embodiment is applicable to, for example, a NOR Flash storage device. Please refer to FIG. 5 , in this embodiment, the memory control circuit 120 performs an erase operation on the memory blocks 111_1 to 111_N located in the same well region 112 in the memory cell array 110 . The erase operation includes performing a pre-program operation (step S210), an erase operation (step S220), and a post-program operation (step S230) on the target memory block 111_2, To weakly program (soft-program) the memory cells that are over-erased in the target memory block and perform a refresh (refresh) operation on the memory blocks 111_1 and 111_3 to 111_N outside the target memory (step S240), so as to target non- Already programmed memory cells in the target memory block are programmed. In this embodiment, performing the pre-programming operation, erasing operation, post-programming operation on the target memory block 111_2, and performing refresh operations on the memory blocks 111_1 and 111_3 to 111_N other than the target memory can be performed by those skilled in the art Obtain sufficient enlightenment, suggestions and implementation instructions from common knowledge.

In this embodiment, before step S210 is executed, in step S200 , the memory control circuit 120 first scans the bytes 312_1 and 312_2 in the record column 310_1 to determine which bits are “1”. If the state of at least one bit in the bytes 312_1 and 312_2 is “1”, the memory control circuit 120 may record the erasing count data in the bit whose state is “1” in step S250 . If the states of all the bits in the bytes 312_1 and 312_2 are “0”, the memory control circuit 120 can record the data of the erasing times in the record row 310_2 , that is, the programmed record row 310_2 in step S250 . Moreover, in step S220 , the memory control circuit 120 performs an erase operation on the record row 310_1 while performing an erase operation on the target memory block 111_2 .

In step S200, after scanning, if the memory control circuit 120 judges that the state of all bits of the bytes in the recording columns 310_1 and 320_2 is "0", the memory control circuit 120 can record the data of the erasing times in step S250 In the next record column of record column 310_2. Moreover, in step S220 , the memory control circuit 120 performs an erase operation on the record columns 310_1 and 310_2 while performing an erase operation on the target memory block 111_2 . The erase operation of the memory control circuit 120 on the remaining record rows can be deduced by analogy.

In this embodiment, the memory control circuit 120 performs post-programming and refresh operations on the memory blocks 111_1 to 111_N in steps S230 and S240, and also performs post-programming and refresh operations on the recording block 113. Refresh operation. In addition, the operation method of the flash memory storage device of the embodiment of the present invention can obtain sufficient enlightenment, suggestion and implementation description from the description of the embodiment in FIG. 1 to FIG. 4 .

FIG. 6 shows a detailed flowchart of step S200 in FIG. 5 . Please refer to FIG. 3 and FIG. 6 , in step S300 , the memory control circuit 120 sets the read mode to the record block 113 , and sets to start reading from the record row 310_1 . In step S310, the memory control circuit 120 reads the data of the byte 312_1 starting from the least significant bit LSB in the byte 312_1. In step S320, the memory control circuit 120 judges whether or not the states of the read data are all "0".

If the data state is not all "0", for example, at least one data state is "1", the memory control circuit 120 executes step S330, loads the address of byte 312_1 and its data into the register and loads its program in step S250 For example, perform one-bit programming (one-bit program) on the bits whose data state is not “0” in the byte 312_1 to record the erasing times. After step S330, the memory control circuit 120 returns to the process of FIG. 5 to execute step S210.

If the data states are all "0", the memory control circuit 120 executes step S340 to determine whether the read byte is the last byte in the record row 310_1. If the read byte is not the last byte in the record column 310_1 , the memory control circuit 120 returns to step S310 to read the next byte, namely byte 312_2 . If the read byte is the last byte in the record row 310_1 , the memory control circuit 120 executes step S350 to determine whether the read record row is the last record row 310_M in the record block 113 .

If the read record column is not the last record column 310_M in the record block 113, the memory control circuit 120 returns to step S310, and reads the first byte of the next record column, such as the byte 312_3 of the record column 310_2 . If the data state is not all "0", the memory control circuit 120 executes step S330, and the address of byte 312_3, its data and the record column address that has reached the upper limit of recording are loaded into the register, and will be processed in steps S210 to S240 While the target memory block is performing the erasing operation, the erasing operation is also performed on the record column 310_1, and in step S250, a bit is programmed for the bit whose data state is not "0" in the byte 312_3 to record the erasing number of divisions. If the read record row is the last record row 310_M in the record block 113 , the memory control circuit 120 executes step S360 to finish setting the data of the read byte. After step S360, the memory control circuit 120 returns to the process of FIG. 5 to execute step S210.

To sum up, in the exemplary embodiment of the present invention, the flash memory storage device can automatically record the erasing times of each well area in the respective recording blocks. The recording column in the recording block is additionally arranged on the word line in the well area for recording the erasing times, and part or all of the memory cells coupled with the word lines can be used to store the erasing times data. The recorded data can be used for subsequent evaluation of the performance of the flash memory storage device.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of the invention should be defined by the claims.

Claims (15)

1. A flash memory storage device, comprising:

a memory cell array including a plurality of well regions, each well region including a plurality of memory blocks and a recording block, wherein the plurality of memory blocks and the recording block are in the same well region, wherein the plurality of memory blocks are used for storing data, and the recording block is used for storing erase times of the plurality of memory blocks; and

a memory control circuit, coupled to the memory cell array, for performing an erase operation on the plurality of memory blocks of each of the well regions and recording the erase count of the plurality of memory blocks of each of the well regions in the respective recording blocks,

wherein the recording block includes at least one recording row serving as a word line, wherein at least one memory cell coupled to the at least one recording row stores the erase count,

wherein if the erase count recorded by the at least one record row has reached an upper limit, the memory control circuit performs the erase operation on the at least one record row while performing the erase operation on the plurality of memory blocks in the memory cell array.

2. The flash memory storage device of claim 1, wherein the at least one record row comprises a plurality of record rows for storing the erasure count data, and each record row comprises a plurality of bytes.

3. The flash memory storage device of claim 2, wherein the memory control circuit sequentially records the erase count data to a last recording row of the recording blocks starting from a first recording row of the recording blocks.

4. The flash memory storage device of claim 3, wherein the memory control circuit sequentially records the erase count data to the most significant bit of each of the bytes, starting from the least significant bit of each of the bytes.

5. The flash memory storage device of claim 2, wherein the erase count recorded in each record row has an upper limit, the plurality of record rows includes a first record row and a second record row, and when the erase count recorded in the first record row reaches the upper limit of the first record row, the memory control circuit records the erase count recorded in the first record row by using the second record row until the erase count recorded in the second record row reaches the upper limit of the second record row.

6. The flash memory storage device of claim 5, wherein the memory control circuit performs the erase operation on the first record row during an erase when the erase count recorded by the first record row has reached an upper limit value of the first record row.

7. The flash memory storage device of claim 6, wherein the memory control circuitry performs the erase operation on the first record column together during the erase while performing the erase operation on the plurality of memory blocks.

8. The flash memory storage device of claim 5, wherein the second record row is a next record row of the first record row in the record block.

9. The flash memory storage device of claim 6, wherein the memory control circuit restores the erased data to the erased first record row after the erase operation is performed on the first record row.

10. An operation method of a flash memory storage device, wherein the flash memory storage device includes a memory cell array including a recording block including a plurality of recording rows, the operation method comprising:

performing an erase operation on a plurality of memory blocks in the memory cell array, wherein the plurality of memory blocks and the recording block are located in the same well region, wherein the plurality of memory blocks are used for storing data, and the recording block is used for storing erase times of the plurality of memory blocks;

recording all the erasing times of the recording block in a first recording row in the plurality of recording rows;

judging whether the erasing times recorded by the first recording row reach an upper limit value or not;

if the erase count recorded in the first record row has reached the upper limit, performing the erase operation on the first record row while performing the erase operation on the plurality of memory blocks in the memory cell array, and recording data of the erase count recorded in the first record row in a second record row of the plurality of record rows;

after the first record row is subjected to erasing operation, recording the data of the erasing times in the first record row again, and sequentially recording the data of the erasing times recorded in the first record row to an upper limit value in the second record row;

if the erase count recorded in the first record row and the second record row has reached the upper limit, performing the erase operation on the first record row and the second record row while performing the erase operation on the plurality of memory blocks in the memory cell array, and recording the data of the erase count recorded in the second record row in a third record row level record row in the plurality of record rows; and

after the first record row and the second record row are erased, re-recording the data of the erase count in the first record row and recording the data of the erase count recorded in the first record row in the second record row, sequentially recording the data of the erase count recorded in the second record row to an upper limit value in the third record row,

the second record row is used for storing whether the erasing times recorded by the first record row reach an upper limit value, and the third record row is used for storing whether the erasing times recorded by the second record row reach the upper limit value.

11. The operating method according to claim 10, wherein the step of recording the erasure count data in the plurality of record columns comprises:

and sequentially recording the data of the erasing times to the last recording row of the recording block from the first recording row of the recording block.

12. The operating method according to claim 11, wherein the step of recording the data of the erasure count in the plurality of record columns further comprises:

sequentially recording the erasure count data to the most significant bit of each of the plurality of bytes, starting from the least significant bit of the plurality of bytes of each of the plurality of record rows, wherein the plurality of record rows are used for storing the erasure count data, and the erasure count of each well region is calculated by the data with different values in the plurality of bytes of each of the plurality of record rows.

13. The operating method according to claim 10, wherein the plurality of record rows include a first record row and a second record row, and in the step of performing the erase operation on the plurality of record rows for which the erase count has reached the upper limit value, when the erase count recorded by the first record row has reached the upper limit value of the first record row, the erase operation is performed on the first record row while performing the erase operation on the plurality of memory blocks in the memory cell array.

14. The operating method according to claim 13, wherein the second recording column is a next recording column of the first recording column in the recording block.

15. The method according to claim 13, wherein in the step of recording the erased data in the plurality of record rows, the erased data is stored again in the first record row after the erasing operation is performed on the first record row.

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