CN111008507B - A method and device for calculating the reliability boundary of logic circuits affected by soft errors - Google Patents

Abstract

The invention discloses a method and a device for calculating the reliability boundary of a logic circuit affected by soft errors, wherein the method comprises the following steps: representing a circuit reliability target as a sum of the multi-stage components; performing single-fault simulation on the circuit to obtain T₁A value; performing double-fault simulation on the circuit to obtain T₂A value; calculating a reliability boundary of the circuit; compared with the prior art, the method of the invention utilizes a probability distribution model, and firstly expresses the reliability target of the large-scale and super-large-scale logic circuit to be calculated as the sum of multi-order components; then, simulating and calculating the working conditions of the circuit with single fault and double faults so as to calculate the correct output probability of the circuit when the faults occur; and finally substituting the simulation result into the reliability boundary expression to obtain the first-order and second-order upper and lower limits of the circuit reliability. The method ensures that the reliability boundary value which is very close to the real reliability of the circuit is calculated in reasonable time, and is suitable for the reliability calculation of large-scale and super-large-scale logic circuits.

Description

A method and device for calculating the reliability boundary of logic circuits affected by soft errors

technical field

The invention relates to the field of circuits, in particular to a method and device for calculating the reliability boundary of a logic circuit affected by soft errors.

Background technique

With the application and popularization of nanotechnology, the scale of logic circuits continues to increase, the feature size of devices continues to shrink, and the performance of chips has been steadily improved. At the same time, due to various space radiation reasons and the reaction of radioactive impurities in chip packaging materials. Soft errors also pose serious challenges to chip reliability. The latest research by many well-known companies such as Sony and IBM shows that reliability issues will always accompany the development and application of semiconductor devices and integrated circuits.

A soft error in an integrated circuit is a transient error that is not destructive to the circuit hardware itself. Soft errors have the characteristics of transient, recoverable, random occurrence time and place. There are many factors that cause soft errors, such as power supply noise, electromagnetic interference, the reaction of radioactive impurities in packaging materials, and the radiation of high-energy particles in space. Among them, particle radiation is the main cause of soft errors. High-energy particle effects that cause soft errors include Single Event Upset (SEU) and Single Event Transient (SET). SEU refers to the memory cells of integrated circuits, such as memories, flip-flops and latches, which are attacked by high-energy particles and cause logic flips; SET refers to transient fault pulses that occur in logic circuit combination modules. The sensitization path propagates to the circuit output and is sampled by the latch, causing soft errors. Both SEU and SET can cause integrated circuit failure. As the threshold voltage of the chip is further reduced, the number of integrated transistors increases exponentially, the design becomes more and more sensitive to radiation, and the circuit soft error rate also rises sharply. Accurately calculating the reliability of logic circuits affected by soft errors can provide a basis for the comprehensive layout and fault-tolerant design of circuits. It is the main technical direction of reliability research and an important problem that needs to be solved urgently.

The data inversion of the storage unit caused by SEU can be detected and recovered by the method of error correction code.

Logic circuit failures caused by SET mainly include:

One common method for calculating soft error reliability of logic circuits is to inject SET fault pulses into the circuit and simulate the propagation of fault pulses under different input excitations; the other method mainly uses signal probability theory, aiming at different logic units. Establish the propagation rule of fault pulse and the calculation formula of signal probability. There are also mathematical concepts and mathematical tools used to analyze the reliability of logic circuits affected by soft errors, such as: Probabilistic Transfer Matrices (PTMs), Algebraic Decision Diagrams (ADDs), and Transient Fault Propagation Metrics (Transient Fault Propagation Metrics, TFPMs), etc.

The method based on fault injection and simulation can provide accurate reliability calculation results, but the calculation process is very time-consuming, especially when evaluating large-scale, ultra-large-scale or even larger-scale circuits. The number of excitation vectors is very large, and in order to obtain relatively accurate results, the computational time required by such methods is often unacceptable.

The computational complexity of the circuit reliability assessment method based on signal probability calculation is roughly linear with the circuit scale, so the computational speed of this kind of method will be several orders of magnitude faster than that of the fault simulation method. However, in terms of the accuracy of calculation results, the calculation method of signal probability is not as good as the method of large sample input excitation combined with fault simulation. In order to obtain relatively accurate results, such methods also need to consider a large number of fan-out and re-convergence structures in the circuit, and the signal correlation calculation caused by the fan-out and re-convergence structures is also very time-consuming. In addition, once the influence of multiple transient faults is considered, the computational complexity of the logic circuit node signal probability will be significantly increased, and such methods will no longer be suitable for large-scale and ultra-large-scale circuit reliability calculations.

Using the probability transition matrix to evaluate circuit reliability is a probabilistic analysis method to calculate the influence of soft errors on the reliability of the entire logic circuit. Matrix multiplication or matrix tensor product operation is performed according to the connection inside the circuit, and finally the PTM of the entire circuit is obtained. Algebraic decision diagrams can be used to optimize the PTM computational model. However, with the continuous increase of circuit scale, the PTM method may face the problem of storage space explosion. The circuit reliability calculation method based on transient fault propagation metric is to calculate the fault propagation metric value of all nodes of the circuit by traversing the circuit topology in reverse, and then further calculate the soft error reliability of the combinational logic part. The disadvantage of this method is that the fan-out re-convergence structure in the logic circuit is not fully considered, thus resulting in insufficient accuracy of the calculation results.

SUMMARY OF THE INVENTION

The purpose of the present invention is to solve at least one of the technical problems existing in the prior art, and to provide a method and device for calculating the reliability boundary of a logic circuit affected by soft errors, so as to ensure that the calculation and the circuit are true and reliable within a reasonable time. It is very close to the reliability boundary value, and is suitable for reliability calculation of large-scale and very large-scale logic circuits.

A first aspect of the present invention provides a method for calculating the reliability boundary of a logic circuit affected by soft errors, which is applied to a combinational logic circuit, and is characterized in that it includes the following steps:

The first step is to express the circuit reliability target as the sum of multi-stage components;

Assuming that the circuit has t logic gates that are independent of each other and all fail with a certain probability f, let the reliability R of the circuit be:

In formula (5), p(k=i) represents the probability that the number of fault gates is i; 2 ^m represents the number of input vectors; Y represents the output vector; X _w represents the wth input vector; p(X _w ) represents the input The probability that the vector is _Xw ; p(Y is the correct logical value _Xw , k=i) indicates the probability that the output vector is correct when the input vector is _Xw and the number of fault gates is i;

Rewrite equation (5) as:

表示在t个逻辑门中出现i个故障门的组合数，Y(G_t(i)：j；X_w)表示输入向量为X_w，故障门数量为i，组合数为j时对应的输出向量；G_t(i)表示在t个逻辑门中存在有i个故障门；符号

用于判断符号前后两个向量是否相等，若相等，则输出1；若不相等，则输出0；Y(G_t(0)；X_w)表示输入向量为X_w，故障门数量为0时对应的输出向量；In formula (6),

Indicates the number of combinations of i fault gates in t logic gates, Y(G _t (i): j; X _w ) represents the input vector X _w , the number of fault gates i, and the corresponding output when the number of combinations is j vector; G _t (i) indicates that there are i fault gates in t logic gates; the symbol

It is used to judge _whether the two vectors before and after the symbol are equal. If they are _equal , output 1; if they are not equal, _output 0; the corresponding output vector;

Simplify formula (6) to get:

In formula (7), T _i represents the probability that the output vector is correct when the number of fault gates is i;

The number of fault gates in the circuit satisfies the random variable of Bernoulli distribution, and we get:

Substitute formula (7) into formula (8) to get:

The second step is to perform single _- fault simulation on the circuit to obtain the T1 value;

The third step is to perform a double fault simulation on the circuit to obtain the T ₂ value;

The fourth step is to calculate the reliability boundary of the circuit;

According to T ₀ =1, formula (9) is rewritten as:

表示为所述电路可靠性的i阶分量之和，其中i＝(1，2，...，t)；In Equation (10), (1-f) ^t represents a conservative lower limit for the reliability of the circuit,

Expressed as the sum of the i-order components of the circuit reliability, where i=(1, 2, . . . , t);

According to formula (10), it can be obtained that the first-order component and the second-order component of the circuit reliability are:

According to formula (10), formula (11) and formula (12), the reliability first-order lower limit value R _lower1 , the reliability first-order upper limit value R _upper1 , the reliability second-order lower limit value R _lower2 and The reliability second-order upper limit value R _upper2 is:

R _lower1 = (1-f) ^t + R ₁ (13)

R _lower2 = (1-f) ^t +R ₁ +R ₂ (15)

The method for calculating the reliability boundary of a logic circuit affected by soft errors provided by the first aspect of the present invention has at least the following beneficial effects:

The invention utilizes the probability distribution model of the soft error of the logic circuit, firstly expresses the circuit reliability target in the form of the sum of multi-order components; then simulates the working conditions of the circuit when a single fault and double faults occur respectively, and calculates the single fault and double faults. The probability of correct output of the circuit when fault occurs; finally calculate the conservative lower limit, first-order upper limit, first-order lower limit, second-order upper limit and second-order lower limit of circuit reliability.

This method combines the idea of fault injection and simulation and the probability distribution model, which can not only deal with the situation of multiple transient faults, but also solve the signal correlation problem caused by the fan-out re-convergence structure. At the same time, since the relationship between calculation speed and accuracy can be well balanced, the method provided by the present invention is also applicable to the soft error reliability calculation of large-scale, ultra-large-scale or even larger-scale logic circuits.

Further, performing single-fault simulation on the circuit to obtain the T1 value, further comprising:

setting a number of random input vectors and a count variable in the circuit;

Record the normal output vectors obtained by simulating operation of all input vectors in the circuit, traverse all logic gates, and set all logic gates as fault gates one by one;

If the current logic gate is set as the fault gate, the fault gate is transformed into the corresponding inverse gate, and the abnormal output vector obtained by simulating the operation of the inverse gate in the circuit, if the abnormal output vector is the same as the normal output vector, the count variable Add 1 to restore the current logic gate and simulate the next logic gate;

When the processing of the last logic gate is completed, the correct probability T ₁ of the circuit output in the case of a single fault is calculated.

Further, performing double-fault simulation _on the circuit to obtain the T2 value, further comprising:

setting a number of random input vectors, a number of random double fault logic gates, and a count variable in the circuit;

Record the normal output vectors obtained by simulating the operation of all input vectors in the circuit, traverse all the double-fault logic gates in all the input vectors, and simulate the double-fault logic gates one by one;

Transform the current dual fault logic gates into their corresponding opposite gates, and simulate the abnormal output vector obtained by the operation of the opposite gate in the circuit. If the abnormal output vector is the same as the normal output vector, the count variable is incremented by 1, and the current dual fault output vector is restored. Fault logic gate, simulating the next double fault logic gate;

When the double-fault logic gates are all processed, the correct probability T ₂ of the circuit output under the double-fault situation is calculated.

A second aspect of the present invention provides a logic circuit reliability boundary calculation device affected by soft errors, applied to a combinational logic circuit, including: a multi-stage component setting unit, a single-fault simulation unit, a double-fault simulation unit, and a reliable Sex boundary calculation unit;

The multi-stage component setting unit is used to express the circuit reliability target as the sum of the multi-stage components;

Assuming that the circuit has t logic gates that are independent of each other and all fail with a certain probability f, let the reliability R of the circuit be:

In formula (5), p(k=i) represents the probability that the number of fault gates is i; 2 ^m represents the number of input vectors; Y represents the output vector; X _w represents the wth input vector; p(X _w ) represents the input The probability that the vector is _Xw ; p(Y is the correct logical value _Xw , k=i) indicates the probability that the output vector is correct when the input vector is _Xw and the number of fault gates is i;

Rewrite equation (5) as:

表示在t个逻辑门中出现i个故障门的组合数，Y(G_t(i)：j；X_w)表示输入向量为X_w，故障门数量为i，组合数为j时对应的输出向量；G_t(i)表示在t个逻辑门中存在有i个故障门；符号

用于判断符号前后两个向量是否相等，若相等，则输出1；若不相等，则输出0；Y(G_t(0)；X_w)表示输入向量为X_w，故障门数量为0时对应的输出向量；In formula (6),

Indicates the number of combinations of i fault gates in t logic gates, Y(G _t (i): j; X _w ) represents the input vector X _w , the number of fault gates i, and the corresponding output when the number of combinations is j vector; G _t (i) indicates that there are i fault gates in t logic gates; the symbol

It is used to judge _whether the two vectors before and after the symbol are equal. If they are _equal , output 1; if they are not equal, _output 0; the corresponding output vector;

Simplify formula (6) to get:

In formula (7), T _i represents the probability that the output vector is correct when the number of fault gates is i;

The number of fault gates in the circuit satisfies the random variable of Bernoulli distribution, and we get:

Substitute formula (7) into formula (8) to get:

The single-fault simulation unit is used to perform single _- fault simulation on the circuit to obtain the T1 value;

The double-fault simulation unit is used to perform double-fault simulation _on the circuit to obtain the T2 value;

The reliability boundary calculation unit is used to calculate the reliability boundary of the circuit;

According to T ₀ =1, formula (9) is rewritten as:

表示为所述电路可靠性的i阶分量之和，其中i＝(1，2，...，t)；In Equation (10), (1-f) ^t represents a conservative lower limit for the reliability of the circuit,

Expressed as the sum of the i-order components of the circuit reliability, where i=(1, 2, . . . , t);

According to formula (10), it can be obtained that the first-order component and the second-order component of the circuit reliability are:

According to formula (10), formula (11) and formula (12), the reliability first-order lower limit value R _lower1 , the reliability first-order upper limit value R _upper1 , the reliability second-order lower limit value R _lower2 and The reliability second-order upper limit value R _upper2 is:

R _lower1 = (1-f) ^t + R ₁ (13)

R _lower2 = (1-f) ^t +R ₁ +R ₂ (15)

The device for calculating the reliability boundary of a logic circuit affected by soft errors provided by the second aspect of the present invention has at least the following beneficial effects:

The device can be used to execute the method for calculating the reliability boundary of a logic circuit affected by soft errors described in the first aspect of the present invention. Through the device, the relationship between calculation speed and accuracy can be better balanced, and the device can be used for large-scale , very large-scale and even larger-scale logic circuits provide soft-error reliability calculations.

Further, the single-fault simulation unit further includes: a first setting unit, a first simulation unit and a first calculation unit;

The first setting unit is used to set the number of random input vectors and a counting variable in the circuit;

The first simulation unit is used for recording normal output vectors obtained by simulating all input vectors in the circuit, traversing all logic gates, and setting all logic gates as fault gates one by one;

If the current logic gate is set as the fault gate, the fault gate is transformed into the corresponding inverse gate, and the abnormal output vector obtained by simulating the operation of the inverse gate in the circuit, if the abnormal output vector is the same as the normal output vector, the count variable Add 1 to restore the current logic gate and simulate the next logic gate;

The first calculation unit is configured to calculate the correct probability T ₁ of the circuit output in the case of a single fault after the processing of the last logic gate is completed.

Further, the double-fault simulation unit further includes: a second setting unit, a second simulation unit and a second calculation unit;

The second setting unit is used to set the number of random input vectors, the number of random double fault logic gates and the counting variable in the circuit;

The second simulation unit is used to record the normal output vectors obtained by simulating operation of all input vectors in the circuit, traverse all the double-fault logic gates in all the input vectors, and simulate the double-fault logic gates one by one;

Transform the current dual fault logic gates into their corresponding opposite gates, and simulate the abnormal output vector obtained by the operation of the opposite gate in the circuit. If the abnormal output vector is the same as the normal output vector, the count variable is incremented by 1, and the current dual fault output vector is restored. Fault logic gate, simulating the next double fault logic gate;

The second calculation unit is configured to calculate the correct probability T ₂ of the circuit output in the case of double faults after all processing of the double fault logic gates is completed.

In a third aspect of the present invention, there is provided a logic circuit reliability boundary computing device affected by soft errors, comprising at least one control processor and a memory for communicating with the at least one control processor; the memory stores there are instructions executable by the at least one control processor, the instructions being executed by the at least one control processor to enable the at least one control processor to perform a soft error-sensitive as described in the first aspect of the present invention Affecting logic circuit reliability boundary calculation method.

A fourth aspect of the present invention provides a computer-readable storage medium, characterized in that: the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to cause a computer to execute the method according to the fourth aspect of the present invention. In one aspect, a method for calculating the reliability boundary of a logic circuit affected by soft errors is described.

Description of drawings

Below in conjunction with accompanying drawing and embodiment, the present invention is further described;

1 is a schematic structural diagram of a combinational logic module provided by an embodiment of the present invention;

FIG. 2 is a schematic flowchart of a method for calculating a reliability boundary of a logic circuit affected by soft errors according to an embodiment of the present invention.

3 is a schematic structural diagram of an apparatus for calculating the reliability boundary of a logic circuit affected by soft errors according to an embodiment of the present invention;

Fig. 4 is a further structural schematic diagram of the single-fault simulation unit in Fig. 3;

Fig. 5 is a further structural schematic diagram of the double-fault simulation unit in Fig. 3;

6 is a schematic structural diagram of a logic circuit reliability boundary computing device affected by soft errors according to an embodiment of the invention;

7 is a schematic diagram of comparison between the time required to calculate T ₁ and T ₂ in the method for calculating the reliability boundary of a logic circuit affected by soft errors provided by an embodiment of the present invention and a fault simulation method;

FIG. 8 is a schematic diagram of a comparison between the reliability boundary value of an experimental circuit and R in the method for calculating the reliability boundary of a logic circuit affected by soft errors according to an embodiment of the present invention.

Detailed ways

This part will describe the specific embodiments of the present invention in detail, and the preferred embodiments of the present invention are shown in the accompanying drawings. Each technical feature and overall technical solution of the invention should not be construed as limiting the protection scope of the invention.

For ease of understanding, the soft error reliability is described below:

The soft error reliability of a combinational logic circuit is defined as the probability that the logic values of all outputs of the circuit remain correct under the influence of soft errors.

Referring to the combinational logic circuit with m inputs and n outputs as shown in FIG. 1, the circuit reliability R can be expressed as:

In formula (1), X and Y represent the input vector and output vector of the circuit respectively; p(X) represents the probability that the input vector is X, and p(Y is the correct logical value |X) represents the case where the input vector is X , the probability that the output vector Y is correct.

When all input vectors occur with equal probability, R can be expressed as:

In formula (2), X _w represents the w-th input vector; 2 ^m represents the number of input vectors; for example, the 0- ^th input vector represents a vector with all input bits 0; Refers to a vector with all input bits set to 1.

比较两个向量是否相等：若

表示向量Y_i和Y_j等长且各位对应相等。若施加至电路的输入向量为X_w，且有k个逻辑门发生故障，此时电路还能正常输出需满足的条件是：This embodiment uses a fault gate model, that is, all logic gates fail with a certain probability f, and whether the output of each gate is correct or not is independent of each other. The states of all logic gates are represented by a vector G=(g ₁ , g ₂ , ..., g _t ), where g ₁ =0 or 1, (i=1, 2, ..., t), t represents The total number of logic gates in the circuit, _gi = 0 indicates that the ith logic gate is in a normal state, and _gi = 1 indicates that the gate is faulty. Then use G _t (k) to indicate that the vector G with a total of t bits contains k 1s, that is, the circuit has k gates that fail at the same time. Use the exclusive or not (exclusive or) operator

Compares two vectors for equality: if

Indicates that the vectors Y _i and Y _j are of equal length and the corresponding bits are equal. If the input vector applied to the circuit is X _w , and k logic gates fail, the conditions that the circuit can still output normally are:

Referring to FIG. 2, an embodiment of the present invention provides a method for calculating the reliability boundary of a logic circuit affected by soft errors, applied to a combinational logic circuit, including the following steps:

S100, expressing the circuit reliability target as the sum of multi-stage components;

Depending on the number of failures, the circuit reliability R is expressed as:

Among them, p(k=i) represents the probability that the number of faulty gates is i, and p(Y is the correct logic value|k=i) represents the probability that the output vector is correct when the number of faulty logic gates is i.

Rewrite R as:

使用Y(G_t(i)：j；X_w)

表示输入向量为X_w，且i个逻辑门发生故障时，输出向量对应的一种组合情况(情况j)。公式(5)可表示为：Among them, X _w represents the w-th input vector; p(X _w ) represents the probability that the input vector is X _w ; p (Y is the correct logical value |X _w , k=i) represents the number of faulty logic gates i, And when the input vector is X _w , the probability that the output vector is correct. Considering that the number of combinations of i fault gates in the t logic gates of the circuit is

Use Y(Gt(i): _j ; _Xw )

It represents a combination situation (case j) corresponding to the output vector when the input vector is X _w and i logic gates fail. Formula (5) can be expressed as:

表示在t个逻辑门中出现i个故障门的组合数，Y(G_t(i)：j；X_w)表示输入向量为X_w，故障门数量为i，组合数为j时对应的输出向量；G_t(i)表示在t个逻辑门中存在有i个故障门；符号

用于判断符号前后两个向量是否相等，若相等，则输出1；若不相等，则输出0；Y(G_t(0)；X_w)表示输入向量为X_w，故障门数量为0时对应的输出向量；In formula (6),

Indicates the number of combinations of i fault gates in t logic gates, Y(G _t (i): j; X _w ) represents the input vector X _w , the number of fault gates i, and the corresponding output when the number of combinations is j vector; G _t (i) indicates that there are i fault gates in t logic gates; the symbol

It is used to judge _whether the two vectors before and after the symbol are equal. If they are _equal , output 1; if they are not equal, _output 0; the corresponding output vector;

Simplify formula (6) to get:

Among them, T _i represents the probability that the output vector of the circuit is correct when the number of faulty logic gates is i.

Since the error probability of each logic gate is independent of each other, and the error probability is f, the number of failed logic gates satisfies the random variable of Bernoulli distribution. Therefore:

After combining and simplifying formula (7) and formula (8), it can be expressed as:

S200. Perform single _- fault simulation on the circuit to obtain the T1 value;

The purpose _of this step is to get the T1 value. As a kind of embodiment, the concrete method of step is as follows:

(1) Set the number of random input vectors and counting variables in the circuit;

(2) record the normal output vectors obtained by simulating operation of all input vectors in the circuit, traverse all logic gates, and set all logic gates as fault gates one by one;

(3) If the current logic gate is set as the fault gate, the fault gate is transformed into the corresponding opposite gate, and the abnormal output vector obtained by simulating the operation of the opposite gate in the circuit, if the abnormal output vector is the same as the normal output vector, Then the count variable is incremented by 1, the current logic gate is restored, and the next logic gate is simulated;

(4) After the processing of the last logic gate is completed, calculate the correct probability T ₁ of the circuit output in the case of a single fault.

In order to facilitate understanding, the following description of the "reverse gate":

The AND gate and the NAND gate are mutually "opposite gates"; the OR gate and the NOR gate are mutually "opposite gates"; the XOR gate and the XOR gate are mutually "opposite gates"; the "opposite gate" of the NOT gate is the buffer gate .

S300. Perform double-fault simulation on the circuit to obtain the T ₂ value;

_The purpose of this step is to obtain the T2 value. As an embodiment, the steps are as follows:

(1) The number of random input vectors, the number of random double fault logic gates and the counting variable are set in the circuit;

(2) record the normal output vectors obtained by simulating the operation of all input vectors in the circuit, traverse all the double-fault logic gates in all the input vectors, and simulate the double-fault logic gates one by one;

(3) Transform the current dual-fault logic gates into their corresponding opposite gates, and simulate the abnormal output vector obtained by the operation of the opposite gate in the circuit. If the abnormal output vector is the same as the normal output vector, the count variable is incremented by 1 and restored The current double-fault logic gate simulates the next double-fault logic gate;

(4) After the double-fault logic gates are all processed, calculate the correct probability T ₂ of the circuit output in the double-fault case.

S400. Calculate the reliability boundary of the circuit;

Since T ₀ =1, formula (9) is rewritten as:

可认为是可靠性R的i(i＝1,2,...,t)阶分量之和。Here, (1-f) ^t is denoted as Rc-lower, which represents a conservative lower limit of circuit reliability. The second half of formula (10)

It can be considered as the sum of the i (i=1, 2, . . . , t) order components of the reliability R.

For example: the 1st and 2nd order components of R are expressed as:

The various boundaries and corresponding expressions of logic circuit reliability are defined as follows:

The first-order lower bound of reliability is:

R _lower1 =R _c-lower +R ₁ (13)

The first-order upper bound for reliability is:

The second-order lower bound of reliability is:

R _lower2 =R _c-lower +R ₁ +R ₂ (15)

The second-order upper limit of reliability is:

According to the above-mentioned steps 1 to 4, the first-order upper and lower limit values and the second-order upper and lower limit values of the reliability of the logic circuit can be calculated. The circuit reliability R is already very close, and as the probability f of failure of a single logic cell continues to decrease, these boundary values are closer to the true reliability of the circuit.

In order to demonstrate this method, Figures 7 and 8 are experimental results of this method.

In Figure 7, the abscissa represents 6 experimental circuits of different scales; the ordinate is the logarithmic coordinate, representing the simulation time, in seconds; the leftmost in the bar graph represents T ₁ , the middle represents T ₂ , and the far right represents the fault simulation . For 6 experimental circuits of different scales, the time required to calculate T ₁ and T ₂ using this method is much lower than the time required by the fault simulation method. It takes time. In Figure 8, f is set to 1e-4 according to the CMOS circuit technology level; the abscissa represents five experimental circuits of different scales; the ordinate represents the reliability value. R _lower1 indicates the first-order lower limit of reliability; R _upper1 indicates the first-order upper limit of reliability; R _lower2 indicates the second-order lower limit of reliability; R _upper2 indicates the second-order upper limit of reliability; PGM-Simulation indicates the circuit reliability R obtained by simulation.

Further, for a sequential logic circuit with a full scan structure, since the circuit flip-flops are replaced by scan flip-flops, all input signals, including the outputs of the scan flip-flops, are controllable, and all output signals include the input of the scan flip-flops. are all observable. Therefore, the method used in this embodiment is also applicable to the sequential logic circuit of the full scan structure.

Compared with the prior art, this embodiment uses a probability distribution model, firstly expressing the reliability target of large-scale and ultra-large-scale logic circuits to be calculated as the sum of multi-order components; then transforming the fault gate into the corresponding " The method of "reverse gate" simulates the working conditions of single-fault and double-fault circuits, so as to calculate the correct output probability of the circuit when the fault occurs; finally, the first-order and second-order reliability of the circuit can be obtained by substituting the simulation results into the reliability boundary expression. upper and lower limit.

According to the probability model, this method only considers the single-fault and double-fault situations, and uniformly calculates the three-fault and above conditions into the reliability boundary value, which not only ensures sufficient accuracy, but also greatly saves the calculation time; In the process of considering single fault and double fault, because of the fault simulation method, this method can solve the problem of signal correlation very well.

This method combines the idea of fault injection and simulation and the probability distribution model, which can not only deal with the situation of multiple transient faults, but also solve the signal correlation problem caused by the fan-out re-convergence structure. At the same time, because the relationship between calculation speed and accuracy can be well balanced, it can be applied to the reliability calculation of large-scale and ultra-large-scale logic circuits.

3 to 5, another embodiment of the present invention provides a logic circuit reliability boundary calculation device 1000 affected by soft errors, applied to a combinational logic circuit, including: a multi-stage component setting unit 1100, a single a fault simulation unit 1200, a double fault simulation unit 1300, and a reliability boundary calculation unit 1400;

The multi-stage component setting unit 1100 is used to express the circuit reliability target as the sum of the multi-stage components;

It is assumed that the circuit has t logic gates that are independent of each other and all fail with a certain probability f, so that the reliability R of the circuit is:

In formula (5), p(k=i) represents the probability that the number of fault gates is i; 2 ^m represents the number of input vectors; Y represents the output vector; X _w represents the wth input vector; p(X _w ) represents the input The probability that the vector is _Xw ; p(Y is the correct logical value _Xw , k=i) indicates the probability that the output vector is correct when the input vector is _Xw and the number of fault gates is i;

Rewrite equation (5) as:

表示在t个逻辑门中出现i个故障门的组合数，Y(G_t(i)：j；X_w)表示输入向量为X_w，故障门数量为i，组合数为j时对应的输出向量；G_t(i)表示在t个逻辑门中存在有i个故障门；符号

用于判断符号前后两个向量是否相等，若相等，则输出1；若不相等，则输出0；Y(G_t(0)；X_w)表示输入向量为X_w，故障门数量为0时对应的输出向量；In formula (6),

Indicates the number of combinations of i fault gates in t logic gates, Y(G _t (i): j; X _w ) represents the input vector X _w , the number of fault gates i, and the corresponding output when the number of combinations is j vector; G _t (i) indicates that there are i fault gates in t logic gates; the symbol

It is used to judge _whether the two vectors before and after the symbol are equal. If they are _equal , output 1; if they are not equal, _output 0; the corresponding output vector;

Simplify formula (6) to get:

In formula (7), T _i represents the probability that the output vector is correct when the number of fault gates is i;

The number of fault gates in the circuit satisfies the random variable of Bernoulli distribution, we get:

Substitute formula (7) into formula (8) to get:

The single-fault simulation unit 1200 is used to perform single _- fault simulation on the circuit to obtain the T1 value;

The double-fault simulation unit 1300 is used to simulate _double -faults on the circuit to obtain the T2 value;

The reliability boundary calculation unit 1400 is used to calculate the reliability boundary of the circuit;

According to T ₀ =1, formula (9) is rewritten as:

表示为电路可靠性的i阶分量之和，其中i＝(1，2，...，t)；In equation (10), (1-f) ^t represents the conservative lower limit of circuit reliability,

Expressed as the sum of the i-order components of circuit reliability, where i=(1, 2, . . . , t);

According to formula (10), the first-order component and second-order component of circuit reliability can be obtained as:

According to formula (10), formula (11) and formula (12), the reliability first-order lower limit value R _lower1 , the reliability first-order upper limit value R _upper1 , the reliability second-order lower limit value R _lower2 and the reliability of the circuit are obtained according to formula (10), formula (11) and formula (12). The second-order upper limit values R _upper2 are:

R _lower1 = (1-f) ^t + R ₁ (13)

R _lower2 = (1-f) ^t +R ₁ +R ₂ (15)

Further, the single-fault simulation unit 1200 further includes: a first setting unit 1210, a first simulation unit 1220 and a first calculation unit 1230;

The first setting unit 1210 is used to set the number of random input vectors and counting variables in the circuit;

The first simulation unit 1220 is used to record the normal output vectors obtained by simulating operation of all input vectors in the circuit, traverse all logic gates, and set all logic gates as fault gates one by one;

If the current logic gate is set as the fault gate, the fault gate is transformed into the corresponding inverse gate, and the abnormal output vector obtained by simulating the operation of the inverse gate in the circuit, if the abnormal output vector is the same as the normal output vector, the count variable is incremented by 1 , restore the current logic gate and simulate the next logic gate;

The first calculation unit 1230 is configured to calculate the correct probability T ₁ of the circuit output in the case of a single fault after the processing of the last logic gate is completed.

Further, the double-fault simulation unit 1300 further includes: a second setting unit 1310, a second simulation unit 1320 and a second calculation unit 1330;

The second setting unit 1310 is used to set the number of random input vectors, the number of random double-fault logic gates and the counting variable in the circuit;

The second simulation unit 1320 is configured to record the normal output vectors obtained by simulating the operation of all input vectors in the circuit, traverse all the double-fault logic gates in all the input vectors, and simulate the double-fault logic gates one by one;

Transform the current double-fault logic gates into their corresponding opposite gates, and simulate the abnormal output vector obtained by the operation of the opposite gate in the circuit. If the abnormal output vector is the same as the normal output vector, the count variable is incremented by 1 to restore the current double-fault logic. gate to simulate the next double fault logic gate;

The second calculation unit 1330 is configured to calculate the correct probability T ₂ of the circuit output in the case of double faults after all the processing of the double fault logic gates is completed.

It should be noted that, since the device for calculating the reliability boundary of a logic circuit affected by soft errors in this embodiment and the above-mentioned method for calculating the reliability boundary of a logic circuit affected by soft errors are based on the same inventive concept, therefore, Corresponding contents in the method embodiments are also applicable to the device embodiments, and will not be described in detail here.

6, another embodiment of the present invention also provides a logic circuit reliability boundary computing device 6000 affected by soft errors; the device can be any type of intelligent terminal, such as a mobile phone, a tablet computer, a personal computer, etc. .

Specifically, the device includes: one or more control processors 6001 and a memory 6002. In FIG. 6, a control processor 6001 and a memory 6002 are taken as an example. The control processor 6001 and the memory 6002 can be connected by a bus or in other ways. In FIG. 6, the connection through the bus is taken as an example.

The memory 6002, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs and modules, such as a logic circuit affected by soft errors in an embodiment of the present invention Program instructions/modules corresponding to the reliability boundary computing device, the control processor 6001 executes the logic circuit reliability boundary computing device 1000 affected by the soft error by running the non-transitory software programs, instructions and modules stored in the memory 6002 Various functional applications and data processing of , that is, the method for calculating the reliability boundary of a logic circuit affected by soft errors in the above method embodiments.

The memory 6002 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required by at least one function; the storage data area may store the computing device 1000 according to the reliability boundary of the logic circuit affected by soft errors using the created data, etc. Additionally, memory 6002 may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, memory 6002 may optionally include memory located remotely from control processor 6001 that may be connected to the soft error affected logic circuit reliability boundary computing device 6000 via a network. Examples of such networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

One or more modules are stored in the memory 6002, and when executed by the one or more control processors 6001, execute a method for calculating the reliability boundary of a logic circuit affected by soft errors in the above method embodiments, for example, executing The method steps S100 to S400 in FIG. 2 described above.

Another embodiment of the present invention further provides a computer-readable storage medium, where the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to cause a computer to execute a software-controlled storage medium as described above. The error-affected logic circuit reliability boundary calculation method, for example, executes the method steps S100 to S400 in FIG. 2 described above.

The apparatus embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

From the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a general hardware platform. Those skilled in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium. When the program is executed, A flow as an embodiment of the above-described method may be included. The storage medium may be a magnetic disk, an optical disk, a read only memory (Read Only Memory, ROM), or a random access memory (Random Access Memory, RAM) or the like.

The embodiments of the present invention have been described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned embodiments, and within the scope of knowledge possessed by those of ordinary skill in the technical field, various changes can also be made without departing from the purpose of the present invention. .

Claims (8)

1. A method for calculating the reliability boundary of a logic circuit affected by a soft error is applied to a combinational logic circuit and is characterized by comprising the following steps:

a first step of representing a circuit reliability target as a sum of multi-stage components;

setting t logic gates of the circuit to be mutually independent and generate faults with a specific probability f, and enabling the reliability R of the circuit to be as follows:

in formula (5), p (k ═ i) represents the probability that the number of failed gates is i; 2^mRepresenting the number of input vectors; y represents an output vector; x_wRepresents the w-th input vector; p (X)_w) Representing the input vector as X_wThe probability of (d); p (Y is the correct logical value | X)_wK ═ i) denotes that the input vector is X_wWhen the number of the fault gates is i, outputting the probability of vector correctness;

rewrite equation (5) to:

in the formula (6), the first and second groups of the compound,

indicating the number of combinations of i faulty gates out of t logic gates, Y (G)_t(i)：j；X_w) Representing the input vector as X_wThe corresponding output vector when the number of the fault gates is i and the combination number is j; g_t(i) Indicating that there are i failed gates out of the t logic gates; symbol

The method is used for judging whether the two vectors before and after the symbol are equal, and if so, outputting 1; if not, outputting 0; y (G)_t(0)；X_w) Representing the input vector as X_wOutput vectors corresponding to the number of the fault gates being 0;

reducing equation (6) yields:

in the formula (7), T_iWhen the number of the fault gates is i, the probability of the correct vector is output;

the number of failed gates of the circuit meets the random variable of Bernoulli distribution, and the following results are obtained:

substituting equation (7) into equation (8) yields:

second step, pairThe circuit performs single fault simulation to obtain T₁A value;

thirdly, performing double-fault simulation on the circuit to obtain T₂A value;

fourthly, calculating a reliability boundary of the circuit;

according to T₀When 1, formula (9) is rewritten as:

in the formula (10), (1-f)^tA conservative lower limit value representing the reliability of the circuit,

expressed as the sum of the i-th order components of the circuit reliability, where i is 1,2, …, t;

the 1 st order component and the 2 nd order component of the circuit reliability can be obtained according to the formula (10) as follows:

obtaining a first-order reliability lower limit value R of the circuit according to the formula (10), the formula (11) and the formula (12)_lower1First order upper limit of reliability R_upper1Second order lower limit of reliability R_lower2And a second order upper limit value R of reliability_upper2Respectively as follows:

R_lower1＝(1-f)^t+R₁ (13)

R_lower2＝(1-f)^t+R₁+R₂ (15)

2. the method of claim 1, wherein said single fault simulation of said circuit to obtain T is performed to obtain a reliability bound of said logic circuit affected by soft errors₁Values, further comprising:

setting the number of random input vectors and a counting variable in the circuit;

recording normal output vectors obtained by simulating the operation of all input vectors in the circuit, traversing all logic gates, and setting all logic gates as fault gates one by one;

if the current logic gate is set as a fault gate, the fault gate is converted into a corresponding opposite gate, an abnormal output vector obtained by the operation of the opposite gate in the circuit is simulated, if the abnormal output vector is the same as the normal output vector, the counting variable is increased by 1, the current logic gate is recovered, and the next logic gate is simulated;

when the last logic gate is processed, the probability T that the circuit outputs correctly under the condition of single fault is calculated₁。

3. The method of claim 1, wherein the performing double-fault simulation on the circuit to obtain T is characterized in that₂Values, further comprising:

setting the number of random input vectors, the number of random double-fault logic gates and a counting variable in the circuit;

recording normal output vectors obtained by simulating operation of all input vectors in the circuit, traversing all double-fault logic gates in all the input vectors, and simulating the double-fault logic gates one by one;

converting the current double-fault logic gate into respective corresponding opposite gates, simulating an abnormal output vector obtained by the operation of the opposite gates in the circuit, if the abnormal output vector is the same as the normal output vector, adding 1 to the counting variable, recovering the current double-fault logic gate, and simulating the next double-fault logic gate;

when the double-fault logic gate is completely processed, the probability T that the circuit outputs the correct output under the condition of double faults is calculated₂。

4. A logic circuit reliability boundary calculation device affected by soft errors, applied to a combinational logic circuit, is characterized by comprising: a multi-stage component setting unit, a single-fault simulation unit, a double-fault simulation unit and a reliability boundary calculation unit;

the multi-stage component setting unit is used for representing the circuit reliability target as the sum of the multi-stage components;

setting t logic gates of the circuit to be mutually independent and generate faults with a specific probability f, and enabling the reliability R of the circuit to be as follows:

in equation (5), p (k ═ i) represents the probability 2 that the number of faulty gates is i^mRepresenting the number of input vectors; y represents an output vector; x_wRepresents the w-th input vector; p (X)_w) Representing the input vector as X_wThe probability of (d); p (Y is the correct logical value X)_wK ═ i) denotes that the input vector is X_wWhen the number of the fault gates is i, outputting the probability of vector correctness;

rewrite equation (5) to:

in the formula (6), the first and second groups,

indicating the number of combinations of i faulty gates out of t logic gates, Y (G)_t(i)：j；X_w) Representing the input vector as X_wThe corresponding output vector when the number of the fault gates is i and the combination number is j; g_t(i) Indicating that there are i failed gates out of the t logic gates; symbol

The method is used for judging whether the front vector and the rear vector of the symbol are equal or not, and if so, outputting 1; if not, outputting 0; y (G)_t(0)；X_w) Representing the input vector as X_wThe corresponding output vector when the number of the fault gates is 0;

reducing equation (6) yields:

in the formula (7), T_iWhen the number of the fault gates is i, the probability of the correct vector is output;

the number of failed gates of the circuit meets the random variable of Bernoulli distribution, and the following results are obtained:

substituting equation (7) into equation (8) yields:

the single fault simulation unit is used for carrying out single fault simulation on the circuit to obtain T₁A value;

the double-fault simulation unit is used for carrying out double-fault simulation on the circuit to obtain T₂A value;

the reliability boundary calculation unit is used for calculating the reliability boundary of the circuit;

according toT₀When 1, formula (9) is rewritten as:

in the formula (10), (1-f)^tA conservative lower limit value representing the reliability of the circuit,

expressed as the sum of the i-th order components of the circuit reliability, where i is 1,2, …, t;

the 1 st order component and the 2 nd order component of the circuit reliability can be obtained according to the formula (10) as follows:

obtaining a first-order reliability lower limit value R of the circuit according to the formula (10), the formula (11) and the formula (12)_lower1First order upper limit of reliability R_upper1Second order lower limit of reliability R_lower2And a second order upper limit value R of reliability_upper2Respectively as follows:

R_lower1＝(1-f)^t+R₁ (13)

R_lower2＝(1-f)^t+R₁+R₂ (15)

5. the soft-error affected logic circuit reliability boundary computation apparatus of claim 4, wherein the single-fault simulation cell further comprises: the device comprises a first setting unit, a first simulation unit and a first calculation unit;

the first setting unit is used for setting the number of random input vectors and a counting variable in the circuit;

the first simulation unit is used for recording normal output vectors obtained by simulating operation of all input vectors in the circuit, traversing all logic gates and setting all logic gates as fault gates one by one;

if the current logic gate is set as a fault gate, the fault gate is converted into a corresponding opposite gate, an abnormal output vector obtained by the operation of the opposite gate in the circuit is simulated, if the abnormal output vector is the same as the normal output vector, the counting variable is increased by 1, the current logic gate is recovered, and the next logic gate is simulated;

the first calculating unit is used for calculating the probability T of the circuit output correctness under the condition of single fault after the last logic gate finishes the processing₁。

6. The soft-error affected logic circuit reliability boundary computation apparatus of claim 4, wherein the double-fault simulation unit further comprises: the device comprises a second setting unit, a second simulation unit and a second calculation unit;

the second setting unit is used for setting the number of random input vectors, the number of random double-fault logic gates and a counting variable in the circuit;

the second simulation unit is used for recording normal output vectors obtained by simulating operation of all input vectors in the circuit, traversing all double-fault logic gates in all input vectors and simulating the double-fault logic gates one by one;

converting the current double-fault logic gate into respective corresponding opposite gates, simulating an abnormal output vector obtained by the operation of the opposite gates in the circuit, if the abnormal output vector is the same as the normal output vector, adding 1 to the counting variable, recovering the current double-fault logic gate, and simulating the next double-fault logic gate;

the second calculating unit is used for calculating the probability T that the circuit outputs the correct output under the condition of double faults after the double-fault logic gate finishes all processing₂。

7. A logic circuit reliability boundary computation device affected by soft errors, characterized by: comprises at least one control processor and a memory for communicative connection with the at least one control processor; the memory stores instructions executable by the at least one control processor to enable the at least one control processor to perform a soft error affected logic circuit reliability boundary calculation method as claimed in any one of claims 1 to 3.

8. A computer-readable storage medium characterized by: the computer-readable storage medium stores computer-executable instructions for causing a computer to perform a soft-error affected logic circuit reliability boundary calculation method as recited in any one of claims 1-3.

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