CN111008102B - FPGA accelerator card high-speed interface SI test control device, system and method - Google Patents

Abstract

The present invention provides an FPGA accelerator card high-speed interface SI test control device, system and method. The SI test control device for the high-speed interface of the FPGA accelerator card based on the SOC device includes a user interaction interface and a high-speed interface controller. The user interaction The interface is connected with a pattern switching processing unit through the pattern selection unit; the pattern switching processing unit is connected with a high-speed interface controller; the high-speed interface controller is also connected with a high-speed interface mode configuration unit; the pattern switching processing unit , for generating the configuration information of the corresponding code type according to the judgment of the code type selection unit and outputting it to the high-speed interface controller; the high-speed interface controller is used for according to the information from the high-speed interface mode configuration unit and the code type switching processing unit The configuration information works in the corresponding mode to realize the sending and receiving of high-speed interface data.

Description

FPGA accelerator card high-speed interface SI test control device, system and method

technical field

The invention relates to the technical field of signal integrity testing, in particular to an FPGA accelerator card high-speed interface SI test control device, system and method.

Background technique

Artificial intelligence is one of the most cutting-edge hot technologies at present. FPGA accelerator cards based on SOC devices are widely used in the field of artificial intelligence because of their high-performance computing capabilities. Programmable SOC devices that integrate processor software and FPGA hardware are used to realize artificial intelligence. Technology provides strong support. SOC devices effectively improve the integration, performance, flexibility, and scalability of the system, allowing designers to flexibly add different peripherals and hardware accelerators according to different application scenarios, so as to achieve optimization and differentiation goals. The advantages of rich peripherals and high-speed interfaces also mean that the demand for FPGA accelerator card hardware design and signal integrity is getting higher and higher.

Signal integrity is a series of metrics for the quality of electronic signals. It usually refers to the phenomenon that the signal is distorted and distorted due to the interaction of various factors such as high-speed signal wiring, component layout, and power supply quality in high-speed PCBs. Generally, the high-speed interfaces of FPGA accelerator cards include DDR, USB, PCIE, Ethernet ports, etc. As an external bus standard, USB is used to regulate the connection and communication between computers and external devices. The rapid development of computer technology promotes the improvement of the bus standard. At present, the transmission rate of the ultra-high-speed interface USB3.0 can reach 5Gbps. For this high-speed interface, signal integrity testing is an important part of ensuring the quality of hardware products.

The current conventional method is to test the signal integrity of the USB interface with an oscilloscope, and connect the oscilloscope probe to the USB interface to be tested through a fixture. Among them, the USB3.0 TX test requires the USB interface to be tested to send a variety of standard-compliant packets (including at least CP0, CP1, and LFPS three patterns), and then use the oscilloscope to test the eye diagram to complete the test. In the past, the USB interface SI test of server products can be configured by customizing the BIOS to send the packet pattern. For the FPGA accelerator card, there is currently no specific packet sending control tool for the USB interface SI test. The current method is to complete the test by writing the SOC chip internal register configuration packet sending. The method of writing the internal registers of the SOC device to configure the USB controller to send the contract is completely manual operation, and the degree of automation is low. Since the testers are not familiar with the internal structure and register configuration of the chip, the operation is complicated and error-prone, which seriously affects the progress of the project test. In addition, on-site guidance from R&D personnel is often required, which increases labor costs.

Contents of the invention

For the method of writing the internal register of the SOC device to configure the USB controller to send the contract, it adopts a completely manual operation with a low degree of automation. Since the testers are not familiar with the internal structure and register configuration of the chip, the operation is complicated and error-prone, which seriously affects the progress of the project test. In addition, on-site guidance from R&D personnel is often required, which increases the problem of labor costs. The present invention provides an FPGA accelerator card high-speed interface SI test control device, system and method.

The technical scheme provided by the invention is:

On the one hand, the technical solution of the present invention provides a kind of FPGA accelerator card high-speed interface SI test control device, the SI test control device of the high-speed interface of the FPGA accelerator card based on SOC device, including user interaction interface and high-speed interface controller, described user The interactive interface is connected with a pattern switching processing unit through the pattern selection unit; the pattern switching processing unit is connected with a high-speed interface controller; the high-speed interface controller is also connected with a high-speed interface mode configuration unit;

Described user exchange interface is the debugging interface of FPGA accelerator card, starts test, input pre-test code pattern by described user exchange interface;

The high-speed interface mode configuration unit is used to generate different mode configuration information for sending tests;

The code type selection unit is connected to the user interaction interface and the code type switching processing unit; it is used to identify the type of code type input by the operator through the user interaction interface; it is also used to enter the code type after checking the selected code type. The corresponding code pattern processing link;

The code type switching processing unit is used to generate the configuration information of the corresponding code type according to the judgment of the code type selection unit and output it to the high-speed interface controller;

The high-speed interface controller is used to work in a corresponding mode according to the configuration information from the high-speed interface mode configuration unit and the code switching processing unit to realize the sending and receiving of high-speed interface data.

Preferably, the high-speed interface is a USB interface, the high-speed interface controller is a USB controller, and the high-speed interface mode configuration unit is a USB mode configuration unit.

Preferably, the device is based on the built-in ARM processor of the SOC device, and realizes the pattern packet output required for the signal integrity test of the USB interface and the configuration of the USB mode.

Preferably, the USB mode configuration unit is configured to generate mode configuration information, and set the USB controller to a host mode with different mode interface rates for sending tests;

The user exchange interface is also used to print logs through the interface to understand the packet sending status information of the test pattern;

The code type selection unit is connected to the user interaction interface and the code type switching processing unit; it is used to identify the type of code type input by the operator through the user interaction interface; it is also used to enter the code type after checking the selected code type. The corresponding code pattern processing link;

The code type switching processing unit is used to generate configuration information of the corresponding code type according to the judgment of the code type selection unit and output it to the USB controller;

The USB controller is used to work in a corresponding mode according to the configuration information from the USB mode configuration unit and the code switching processing unit to realize the sending and receiving of USB interface data.

In a second aspect, the technical solution of the present invention provides a FPGA accelerator card high-speed interface SI test system, including a high-speed interface SI test control device and an interface link to be tested; the described high-speed interface SI test control device and the interface link to be tested perform Communication connection, the interface link to be tested is used to be connected to the oscilloscope; The described high-speed interface SI test control device is the FPGA accelerator card high-speed interface SI test control device described in the first aspect.

Preferably, the interface link to be tested includes a USB physical layer transceiver and a USB connector, and the USB physical layer transceiver is connected to the USB connector; the USB connector is connected to an oscilloscope;

Described USB physical layer transceiver is connected with USB controller, is used for realizing the interconnection of sending and receiving with the interface link to be tested by the USB controller in the built-in ARM processor of SOC device, completes the transmission pattern of USB interface by oscilloscope test.

Preferably, the interface link to be tested includes a first interface link to be tested and a second interface link to be tested;

The first interface link to be tested includes a first USB physical layer transceiver and a first USB controller, and the first USB physical layer transceiver is connected to the first USB controller;

The second interface link to be tested includes a second USB physical layer transceiver and a second USB controller, and the second USB physical layer transceiver is connected to the second USB controller;

Both the first USB physical layer transceiver and the second USB physical layer transceiver are connected to the USB controller.

In a third aspect, the technical solution of the present invention also provides a method for testing FPGA accelerator card high-speed interface SI, based on the method for testing the FPGA accelerator card high-speed interface SI test system provided in the second aspect, comprising the following steps:

Step 1: Start the test through the user interaction interface, enter the test mode, and select the first interface link to be tested or the second interface link to be tested;

Step 2: The USB mode configuration unit configures the USB controller to be USB3.0, host host mode, so as to carry out the host terminal sending test;

Step 3: Input the code pattern information corresponding to the test pattern through the user interaction interface;

Step 4: The code pattern selection unit outputs instructions to enter the corresponding code pattern processing link after judgment and verification according to the code pattern information input by the user interaction interface;

Step 5: the code type switching processing unit generates the configuration information of the corresponding code type according to the instruction of the code type selection unit according to the working mechanism of the code type jump state machine and outputs it to the USB controller to complete the code type switching process;

Step 6: The USB controller works in the corresponding mode according to the configuration information from the USB mode configuration unit and the code switching processing unit, and outputs the code pattern corresponding to the configuration information through the sending port to the interface chain to be tested selected in step 1 road;

Step 7: The interface link to be tested outputs the standard code pattern to the oscilloscope, and the eye diagram is tested to complete the USB3.0 TX signal integrity test;

Step 8: After the input code pattern test is completed, jump back to step 3 for the next code pattern test.

As can be seen from the above technical solutions, the present invention has the following advantages: for FPGA accelerator cards based on SOC devices, a USB interface signal integrity testing system and method based on SOC built-in ARM systems are provided, which can automatically output USB3. 0 test code pattern, to solve the problem of unclear packet sending method and poor operability encountered in the signal integrity test of the accelerator card USB interface. The method adopts an internal processor, fully utilizes the advantages of the flexibility of the SOC device, has no hardware layout pressure, and is realized on the basis of an existing hardware platform without adding an external control chip; it can realize multiple standard code patterns (nine kinds of CPO-CP8 ) switch, easy to operate and not easy to make mistakes, effectively reducing the operational redundancy of the test link and improving test efficiency.

In addition, the design principle of the present invention is reliable, the structure is simple, and has very wide application prospects.

It can be seen that, compared with the prior art, the present invention has outstanding substantive features and remarkable progress, and the beneficial effects of its implementation are also obvious.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, In other words, other drawings can also be obtained from these drawings on the premise of not paying creative work.

FIG. 1 is a connection block diagram of an FPGA accelerator card high-speed interface SI test control device provided by Embodiment 1 of the present invention.

FIG. 2 is a connection block diagram of an FPGA accelerator card high-speed interface SI test control system provided by Embodiment 2 of the present invention.

detailed description

In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described The embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

Embodiment one

As shown in Figure 1, the embodiment of the present invention provides a kind of FPGA accelerator card high-speed interface SI test control device, the SI test control device of the high-speed interface of the FPGA accelerator card based on SOC device, comprises user interaction interface and high-speed interface controller, so The user interaction interface described above is connected with a pattern switching processing unit through the pattern selection unit; the pattern switching processing unit is connected with a high-speed interface controller; the high-speed interface controller is also connected with a high-speed interface mode configuration unit;

Described user exchange interface is the debugging interface of FPGA accelerator card and starts test, input pre-test pattern by described user exchange interface; It should be noted that, user exchange interface is as the debugging interface of FPGA accelerator card, is usually a serial port, in During the interface SI test, the operator can start the test through this interface, input the pre-test pattern, and also print the log through this interface to understand the status of the test pattern and other information.

The high-speed interface mode configuration unit is used to generate different mode configuration information for sending tests;

The code type selection unit is connected to the user interaction interface and the code type switching processing unit; it is used to identify the type of code type input by the operator through the user interaction interface; it is also used to enter the code type after checking the selected code type. The corresponding code pattern processing link;

The code type switching processing unit is used to generate the configuration information of the corresponding code type according to the judgment of the code type selection unit and output it to the high-speed interface controller;

The high-speed interface controller is used to work in a corresponding mode according to the configuration information from the high-speed interface mode configuration unit and the code switching processing unit to realize the sending and receiving of high-speed interface data.

Embodiment two

The embodiment of the present invention provides a kind of FPGA accelerator card high-speed interface SI test control device, the SI test control device of the high-speed interface of the FPGA accelerator card based on SOC device, including user interaction interface and high-speed interface controller, described user interaction interface through The pattern selection unit is connected with a pattern switching processing unit; the pattern switching processing unit is connected with a high-speed interface controller; the high-speed interface controller is also connected with a high-speed interface mode configuration unit;

Described user exchange interface is the debug interface of FPGA accelerator card, starts test, input pre-test code pattern by described user exchange interface; It should be noted that user exchange interface is as the debug interface of FPGA accelerator card, usually a serial port, During the interface SI test, the operator can start the test and input the pre-test pattern through this interface, and can also print logs through this interface to understand the status of the test pattern and other information.

The high-speed interface mode configuration unit is used to generate different mode configuration information for sending tests;

The code type selection unit is connected to the user interaction interface and the code type switching processing unit; it is used to identify the type of code type input by the operator through the user interaction interface; it is also used to enter the code type after checking the selected code type. The corresponding code pattern processing link;

The code type switching processing unit is used to generate the configuration information of the corresponding code type according to the judgment of the code type selection unit and output it to the high-speed interface controller;

The high-speed interface controller is used to work in a corresponding mode according to the configuration information from the high-speed interface mode configuration unit and the code switching processing unit to realize the sending and receiving of high-speed interface data.

In this embodiment, the high-speed interface is a USB interface, the high-speed interface controller is a USB controller, and the high-speed interface mode configuration unit is a USB mode configuration unit. The device is based on the built-in ARM processor of the SOC device, and realizes the pattern packet output required for the signal integrity test of the USB interface and the configuration of the USB mode.

Preferably, the USB mode configuration unit is configured to generate mode configuration information, and set the USB controller to a host mode with different mode interface rates for sending tests;

The code type selection unit is connected to the user interaction interface and the code type switching processing unit. On the one hand, it recognizes the code type input by the operator through the user interaction interface. According to the corresponding test standard of USB, the code selection unit can provide the selection of nine standard codes; on the other hand, through the judgment and verification of the selected code After that, enter the corresponding code pattern processing link. The code type switching processing unit generates the configuration information of the corresponding code type according to the judgment of the code type selection unit, and outputs it to the USB controller.

The USB controller is used to realize the sending and receiving of USB interface data. According to the configuration information from the USB mode configuration unit and the code switching processing unit, work in the corresponding mode, and output the code corresponding to the configuration information through the sending port, and the USB controller is connected by the USB physical layer transceiver and the USB connector. A USB interface link to be tested is formed. Here, the USB connector may be a USB3.0 connector, so that the sending code pattern test of the USB3.0 interface can be completed through an oscilloscope.

Embodiment Three

As shown in Figure 2, the technical scheme of the present invention provides a kind of FPGA accelerator card high-speed interface SI test system, comprises high-speed interface SI test control device and the interface link to be tested; Described high-speed interface SI test control device and the interface link to be tested Road for communication connection, the interface link to be tested is used to be connected to the oscilloscope; The described high-speed interface SI test control device is the FPGA accelerator card high-speed interface SI test control device described in the first aspect.

Described interface link to be tested comprises USB physical layer transceiver and USB connector, and described USB physical layer transceiver is connected with USB connector; During system testing, USB connector is connected to oscilloscope; Described USB physical layer The transceiver is connected with the USB controller, and is used to realize the interconnection of sending and receiving with the interface link to be tested through the USB controller in the ARM processor built in the SOC device, and complete the sending code pattern test of the USB interface through the oscilloscope. The interface link to be tested includes a first interface link to be tested and a second interface link to be tested; the first interface link to be tested includes a first USB physical layer transceiver and a first USB controller, The first USB physical layer transceiver is connected to the first USB controller; the second interface link to be tested includes a second USB physical layer transceiver and a second USB controller, and the second USB physical layer transceiver is connected to the second USB physical layer transceiver. USB controller connection; both the first USB physical layer transceiver and the second USB physical layer transceiver are connected to the USB controller.

The USB physical layer transceiver and USB3.0 connector constitute the USB interface link to be tested. The connector of this interface is connected to the oscilloscope through the fixture to build a complete signal integrity test environment. The test control system connects two USB physical layer transceivers through the USB controller in the SOC processor to realize the transceiver interconnection with the interface link to be tested, thus forming a complete USB path to ensure the normal transceiver communication of the USB interface. When the SI test is not started, the interface to be tested is a standard USB interface, which can be configured to support USB2.0 or USB3.0, and can be used as a host or a device at the same time; Start the corresponding pattern sending test, and the normal USB mode can be restored after the test is stopped or the power is lost, without affecting the normal use of the USB interface. In addition, the user interaction interface of the test control system adopts the serial port of the SOC system, which is used as a standard debugging port when the test is not started.

The entire workflow of the FPGA accelerator card USB3.0 interface SI test control system:

Start the test through the user interaction interface, enter the test mode, and select the interface link to be tested; the USB mode configuration unit configures the USB controller as USB3. The unit uses corresponding commands to adjust parameters such as driving capability and emphasis; the user interaction interface inputs the code corresponding to the test pattern, and any of the nine standard patterns of CP0-CP8 can be selected according to the actual test requirements; the pattern selection unit is input according to the interactive interface. After the code pattern information is judged and verified, it enters the corresponding code pattern processing link; the code pattern switching processing unit generates the configuration information of the corresponding pattern according to the instruction of the pattern selection unit and the working mechanism of the pattern jump state machine, Output to the USB controller to complete the pattern switching process; the USB controller works in the corresponding mode according to the configuration information from the USB mode configuration unit and the pattern switching processing unit, and outputs the pattern corresponding to the configuration information through the sending port, and outputs to the interface to be tested; the interface to be tested outputs the standard pattern to the oscilloscope, and the eye diagram is tested to complete the USB3.0 TX signal integrity test.

Embodiment Four

The technical scheme of the present invention also provides a kind of FPGA accelerator card high-speed interface SI test method, based on the test method of the FPGA accelerator card high-speed interface SI test system provided by embodiment three, comprising the following steps:

Step 1: Start the test through the user interaction interface, enter the test mode, and select the first interface link to be tested or the second interface link to be tested;

Step 2: The USB mode configuration unit configures the USB controller to be USB3.0, host host mode, so as to carry out the host terminal sending test;

Step 3: Input the code pattern information corresponding to the test pattern through the user interaction interface;

Step 4: The code pattern selection unit outputs instructions to enter the corresponding code pattern processing link after judgment and verification according to the code pattern information input by the user interaction interface;

Step 5: the code type switching processing unit generates the configuration information of the corresponding code type according to the instruction of the code type selection unit according to the working mechanism of the code type jump state machine and outputs it to the USB controller to complete the code type switching process;

Step 6: The USB controller works in the corresponding mode according to the configuration information from the USB mode configuration unit and the code switching processing unit, and outputs the code pattern corresponding to the configuration information through the sending port to the interface chain to be tested selected in step 1 road;

Step 7: The interface link to be tested outputs the standard code pattern to the oscilloscope, and the eye diagram is tested to complete the USB3.0 TX signal integrity test;

Step 8: After the input code pattern test is completed, jump back to step 3 for the next code pattern test.

Notes:

Although the present invention has been described in detail in conjunction with preferred embodiments with reference to the accompanying drawings, the present invention is not limited thereto. Without departing from the spirit and essence of the present invention, those skilled in the art can make various equivalent modifications or replacements to the embodiments of the present invention, and these modifications or replacements should be within the scope of the present invention/any Those skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention, and all should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (6)

1. A kind of FPGA accelerator card high-speed interface SI test control device, it is characterized in that, the SI test control device based on the high-speed interface of the FPGA accelerator card of SOC device, comprises user interaction interface and high-speed interface controller, user interaction interface passes code pattern The selection unit is connected with a pattern switching processing unit; the pattern switching processing unit is connected with a high-speed interface controller; the high-speed interface controller is also connected with a high-speed interface mode configuration unit; Described user interaction interface is the debugging interface of FPGA accelerator card, starts test, input pre-test pattern by described user interaction interface; The high-speed interface mode configuration unit is used to generate different mode configuration information for sending tests; The code pattern selection unit is connected to the user interaction interface and the code pattern switching processing unit; it is used to identify the code pattern type input by the operator through the user interaction interface; it is also used to enter the corresponding The code pattern processing link; The code type switching processing unit is used to generate the configuration information of the corresponding code type according to the judgment of the code type selection unit and output it to the high-speed interface controller; The high-speed interface controller is used to realize the sending and receiving of high-speed interface data in the corresponding mode according to the configuration information derived from the high-speed interface mode configuration unit and the code type switching processing unit; The high-speed interface is a USB interface, the high-speed interface controller is a USB controller, and the high-speed interface mode configuration unit is a USB mode configuration unit; The USB mode configuration unit is used to generate mode configuration information, and the USB controller is set to a host mode with different mode interface rates for sending tests; The user interaction interface is also used to print logs through the interface to understand the packet sending status information of the test pattern; The code type switching processing unit is used to generate configuration information of the corresponding code type according to the judgment of the code type selection unit and output it to the USB controller; The USB controller is used to work in a corresponding mode according to the configuration information from the USB mode configuration unit and the code switching processing unit to realize the sending and receiving of USB interface data. 2. a kind of FPGA accelerator card high-speed interface SI test control device according to claim 1, is characterized in that, this device is based on the built-in ARM processor of SOC device, realizes the required pattern bag output of USB interface signal integrity test And USB mode configuration. 3. a FPGA accelerator card high-speed interface SI test system is characterized in that comprising a high-speed interface SI test control device and an interface link to be tested; the described high-speed interface SI test control device and the interface link to be tested carry out communication connection, to be Test interface link is used to be connected to oscilloscope; Described high-speed interface SI test control device is the FPGA accelerator card high-speed interface SI test control device described in any one of claims 1-2. 4. a kind of FPGA accelerator card high-speed interface SI testing system according to claim 3 is characterized in that described interface link to be tested comprises USB physical layer transceiver and USB connector, and described USB physical layer transceiver Connect with the USB connector; connect the USB connector to the oscilloscope; Described USB physical layer transceiver is connected with USB controller, is used for realizing the interconnection of sending and receiving with the interface link to be tested by the USB controller in the built-in ARM processor of SOC device, completes the transmission pattern of USB interface by oscilloscope test. 5. a kind of FPGA accelerator card high-speed interface SI testing system according to claim 4 is characterized in that described interface link to be tested comprises the first interface link to be tested and the second interface link to be tested; The first interface link to be tested includes a first USB physical layer transceiver and a first USB controller, and the first USB physical layer transceiver is connected to the first USB controller; The second interface link to be tested includes a second USB physical layer transceiver and a second USB controller, and the second USB physical layer transceiver is connected to the second USB controller; Both the first USB physical layer transceiver and the second USB physical layer transceiver are connected to the USB controller. 6. a FPGA accelerator card high-speed interface SI test method is characterized in that comprising the steps: Step 1: Start the test through the user interaction interface, enter the test mode, and select the first interface link to be tested or the second interface link to be tested; Step 2: The USB mode configuration unit configures the USB controller to be USB3.0, host host mode, so as to carry out the host terminal sending test; Step 3: Input the code pattern information corresponding to the test pattern through the user interaction interface; Step 4: The code pattern selection unit outputs instructions to enter the corresponding code pattern processing link after judgment and verification according to the code pattern information input by the user interaction interface; Step 5: the code type switching processing unit generates the configuration information of the corresponding code type according to the instruction of the code type selection unit according to the working mechanism of the code type jump state machine and outputs it to the USB controller to complete the code type switching process; Step 6: The USB controller works in the corresponding mode according to the configuration information from the USB mode configuration unit and the code switching processing unit, and outputs the code pattern corresponding to the configuration information through the sending port to the interface chain to be tested selected in step 1 road; Step 7: The interface link to be tested outputs the standard code pattern to the oscilloscope, and the eye diagram is tested to complete the USB3.0 TX signal integrity test; Step 8: After the input code pattern test is completed, jump back to step 3 for the next code pattern test.

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