CN110995405B - Chaos-based Initial Vector Generation Algorithm and Its IP Core - Google Patents

Abstract

The present invention provides a chaotic initial vector generation algorithm and its IP core. The generation algorithm is based on Logistic chaotic sequence generator inputting a 32-bit initial value x ₀ , and the 128-bit initial key KEY of the ZUC encryption algorithm is divided into 16 a 32-bit key[i]; assign key[0] to 32-bit x ₀ , and calculate x ₁ =4x ₀ (1‑x ₀ ); assign key[i] to key[i‑1], and then x ₁ is assigned to key[15], and the last 128-bit sequence is truncated at 1024-bit intervals for all the x ₁ sequences generated in sequence as an initial vector. An IP core for generating an algorithm includes an initial vector generation module generated by the method, a ZUC encryption algorithm module, a key stream FIFO module, an operation module, a UART communication module and a controller module. The invention utilizes the good randomness of the chaotic pseudo-random sequence and greatly improves the unpredictability of the initial vector.

Description

Chaos-based Initial Vector Generation Algorithm and Its IP Core

Technical field:

The invention relates to the field of data encryption, in particular to a chaos-based initial vector generation algorithm and an IP core thereof.

Background technique:

Zu Chongzhi (ZUC for short) sequence cipher is a synchronous sequence cipher algorithm. The input of the algorithm consists of two parts, namely, the initial key with a bit width of 128 bits (Initial Key, referred to as KEY) and an initial vector with a bit width of 128 bits (Initial Key) Vector, referred to as IV). The ZUC sequence cipher algorithm uses the input 128-bit KEY and 128-bit initial vector to generate a key stream to encrypt digital information.

The ZUC sequence encryption algorithm is the third set of international encryption algorithms recommended by the International Organization for Standardization 3GPP (3rd Generation Partnership Project). According to the ZUC sequence cipher algorithm promulgated by 3GPP, the initial vector is generated in a fixed manner and structure using the relevant control information in the wireless communication process, which is expressed as: let the signal COUNT=COUNT[0]||COUNT[1]| |COUNT[2]||COUNT[3], COUNT represents the frame counter in the communication process, its bit width is 32 bits, and COUNT[i] (0≦i≦3) is an 8-bit long byte, and 128 The initial vector of bit width is expressed as IV=IV[0]||IV[1]||IV[2]||...||IV[15], where IV[i](0≦i≦15) is 8-bit byte, then:

IV[0]=COUNT[0],IV[1]=COUNT[1],

IV[2]=COUNT[2], IV[3]=COUNT[3],

IV[4]=BEARER||DIRECTION||002,

IV[5]=IV[6]=IV[7]=000000002,

IV[8]=IV[0], IV[9]=IV[1],

IV[10]=IV[2], IV[11]=IV[3],

IV[12]=IV[4], IV[13]=IV[5],

IV[14]=IV[6], IV[15]=IV[7].

The symbol "||" is the bit connection symbol, the bit width of the signal BEARER is 5 bits, the function is the bearer layer identification, the bit width of the signal DIRECTION is 1 bit, and the function is the transmission direction identification. Since the initial vector is not confidential in the communication, it can be transmitted in plain text, and the signal COUNT is set to 0 after each KEY update, and changes in an incremental manner, while the signal DIRECTION has only two states of uplink and downlink, then in the whole The signal BEARER with only 5 bits in the initial vector is completely unpredictable. Ideally, the number of bits in the unpredictable part of the IV and the number of bits in the KEY should be the same to improve the resistance to TMDTO (Time-Memory-Data Trade-Off) attacks. This problem has been pointed out in some literature, and it has also been pointed out that shorter unpredictable bits in the initial vector reduce the complexity of alternative types of TMTO attacks, while increasing the number of unpredictable bits in the initial vector is beneficial to improve this question.

Initial vectors play a very important role in synchronous sequence cryptography. In many cases, in the specific encryption process, the KEY cannot be changed frequently. At this time, the use of different initial vectors for updating avoids the situation that the same ciphertext is generated under the same plaintext and the same key, and also avoids the same key stream from being used for multiple times. times are used for encryption. At the same time, in wireless communication, the information in the channel is easy to be lost. When an encrypted communication system can only perform correct decryption when the information is received completely, this system is difficult to apply.

SUMMARY OF THE INVENTION

Based on the above shortcomings, the present invention provides a chaos-based initial vector generation algorithm and its IP core, which greatly improves the unpredictability of the initial vector and improves the ability to deal with TMTO attacks.

The technology adopted in the present invention is as follows: a chaotic initial vector generation algorithm, the initial vector generation method is as follows:

Step 1. First, input a 32-bit initial value x ₀ into the sequence generator based on Logistic chaos, and divide the 128-bit initial key KEY of the ZUC encryption algorithm into 16 32-bit key[i] (0≤i≤ 15), make key[i] (0≤i≤15) as the input of Logistic chaotic iterative map respectively,

Among them, the expression of Logistic chaotic iterative mapping is as follows:

x _n+1 = 4x _n (1-x _n ) (1)

where x ₀ is the initial value, n is the number of iterations, and x _n consists of a 32-bit register;

Step 2, assign key[0] to 32 bits x ₀ , and calculate x ₁ =4x ₀ (1-x ₀ );

Step 3. Assign key[i] to key[i-1], and then assign x ₁ to key[15]. For all x ₁ sequences generated in sequence, truncate the last 128-bit sequence at 1024-bit intervals as an initial vector, and go back to step two.

The present invention also has the following features: an IP core based on a chaotic initial vector generation algorithm, comprising: an initial vector generation module generated by the above method, a ZUC encryption algorithm module, a key stream FIFO module, an operation module, a UART communication module and a controller module,

The described initial vector generation module is responsible for generating the initial vector required for the work of the ZUC encryption algorithm module;

Described ZUC encryption algorithm module is responsible for generating the key sequence for encryption and decryption according to key KEY and initial vector;

Described key stream FIFO module is used for buffering the key stream output by ZUC encryption algorithm module;

The UART communication module realizes the modulation and demodulation of the communication process between the IP core and the host computer;

The operation module performs XOR operation on the data taken out from the receiver FIFO unit of the UART communication module and the key stream FIFO module, completes the encryption and decryption of the data, and delivers the processed data to the transmitter of the UART communication module. FIFO unit;

The controller module is the main control unit of the entire IP core, all modules work under its scheduling, and it controls the flow of data and the operations accepted by the data.

The advantages and beneficial effects of the present invention are as follows: the present invention utilizes the good randomness of the chaotic pseudo-random sequence, greatly improves the unpredictability of the initial vector, improves the ability to deal with TMTO attacks, and combines it with the ZUC sequence cryptographic algorithm, It forms an important part of the IP core of the ZUC encryption algorithm. In addition, the sequence cipher algorithm adds the initial vector and designs the frame structure for data communication, so that even if some data is damaged or missing, the system can still continue to complete the decryption of those correctly received data frames. In the case where the transmitted information is sequential, the initial vector can also be used as the number of the information frame.

Description of drawings

Figure 1 is a schematic diagram of the FPGA-based ZUC encryption algorithm IP core;

Fig. 2 is the top-level design diagram of hardware implementation of initial vector generation algorithm module based on Logistic chaos;

Fig. 3 is the flow chart of initial vector generation module;

Figure 4 shows the top-level architecture diagram of the FPGA.

Detailed ways

The present invention will be further described below according to the accompanying drawings of the description:

Example 1

A chaos-based initial vector generation algorithm, the initial vector generation method is as follows:

Step 1. First, input a 32-bit initial value x ₀ into the sequence generator based on Logistic chaos, and divide the 128-bit initial key KEY of the ZUC encryption algorithm into 16 32-bit key[i] (0≤i≤ 15), make key[i] (0≤i≤15) as the input of Logistic chaotic iterative map respectively,

Among them, the expression of Logistic chaotic iterative mapping is as follows:

x _n+1 = 4x _n (1-x _n ) (1)

where x ₀ is the initial value, n is the number of iterations, and x _n consists of a 32-bit register;

Step 2, assign key[0] to 32 bits x ₀ , and calculate x ₁ =4x ₀ (1-x ₀ );

Step 3. Assign key[i] to key[i-1], and then assign x ₁ to key[15]. For all x ₁ sequences generated in sequence, truncate the last 128-bit sequence at 1024-bit intervals as an initial vector, and go back to step two.

Among them, the IP core based on the chaotic initial vector generation algorithm includes: an initial vector generation module, a ZUC encryption algorithm module, a key stream FIFO module, an operation module, a UART communication module and a controller module, and the initial vector generation module is responsible for generating The initial vector required for the work of the ZUC encryption algorithm module;

Described ZUC encryption algorithm module is responsible for generating the key sequence for encryption and decryption according to key KEY and initial vector;

Described key stream FIFO module is used for buffering the key stream output by ZUC encryption algorithm module;

The UART communication module realizes the modulation and demodulation of the communication process between the IP core and the host computer;

The operation module performs XOR operation on the data taken out from the receiver FIFO unit of the UART communication module and the key stream FIFO module, completes the encryption and decryption of the data, and delivers the processed data to the transmitter of the UART communication module. FIFO unit;

The controller module is the main control unit of the entire IP core, all modules work under its scheduling, and it controls the flow of data and the operations accepted by the data.

Example 2

FPGA of IP Core Based on Chaos Initial Vector Generation Algorithm

As shown in Figure 2, the initial vector generation module has 6 input and output signals, whose signal definitions are listed in Table 1.

Table 1 Top-level module signal list

In addition to the clock signal and the reset signal, the initial vector generation module also has a control signal "start". The main workflow of the initial vector generation module is described here: when the initial vector generation module is powered on, it first performs a reset operation, and then The initial vector generation module enters the standby state. When the start signal is valid for the first time, the initial vector generation module will download the key and run for 1024 clock cycles, and then output an initial vector. At the same time, the initial vector valid flag signal "IV output valid" is pulled. A high beat indicates that the signal on the output signal "Output IV" is valid at this time, and then the module enters the standby state. If the signal "Start" is valid again, the module will run again for 1024 clock cycles from the previous state and generate a new initial vector. By analogy, the algorithm flow chart is used here to describe the main workflow, as shown in Figure 3.

Figure 4 shows the top-level architecture design, in which the latency of the module with multi-shot latency has been marked in the figure. The global calculation accuracy of the initial vector generation module is 32 bits, and the system variable x _n ∈(0,1) can be known from equation (1), then all operations of IVMKAKER are 32-bit unsigned pure decimals, such as a 32-bit in the system The binary number is represented as M _b = m ₃₁ m ₃₀ m ₂₉ . . . m ₁ m ₀ , where m _i ∈ {0,1} and i=0,1,2,...,31, then the decimal number represented by it can be expressed by the formula (2) means:

The control module is a control unit, which completes the function of generating the initial value in the formula (1), and controls the enabling of each sub-module and the selection signal of the selector module at the same time. The delay module delays the input by two clock cycles and outputs the output; the functional expression of the bit inversion module is as follows:

bn[31:0]=～sel[31:0] (3)

The adder module completes the calculation of adding 1 to the input value, and its expression is as follows:

add[31:0]=bn[31:0]+1 (4)

The bitwise negation module and the adder module are cascaded together to complete the calculation of the (1-x _n ) part of formula (1). =1010, obviously, to get the value of AB, you can get it by ~B+1. This is because in this design, all numbers in the system are 32-bit unsigned decimals. To represent decimal 1, a 33-bit width is required, and the method in this design avoids the need to represent decimal 1. The single-bit width is increased, and the use of subtraction in digital circuits is avoided. In addition, the inversion operation is very simple to implement for digital circuits; the multiplier module completes the calculation of x _n (1-x _n ) Work, when two data with a bit width of 32 bits are multiplied, a 64-bit bit wide product will be generated inside the multiplier.

We made statistics on the resources and speed occupied by the implemented initial vector generation module, and compared it with the circuit that uses the conventional Logistic chaotic sequence generation algorithm to achieve the same function. The results are shown in Table 2. It can be seen that our implementation The initial vector generation module increases the maximum operating frequency of the circuit by 2.4 times when the logic resource slice consumption on the FPGA chip increases by 16.3%. On the basis of better unpredictability of the generated initial vector, at the same time Got a decent level of resource consumption and speed.

Table 2 Comparison of resources and speed

Claims (1)

1. An IP core based on a chaos initial vector generation algorithm comprises the following steps: an initial vector generation module, a ZUC encryption algorithm module, a key stream FIFO module, an operation module, a UART communication module and a controller module,

the initial vector generation module is responsible for generating an initial vector required by the ZUC encryption algorithm module;

the ZUC encryption algorithm module is responsible for generating a KEY sequence for encryption and decryption according to a KEY KEY and an initial vector;

the key stream FIFO module is used for caching the key stream output by the ZUC encryption algorithm module;

the UART communication module realizes the modulation and demodulation work of the communication process of the IP core and the upper computer;

the arithmetic module carries out XOR operation on the data taken out from the receiver FIFO unit and the key stream FIFO module of the UART communication module to finish the encryption and decryption of the data, and the processed data is delivered to the transmitter FIFO unit of the UART communication module;

the controller module is a main control unit of the whole IP core, all modules work under the scheduling of the controller module, and the controller module controls the flow direction of data and the operation received by the data;

the method for generating the initial vector module comprises the following steps:

firstly, inputting an initial value x of 32 bits into a sequence generator based on Logistic chaos₀Dividing 128-bit initial KEY KEY of ZUC encryption algorithm into 16 32-bit KEYs [ i]I is not less than 0 and not more than 15, so that key [ i ≦]Respectively as the input of Logistic chaotic iterative mapping,

the Logistic chaotic iterative mapping expression is as follows:

x_n+1＝4x_n(1-x_n) (1)

wherein x₀Is an initial value, n is the number of iterations, and x_nThe device is composed of a 32-bit register;

step two, key [0]]Assigned to 32 bits x₀And calculate x₁＝4x₀(1-x₀)；

Step three, key [ i ]]Assign a key [ i-1 ]]Then x is added₁Assign value to key [15]For all x generated in sequence₁The sequence intercepts the last 128-bit sequence as an initial vector at 1024-bit intervals, and returns to step two.

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