CN110888519B

CN110888519B - A memory programming method and system

Info

Publication number: CN110888519B
Application number: CN201810941467.4A
Authority: CN
Inventors: 贺元魁; 潘荣华
Original assignee: Zhaoyi Innovation Technology Group Co ltd
Current assignee: Zhaoyi Innovation Technology Group Co ltd
Priority date: 2018-08-17
Filing date: 2018-08-17
Publication date: 2024-02-20
Anticipated expiration: 2038-08-17
Also published as: CN110888519A

Abstract

The invention discloses a memory programming method and system. The method includes the following steps: during the programming sequence B11, apply a programming voltage to the storage cells of the memory. There are r storage cells, and r is a positive integer; during the verification sequence Y11, apply a verification voltage to r storage cells. When there are u When the memory cell verification fails, then in the programming sequence B1u, an increased programming voltage is applied to the u memory cells that have failed verification to rewrite data, 0<u≤r, u is a positive integer; verification At the time sequence Y1u, the verification voltage is applied to u memory cells that have rewritten data. If all verifications are successful, it ends. If v memory cells fail verification, 0≤v≤u, then v memory cells that have failed verification will be applied. Data is rewritten into the storage module.

Description

Method and system for programming memory

Technical Field

The embodiment of the invention relates to the technical field of memories, in particular to a programming method and system of a memory.

Background

The memory is a nonvolatile memory, and has the advantages of high writing speed, large storage capacity and the like. In Nand flash memory, especially TLC memory, the memory cells have more states, and when programming verification is performed, more electric energy is required, and power consumption is high.

Therefore, how to reduce the power consumption of the storage is a need in the memory technology field.

Disclosure of Invention

The invention provides a programming method and a programming system of a memory, which aim to solve the technical problem of high power consumption of the memory during programming.

In a first aspect, an embodiment of the present invention provides a method for programming a memory, including the steps of: in the programming time sequence B11, programming voltages are applied to storage units of the memory, wherein r storage units are provided, and r is a positive integer; when the verification time sequence Y11 is verified, verifying voltage is applied to r storage units, when the verification of u storage units fails, and when the programming time sequence B1u is verified, the amplified programming voltage is applied to the storage units with the failed verification of u to rewrite data, wherein u is more than 0 and less than or equal to r, and u is a positive integer; when the verification time sequence Y1u is verified, verification voltage is applied to the u memory cells for rewriting data, if all verification is successful, and if v memory cells fail to verify, v is more than or equal to 0 and less than or equal to u, the data is rewritten in v memory modules which fail to verify.

Preferably, r memory cells are sequentially arranged from the 1 st state memory cell to the t state memory cell after the programming voltage is applied, t is less than or equal to r, and t is a positive integer; when the verification time sequence Y1 verifies the memory cell in the 1 st state, only the bit line of the memory cell in the 1 st state to be verified is charged, and the verification time sequence Y1 comprises a verification time sequence Y11 to a verification time sequence Y1w; when the checking time sequence Ys checks the storage unit in the S state, only the bit line of the storage unit in the checked S state is charged, S is more than or equal to 1 and less than or equal to t, and S is a positive integer.

Preferably, in the verification timing Y1, a verification voltage is applied to the word line connected to the memory cell in the 1 st state, the bit line where the memory cell in the 1 st state is located is precharged to a precharge voltage, and a pass voltage is applied to the other word lines; and then discharging the charged bit line for a first time, comparing the voltage of the bit line after discharging with a first judging voltage, if the voltage of the bit line after discharging is higher than the first judging voltage, indicating that the verification is successful, otherwise, indicating that the verification is failed, storing data into the memory again, and verifying the memory cell in the 1 st state again.

Preferably, after the verification timing Y1 fails to verify, the amplified program voltage is applied to the word line to which the memory cells of the 1 st to t-th states are connected; after the verification timing Ys fails to verify, the amplified program voltage is applied to the word lines to which the memory cells of the s-th state to the t-th state are connected.

Preferably, in the verification timing Y1, the 1 st memory cell exists on p bit lines, after the verification of the q memory cells on the bit lines fails, the amplified programming voltage is applied to the word line connected to the 1 st memory cell and the 2 nd to t memory cells on the q bit lines failing to verify, and the 1 st memory cell on the q bit lines failing to verify is verified again, where q is less than or equal to p, and p and q are all positive integers.

Preferably, in verifying the timing Ys, a verification voltage is applied to the word line to which the memory cell in the s-th state is connected, the bit line in which the memory cell in the s-th state is located is precharged to a precharge voltage, and a pass voltage is applied to the other word lines; and then discharging the charged bit line for a first time, comparing the voltage of the bit line after discharging with a first judging voltage, if the voltage of the bit line after discharging is higher than the first judging voltage, indicating that the verification is successful, otherwise, indicating that the verification is failed, storing data into a memory again, and verifying the memory cell in the s state again.

Preferably, the states of the memory cells are a state, B state, C state, D state, E state, F state and G state in order, respectively, and the programming voltages required for the memory cells of the a state to the G state are sequentially increased.

Preferably, the memory is a TLC type memory.

Preferably, the program voltage ranges from 12V to 22V, the verify voltage ranges from 0V to 1V, and the precharge voltage ranges from 1V to 1.2V.

In a second aspect, the present invention also provides a programming system of a memory, the programming system of the memory comprising: the programming module is used for applying programming voltages to storage units of the memory when programming the time sequence B11, wherein r storage units are provided, and r is a positive integer; the verification module is used for applying verification voltage to r storage units when the verification time sequence Y11 is used for verifying, and when u storage units fail in verification, the programming module is also used for applying amplified programming voltage to the storage units fail in verification in the programming time sequence B1u so as to rewrite data, wherein u is more than 0 and less than or equal to r, and u is a positive integer; and the verification module is also used for applying verification voltage to the storage units of the u rewritten data when the verification module is used for verifying the time sequence Y1u, and ending if all verification is successful, and rewriting the data into the v storage modules which are failed in verification if v storage units are failed in verification, wherein v is greater than or equal to 0 and less than or equal to u.

Compared with the prior art, the programming method and the programming system of the memory have the advantages that when programming verification is carried out, the charging voltage is only provided for the bit line of the memory unit which is failed to verify, normal operation of the memory is not hindered, the electric energy consumption of the memory during programming verification is reduced, the power consumption of the memory during use is reduced, and the requirement of energy conservation is met.

Drawings

Fig. 1 is a flowchart illustrating a method for programming a memory according to an embodiment of the invention.

Fig. 2 is a schematic diagram of a chip structure of a memory cell according to an embodiment of the invention.

Fig. 3 is a schematic circuit diagram of a memory array according to an embodiment a of the invention.

Fig. 4 is a schematic waveform diagram of voltages at different moments in time of a method for programming a memory according to embodiment a of the present invention.

FIG. 5 is a graph showing the amplitude variation of the program voltage according to the increase of the verification failure times in embodiment A.

Fig. 6 is a schematic block diagram of a programming system of a memory according to an embodiment B of the invention.

Detailed Description

The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.

Before discussing exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart depicts steps as a sequential process, many of the steps may be implemented in parallel, concurrently, or with other steps. Furthermore, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.

Example A

Referring to fig. 1, fig. 1 is a flow chart of a method for programming a memory according to an embodiment of the invention, wherein the method for programming a memory is used for improving durability and usability of read data of the memory so as to improve life of the memory, and the method for programming the memory comprises the following steps:

step S1: in the programming time sequence B11, programming voltages are applied to storage units of the memory, wherein r storage units are provided, and r is a positive integer;

step S2: when the verification time sequence Y11 is verified, verifying voltage is applied to r storage units, when the verification of u storage units fails, and when the programming time sequence B1u is verified, the amplified programming voltage is applied to the storage units with the failed verification of u to rewrite data, wherein u is more than 0 and less than or equal to r, and u is a positive integer;

s3, a step of S3; when the verification time sequence Y1u is verified, verification voltage is applied to the u memory cells for rewriting data, if all verification is successful, and if v memory cells fail to verify, v is more than or equal to 0 and less than or equal to u, the data is rewritten in v memory modules which fail to verify.

Referring to fig. 2, fig. 2 is a schematic diagram of a chip structure of the memory unit 111. The memory cell 111 includes a substrate 1111, a source 1112, a drain 1113, a tunnel oxide film 1114, a floating gate 1115, and a control gate 1116, wherein the substrate 1111 includes a P-well region, the source 1112 and the drain 1113 are disposed in the P-well region, a channel is formed between the source 1112 and the drain 1113, the tunnel oxide film 1114 is formed in the channel between the source 1112 and the drain 1113, the floating gate 1115 is disposed on the tunnel oxide film 1114, and the control gate 1116 is disposed on the floating gate 1115. It is understood that a dielectric film 1117 is disposed between the control gate 1116 and the floating gate 1115. When no charge is stored in the floating gate 1115, that is, when data "1" is written, the threshold is in a negative state, and the memory cell 111 is turned on by the control gate 1116 being set to 0V. When electrons are stored in the floating gate 1115, that is, when data "0" is written, the threshold shift is positive, and the memory cell is turned off by the control gate 1116 being set to 0V. However, the memory cell is not limited to storing a single bit, and may store a plurality of bits.

In step S1, step S1 is a programming step, and data is written into the memory. The memory is preferably a NAND type memory. Referring to fig. 3, fig. 3 is a schematic circuit diagram of a memory array. The memory includes n word lines (WL 1, WL2, …, WLn), m bit lines (BL 1, BL2, …, BLm), one select gate line SGS, one select gate line SGD, and one common source line SL, and the portion of the memory cell identified by the dashed box 11 is referred to as a memory cell string. Each memory cell string includes a plurality of the above-described memory cells 111 (i.e., MC1 to MCn); a bit line side selection transistor TD connected to the memory cell MCn as one end; and a source line side selection transistor TS connected to the memory cell MC1 as the other end portion, wherein the drain of the bit line side selection transistor TD is connected to the corresponding 1 bit line BL, and the source of the source line side selection transistor TS is connected to the common source line SL. The control gate of the memory cell 111 is connected to a word line WLi (i=0 to n), the gate of the bit line side select transistor TD is connected to a select gate line SGD, and the gate of the source line side select transistor TS is connected to a select gate line SGS.

Referring to fig. 4 and 5 together, fig. 4 is a schematic waveform diagram of the memory programming method according to the present invention at different time, fig. 5 is a schematic variation diagram of the amplitude of the programming voltage with the increase of the verification failure time in embodiment a. This embodiment provides a specific programming step, in this embodiment, data is written into the memory cell MC1, and the programming voltage V is applied to the selected word line WL1 at the time of programming the timing B1 _pgm A pass voltage is applied to unselected word lines WL 2-WLn, 0V is applied to selected bit line BLm, and a positive voltage is applied to unselected bit lines BL 1-BLm-1. The program voltage Vpgm ranges from 10 to 18V, preferably from 12V to 16V. In a certain programming time, the memory cell with a lower initial threshold voltage is programmed with a larger increment of threshold voltage, and conversely, the memory cell with a lower initial threshold voltage is programmed with a smaller increment of threshold voltage. It will be appreciated by those skilled in the art that in performing a programming operation, it is also generally necessary to apply a voltage of 0V to the select gate line SGS and to apply a voltage of about 4V to the select gate line SGD to turn on the connected MOS transistors.

When programming a plurality of memory cells, a program voltage is applied to a selected word line of the programmed memory cell, a pass voltage is applied to an unselected word line, 0V is applied to a selected bit line, and a positive voltage is applied to an unselected bit line. In this embodiment, the memory type is a TLC (three byte) type memory. The memory includes r memory cells 111, and the specific number of memory cells 111 is not limited.

In this embodiment, t= 7,r memory cells 111 include at least the 1 st to 7 th memory cells arranged in order after the program voltage is applied, the states of the memory cells are a, B, C, D, E, F and G states in order, and the program voltages required for the memory cells of the a to G states are sequentially increased. It will be appreciated that the programming voltages applied to memory cells of different states are different. All memory cells in the a to G states are charged at the same time when programming write data. It will be appreciated that the states of the memory cells on the same bit line are consistent, if one memory cell is in the B state on the same bit line, the other memory cells on the same bit line are in the B state. It will be appreciated that the programming method of the memory of the present invention is also applicable to programming of memories in general.

In step S2, in the verification timing Y11, a verification voltage is applied to a selected word line of a memory cell in a first state among r memory cells in the memory, a selected bit line is precharged to a precharge voltage, and a pass voltage is applied to an unselected word line; then discharging the selected bit line for a first time, comparing the voltage of the bit line after discharging with a first judging voltage, if the voltage of the selected bit line is higher than the first judging voltage, indicating that the programming verification operation is successful, and if the programming verification operation is finished, otherwise, the verification fails, and the data needs to be stored in the memory again. After verification, if the voltage of the bit lines where the u memory cells are positioned after discharging is lower than the first judging voltage, judging that the verification of the u memory cells fails. Preferably, the range of the verification voltage is 0V to 1V. The precharge voltage ranges from 1v to 1.2v.

When the states of the memory cells are t types, the check time sequences Y11 to Y1W only check the memory cells in the 1 st state until all the memory cells in the 1 st state are successfully checked, and the memory cells in the next state are checked.

In the programming timing B1u, a program voltage is applied to the selected word line of the u memory cells in the first state and the selected word lines of the memory cells in the 2 nd to t-th states to write data, a pass voltage is applied to the unselected word lines, 0V is applied to the selected bit lines, and a positive voltage is applied to the unselected bit lines.

In step S3, a verify voltage is applied to a selected word line of u memory cells in which data is rewritten, a selected bit line is precharged to a precharge voltage, and a pass voltage is applied to unselected word lines; then discharging the selected bit line for a first time, comparing the voltage of the bit line after discharging with a first judging voltage, if the voltage of the selected bit line is higher than the first judging voltage, indicating that the programming verification operation is successful, and if the programming verification operation is finished, otherwise, the verification fails, and the data needs to be stored in the memory again. And all the memory cells up to the 1 st state are verified successfully.

For example, the 1 st state memory cell exists on p bit lines, after the verification of the u th memory cells on q bit lines fails, the amplified programming voltage is applied to the word line connected to the 1 st state memory cell and the 2 nd to t state memory cells on the q bit lines failing to verify, the pass voltage is applied to the unselected word lines, 0V is applied to the selected bit line, the positive voltage is applied to the unselected bit line to write data, and then the 1 st state memory cell on the q bit lines failing to verify is again verified, wherein q is equal to or less than p, and p and q are positive integers.

It is understood that the verification timings Y11 to Y1w are verification of the 1 st state memory cell. That is, the verification timing Y1 includes verification timing Y11 to verification timing Y1w. When the verification timing Y1 verifies the 1 st-state memory cell, only the bit line of the verified 1 st-state memory cell is charged. Applying a verification voltage to a word line connected with a memory cell with failed 1 state verification, precharging a bit line where the memory cell with failed 1 state verification is positioned to a precharge voltage, and applying a pass voltage to other word lines; and then discharging the charged bit line for a first time, comparing the voltage of the bit line after discharging with a first judging voltage, if the voltage of the bit line after discharging is higher than the first judging voltage, indicating that the verification is successful, otherwise, indicating that the verification is failed, storing data into the memory again, and verifying the memory cell in the 1 st state again.

Because the memory cell successfully verified in the 1 st state is not written with data and re-verified, the electric energy is saved, the power consumption of the memory is reduced, and the social development requirement is met. And when the memory cell in the 1 st state is verified, only the bit line of the verified memory cell in the 1 st state is charged, so that the power consumption of the memory is further reduced, and the power consumption of the memory is reduced.

When the checking time sequence Ys checks the storage unit in the S state, only the bit line of the storage unit in the checked S state is charged, S is more than or equal to 1 and less than or equal to t, and S is a positive integer.

When verifying the time sequence Ys, applying a verification voltage to the word line connected with the memory cell in the s state, precharging the bit line where the memory cell in the s state is positioned to a precharge voltage, and applying a passing voltage to other word lines; and then discharging the charged bit line for a first time, comparing the voltage of the bit line after discharging with a first judging voltage, if the voltage of the bit line after discharging is higher than the first judging voltage, indicating that the verification is successful, otherwise, indicating that the verification is failed, storing data into a memory again, and verifying the memory cell in the s state again. If some of the memory cells in the s state are successfully verified, and another part of the memory cells in the s state are failed to be verified, the data can be selected to be re-input and re-verified for all the memory cells in the s state, or the data can be selected to be re-input and re-verified for only the memory cells in the s state which are failed to be verified. Preferably, data is re-entered and re-verified only for memory cells that failed verification in the s-th state.

After the verification timing Ys fails to verify, the amplified program voltage is applied to the word lines connected to the memory cells of the s-th state to the t-th state to write data. It will be appreciated that the method of writing data may refer to the method of writing data described above, or a method of writing data in the prior art may be used.

Example B

Referring to fig. 6, fig. 6 is a schematic block diagram of a programming system 12 of the memory according to the present invention. The memory programming system 12 is capable of performing the memory programming method provided by any of the embodiments of the present invention. The programming system 12 of the memory includes:

a programming module 121, configured to apply a programming voltage to r memory cells of the memory when programming the timing B11, where r is a positive integer;

the verification module 122 is configured to apply a verification voltage to r memory cells when the verification sequence Y11 is verified, and when u memory cells fail to verify, the programming module 121 is further configured to apply an amplified programming voltage to the memory cells that fail to verify to rewrite data when the programming sequence B1u is programmed, where u is greater than 0 and less than or equal to r, and u is a positive integer;

the verification module 122 is further configured to apply a verification voltage to the u memory cells for rewriting data when the verification sequence Y1u is verified, and finish all verification if v memory cells fail to verify, and rewrite data to v memory modules that fail to verify if v memory cells fail to verify.

Through the programming system 12 of the memory, after the verification of part of the memory units fails, only the memory units which fail to be verified are re-verified, and the memory units which fail to be verified are not verified any more, so that unnecessary electric energy consumption is saved, and the power consumption of the memory units is reduced.

It will be appreciated that the teachings of embodiments A and B of the present invention are complementary and illustrative.

It should be noted that, in all the above embodiments, each unit and module included are only divided according to the functional logic, but not limited to the above division, so long as the corresponding functions can be implemented; in addition, the specific names of the functional units are also only for distinguishing from each other, and are not used to limit the protection scope of the present invention.

Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims

1. A memory programming method, characterized in that it includes the following steps:

During programming sequence B11, the programming voltage is applied to the storage cells of the memory. There are r storage cells, and r is a positive integer;

In the verification sequence Y11, the verification voltage is applied to r memory cells. When u memory cells fail to verify, then in the programming sequence B1u, amplified programming is applied to the u memory cells that failed to verify. The voltage is used to rewrite data, 0<u≤r, u is a positive integer; among them, during the programming sequence B1u, the selected word lines of u memory cells in the first state and the memory cells in the second to t states Apply a programming voltage to the selected word line to write data, apply a pass voltage to the unselected word line, apply 0V to the selected bit line, and apply a positive voltage to the unselected bit line;

At the verification timing Y1u, the verification voltage is applied to u memory cells that have rewritten data. If all verifications are successful, it ends. If v memory cells fail verification, 0 ≤ v ≤ u, the verification voltage is applied to the memory cells that have failed verification. Rewrite data in v storage modules;

Wherein, r memory cells are arranged in sequence from the memory cells in the first state to the memory cells in the t state after applying the programming voltage, t is less than or equal to r, and t is a positive integer;

When the verification timing Y1 verifies the memory cell in the first state, only the bit line of the verified first state memory cell is charged. The verification timing Y1 includes the verification timing Y11 to the verification timing Y1w;

When the verification timing Ys verifies the storage unit in the S-th state, only the bit line of the verified S-th state storage unit is charged, 1≤s≤t, s is a positive integer; among them, when the S-th state When a part of the storage units fails the verification, only the storage units that failed the verification in the s-th state are re-entered with data and re-verified;

Among them, during the verification sequence Y1, a verification voltage is applied to the word line connected to the memory cell in the first state, the bit line where the memory cell in the first state is located is precharged to the precharge voltage, and the pass voltage is applied to other word lines; Then, the charged bit line is discharged for a first time, and then the voltage of the bit line after discharge is compared with the first determination voltage. If the voltage of the bit line after discharge is higher than the first determination voltage, it indicates verification. Success, otherwise, it means that the verification fails and the data needs to be stored in the memory again, and the storage unit in the first state is verified again;

Among them, after the verification of the verification timing Y1 fails, an amplified programming voltage is applied to the word line connected to the memory cells in the first to t-th states; after the verification of the verification timing Ys fails, the word lines connected to the memory cells in the s-th to t-th states are The amplified programming voltage is applied to the word line connected to the memory cell of the state;

Among them, during the verification timing Y1, the memory cells in the first state exist on p bit lines. After the memory cells on q bit lines fail to verify, the first state of the memory cells on the q bit lines that failed to verify will be The increased programming voltage is applied to the word lines connected to the memory cells in the 2nd to tth states and the memory cells in the 2nd to tth states, and the 1st state memory cells on the q bit lines that failed to verify are verified again, q ≤p, p and q are both positive integers.

2. The memory programming method according to claim 1, characterized in that: when verifying the timing Ys, a verification voltage is applied to the word line connected to the memory cell in the s-th state, and the bit where the memory cell in the s-th state is located is The line is precharged to the precharge voltage, and a pass voltage is applied to other word lines; then the charged bit line is discharged for the first time, and then the discharged bit line voltage is compared with the first determination voltage. If the bit line after discharge If the voltage of the line is higher than the first determination voltage, it means that the verification is successful. On the contrary, it means that the verification fails and the data needs to be stored in the memory again and the storage unit in the s-th state is verified again.

3. The memory programming method according to claim 1, characterized in that: the t=7, and the states of the memory cells are A state, B state, C state, D state, E state, and F state in order. state and G state, the programming voltage required for the memory cells from the A state to the G state increases in sequence.

4. The memory programming method according to any one of claims 1 to 3, characterized in that: the memory is a TLC type memory.

5. The memory programming method according to claim 1, characterized in that: the programming voltage ranges from 12V to 22V, the verification voltage ranges from 0V to 1V, and the precharge voltage ranges from 1v ~1.2v.

6. A memory programming system, characterized in that the memory programming system includes:

The programming module is used to apply programming voltage to the storage cells of the memory during programming sequence B11. There are r storage cells, and r is a positive integer;

The verification module is used to apply verification voltages to r memory cells during verification timing Y11. When u memory cells fail to verify, the programming module is also used to verify u memory cells during programming timing B1u. The failed memory cell applies an increased programming voltage to rewrite data, 0<u≤r, u is a positive integer;

The verification module is also used to verify the timing Y1u, applying verification voltage to u memory cells that rewrite data. If all verifications are successful, the verification will end. If v memory cells fail to verify, 0≤v≤u, Then rewrite data into the v memory modules that failed the verification; among them, during the programming sequence B1u, the selection word lines of the u memory cells in the first state and the selection of the memory cells in the second to t states are A programming voltage is applied to the word line to write data, a pass voltage is applied to the unselected word line, 0V is applied to the selected bit line, and a positive voltage is applied to the unselected bit line;

Among them, after the verification of the verification timing Y1 fails, an amplified programming voltage is applied to the word line connected to the memory cell from the first state to the t-th state; after the verification of the verification timing Ys fails, the s-th state to the t-th state are applied The amplified programming voltage is applied to the word line connected to the memory cell of the state;