CN110808804A - Structure and method for realizing receiving synchronization of multipath RapidIO test board cards and test equipment - Google Patents
Structure and method for realizing receiving synchronization of multipath RapidIO test board cards and test equipment Download PDFInfo
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- CN110808804A CN110808804A CN201911045730.2A CN201911045730A CN110808804A CN 110808804 A CN110808804 A CN 110808804A CN 201911045730 A CN201911045730 A CN 201911045730A CN 110808804 A CN110808804 A CN 110808804A
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04J3/0635—Clock or time synchronisation in a network
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Abstract
The utility model provides a structure, a method and a test device for realizing the receiving synchronization of a plurality of RapidIO test board cards, which comprises a back plate and a plurality of cascaded RapidIO test board cards, wherein each RapidIO test board card is provided with a synchronous clock output interface, a synchronous clock input interface, a synchronous clock generating device and a clock selector, and the synchronous clock input interface of each RapidIO test board card is connected with the synchronous clock output interface of a first-level RapidIO test board card; the input end of each RapidIO test board card clock selector is respectively connected with a synchronous clock generating device and a synchronous clock input interface of the RapidIO test board card; the clock selector is used for selecting a clock signal of the RapidIO test board card and transmitting the clock signal to the next RapidIO test board card. The GPS time system module is not needed, the hardware circuit composition of the multi-path RapidIO test board cards is the same, the master-slave mode is switched through the dial switch, the signal synchronization of the multi-path board cards can be realized from the aspect of hardware operation, the multiplexing and the cascading of the multi-path board cards are realized, the use is simple and convenient, and the implementation is easy.
Description
Technical Field
The disclosure relates to the technical field related to testing technology, in particular to a method for realizing receiving synchronization of a plurality of RapidIO test board cards and automatic test equipment.
Background
The statements in this section merely provide background information related to the present disclosure and may not necessarily constitute prior art.
With the development of a RapidIO bus, the transmission rate is continuously improved, the highest test rate of a single channel reaches 6.25Gb/s, and the highest test rate can support a 4x mode. However, in the actual test process, the situation that the test bandwidth of a single test board card is not enough still exists, and a plurality of RapidIO test board cards are required to be tested in parallel, so that the problem of time synchronization when a plurality of RapidIO test board cards receive data is involved.
In the prior art, a mode of adding a GPS time system module can be adopted, and the GPS time system module is adopted to provide a uniform synchronous clock signal to perform time synchronization on a plurality of RapidIO test board cards. The inventor finds that the prior art adopts a mode of a GPS time system module, on one hand, the structure of the GPS time system module is in a board card mode, and needs to occupy one card slot independently, thereby occupying space and increasing weight; on the other hand, the GPS time system module is only used for providing synchronous clock signals, and the cost performance is low.
Disclosure of Invention
The present disclosure provides a structure, a method, and a test device for realizing synchronization of reception of multiple RapidIO test boards, where the multiple RapidIO test boards have the same hardware circuit composition, and only need to switch master-slave modes through a dial switch, signal synchronization of the multiple boards can be realized, synchronization can be realized, multiplexing and cascading of the multiple boards can be realized, and the structure, the method, and the test device are simple and easy to use and implement.
In order to achieve the purpose, the following technical scheme is adopted in the disclosure:
one or more embodiments provide a structure for realizing the receiving synchronization of a plurality of RapidIO test board cards, which comprises a backboard and a plurality of cascaded RapidIO test board cards, wherein each RapidIO test board card is provided with a synchronous clock output interface, a synchronous clock input interface, a synchronous clock generation device and a clock selector, and the synchronous clock input interface of each RapidIO test board card is connected with the synchronous clock output interface of the first-level RapidIO test board card; the input end of each RapidIO test board card clock selector is respectively connected with a synchronous clock generating device and a synchronous clock input interface of the RapidIO test board card; the clock selector is used for selecting a clock signal of the RapidIO test board card and transmitting the clock signal to the next RapidIO test board card.
Based on the synchronization method of the structure for realizing the receiving synchronization of the multipath RapidIO test board cards, the method comprises the following steps:
setting one RapidIO test board card of the plurality of RapidIO test board cards as a master mode board card, and setting the other RapidIO test board cards as slave mode board cards;
the master mode board card adopts a clock signal generated by a crystal oscillator on the board card as a synchronous clock of the board card, and simultaneously transmits the clock signal to the slave mode board card step by step;
the slave mode board card adopts a clock signal transmitted by the master mode board card as a synchronous clock;
the master mode board card generates a synchronization start signal and starts to receive data, and transmits the synchronization start signal to the slave mode board card;
and the slave mode board card receives a synchronization starting signal of the master mode board card and starts to receive data.
A test device comprises a backboard and a plurality of cascaded RapidIO test board cards, wherein the backboard and the cascaded RapidIO test board cards are of the structure for realizing the receiving synchronization of the multi-path RapidIO test board cards.
Compared with the prior art, the beneficial effect of this disclosure is:
(1) the GPS time system module is not needed, so that the cost is low; the hardware circuit composition of the multipath RapidIO test board cards is completely the same, the production, debugging and management are convenient, the signal synchronization of the multipath board cards can be realized from the operation of hardware only by switching a master mode and a slave mode through a dial switch, the multiplexing and the cascading of the multipath board cards are realized, the use is simple and convenient, and the implementation is easy.
(2) The synchronous start signal generating device and the synchronous clock generating device are arranged on each test board card, when synchronous receiving is not needed, the multiple RapidIO test board cards can be detached and used independently, each test board card can work in a master mode, data receiving is carried out by using the clocks and the start signals generated by the test board cards, and meanwhile hardware circuits of all the test board cards are completely the same, so that production, debugging and management are facilitated.
(3) The synchronous clock is generated by adopting the crystal oscillator and is cascaded in a hardware mode, the synchronous starting signal is generated by adopting the FPGA and is cascaded in the hardware mode, and the synchronous precision is high and can be less than 1 mu s.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure and not to limit the disclosure.
Fig. 1 is a schematic diagram of a connection structure for realizing clock signal synchronization of a plurality of RapidIO test boards according to the embodiment of the present disclosure;
fig. 2 is a schematic diagram of a connection structure for realizing synchronization start signal unification of multiple RapidIO test boards according to the embodiment of the present disclosure;
FIG. 3 is a flow chart of a synchronization method for receiving synchronization of a plurality of RapidIO test boards in the embodiment of the present disclosure;
the specific implementation mode is as follows:
the present disclosure is further described with reference to the following drawings and examples.
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise. It should be noted that, in the case of no conflict, the embodiments and features in the embodiments in the present disclosure may be combined with each other. The embodiments will be described in detail below with reference to the accompanying drawings.
In the technical solutions disclosed in one or more embodiments, as shown in fig. 1, a structure for realizing the receiving synchronization of multiple RapidIO test boards includes a backplane and a plurality of cascaded RapidIO test boards, each RapidIO test board is provided with a synchronous clock output interface, a synchronous clock input interface, a synchronous clock generation device and a clock selector, and the synchronous clock input interface of each RapidIO test board is connected with the synchronous clock output interface of the first-level RapidIO test board; the input end of each RapidIO test board card clock selector is respectively connected with a synchronous clock generating device and a synchronous clock input interface of the RapidIO test board card; the clock selector is used for selecting a clock signal of the RapidIO test board card and transmitting the clock signal to the next RapidIO test board card.
Optionally, the cascade connection of the RapidIO test board cards may be a series connection mode.
As a further improvement, each RapidIO test board card is further provided with a synchronization start signal generation device and a second selector, and the input end of the second selector is connected with the synchronization start signal generation device and the output end of the second selector of the previous RapidIO test board card; the second selector is used for selecting a synchronization start signal of the current RapidIO test board card and transmitting the selected synchronization start signal to the next RapidIO test board card;
as an achievable structure, the synchronous clock generation device may be a crystal oscillator, the crystal oscillator is arranged on each test board card, and can generate clock signals, so that the clock on any RapidIO test board card can be used as the clock signal of the whole multipath RapidIO test board card.
Alternatively, the clock selector may be a multiplexer or a multiplexer switch. In some embodiments, the path selection of the multi-path selection switch can be realized by arranging a first dial switch which is connected with the path selection end of the multi-path selector.
In some embodiments, the synchronization start signal generation module is an FPGA module disposed on each RapidIO test board.
Alternatively, the second selector may be a multiplexer or a multiplexer switch. In some embodiments, the path selection of the multi-path selection switch can be realized by arranging a second dial switch, and the second dial switch is connected with the path selection end of the multi-path selector. The first toggle switch and the second toggle switch may be configured as the same switch.
In some embodiments, the second selector on the current RapidIO test board is connected to an input end of the second selector on the next RapidIO test board through a signal line of the backplane.
The structure for realizing the receiving synchronization of the multiple RapidIO test boards in the embodiment is described below by taking a specific example, specifically taking three RapidIO test boards as an example for description:
the RapidIO test board of this embodiment adopts the CPCI bus standard, and sets a working mode of the current RapidIO test board by setting a dial switch, and the working mode can determine the selection of a clock signal and the selection of a synchronization start signal of the current RapidIO test board, and the working mode can include a master mode and a slave mode, and a clock signal generated by a crystal oscillator on the RapidIO test board set as the master mode and a synchronization start signal generated by an FPGA module serve as synchronization signals of the entire multi-path system.
1) Generating a synchronous clock signal: the RapidIO test board card adopts the CPCI bus standard, as shown in fig. 1, firstly, the working modes of a plurality of RapidIO test board cards are set through a dial switch, and the working modules are divided into a master mode and a slave mode. And only one board card is set as a master mode, and the other board cards are set as slave modes.
Each RapidIO test board card comprises a crystal oscillator, and each board card generates an independent clock signal through the crystal oscillator. If the current board card is in the master mode, directly adopting a clock signal generated by a crystal oscillator on the board card as a synchronous clock of the multiple board cards, and simultaneously connecting the clock signal to an external synchronous clock input interface of a next-stage slave mode board card through an external synchronous clock output interface; if the current board card is in the slave mode, the clock signal generated by the crystal oscillator on the board card is not adopted, and an external synchronous clock input interface is adopted as a synchronous clock.
2) Generating a synchronization start signal: as shown in fig. 2, each test board generates an independent synchronization start signal through the FPGA on the board. If the current board card is in the master mode, the synchronous start signal generated by the board card is used as the synchronous start signal when a plurality of RapidIO test board cards receive data, and meanwhile, the synchronous start signal is transmitted to the other board cards through a reserved signal line on the CPCI backboard; and if the current board card is in the slave mode, the synchronous start signal generated by the board card is not adopted, and the synchronous start signal transmitted from the CPCI backboard by the main mode board card is adopted. The reserved signal line on the CPCI backplane can be selected from the B5 pin of J1.
When data are synchronously received among the multiple RapidIO test board cards, the master mode board card generates a synchronous clock signal and transmits the synchronous clock signal to the slave mode board cards step by step; the master mode board card sends out a synchronization start signal and starts to receive data at the same time, and the slave mode board card starts to receive data after receiving the synchronization start signal.
The embodiment further provides a synchronization method based on the structure for realizing the receiving synchronization of the multiple RapidIO test boards, which specifically includes the following steps:
step 2, the master mode board card adopts a clock signal generated by a crystal oscillator on the board card as a synchronous clock of the board card, and simultaneously transmits the clock signal to the slave mode board card step by step;
step 3, the slave mode board card adopts a clock signal transmitted by the master mode board card as a synchronous clock;
step 4, the master mode board card generates a synchronization start signal and starts to receive data, and the synchronization start signal is transmitted to the slave mode board card;
and 5, receiving a synchronization starting signal of the master mode board card from the slave mode board card, and starting to receive data.
The working modes of the multipath RapidIO test board cards comprise a master mode and a slave mode, the master mode board card adopts a synchronous clock signal and a synchronous start signal generated on the board card, and the slave mode board card adopts the two received signals as the synchronous clock signal and the synchronous start signal of the slave mode board card.
In step 2, the transmission of the synchronous clock signal can be transmitted to the slave mode board card through an external synchronous clock interface on the test board, and the synchronous start signal can be transmitted to the slave mode board card through a reserved signal line on the CPCI backplane.
Optionally, the working mode of the RapidIO test board card may be selected through hardware operation. And in the step 1, switching setting is carried out on the RapidIO test board card to be in a master mode or in a slave mode through a dial switch. The channel selection end of the multi-path selector serving as the clock selector and the second selector can be selected through the dial switch, the main mode is to gate the channel of a clock signal generated by a crystal oscillator arranged on a test board of the clock selector, and the channel of a synchronous starting signal generated by an FPGA module on the test board of the second selector is gated. The slave mode is to gate the channel of the clock signal transmitted by the clock selector with the other test board received, and to gate the channel of the second selector with the synchronization start signal transmitted by the other test board received.
The embodiment also provides a test device, the test device at least comprises a backboard and a plurality of cascaded RapidIO test boards, and the backboard and the plurality of cascaded RapidIO test boards are of the structure for realizing the receiving synchronization of the multipath RapidIO test boards.
The embodiment does not need a GPS time system module, so the cost is low; hardware circuit composition among the multipath RapidIO test board cards can be set to be the same structure, multiplexing and cascading of the multipath board cards can be achieved only by switching a master mode and a slave mode through a dial switch, and the RapidIO test board card is simple and convenient to use and easy to implement.
The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure, and various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.
Although the present disclosure has been described with reference to specific embodiments, it should be understood that the scope of the present disclosure is not limited thereto, and those skilled in the art will appreciate that various modifications and changes can be made without departing from the spirit and scope of the present disclosure.
Claims (10)
1. Realize that multichannel rapidIO test board card receives synchronous structure, characterized by: the system comprises a back plate and a plurality of cascaded RapidIO test board cards, wherein each RapidIO test board card is provided with a synchronous clock output interface, a synchronous clock input interface, a synchronous clock generation device and a clock selector, and the synchronous clock input interface of each RapidIO test board card is connected with the synchronous clock output interface of the first-stage RapidIO test board card; the input end of each RapidIO test board card clock selector is respectively connected with a synchronous clock generating device and a synchronous clock input interface of the RapidIO test board card; the clock selector is used for selecting a clock signal of the RapidIO test board card and transmitting the clock signal to the next RapidIO test board card.
2. The structure for realizing the receiving synchronization of the multipath RapidIO test boards as claimed in claim 1, characterized in that: each RapidIO test board card is also provided with a synchronization start signal generation device and a second selector, and the input end of the second selector is connected with the synchronization start signal generation device and the output end of the second selector of the previous RapidIO test board card; the second selector is used for selecting a synchronization start signal of the current RapidIO test board card and transmitting the selected synchronization start signal to the next RapidIO test board card.
3. The structure for realizing the receiving synchronization of the multipath RapidIO test boards as claimed in claim 2, characterized in that: the synchronous start signal generating device is an FPGA module arranged on each RapidIO test board card.
4. The structure for realizing the receiving synchronization of the multipath RapidIO test boards as claimed in claim 2, characterized in that: the second selector is a multi-channel selector, and the channel selection end of the second selector is connected with the second dial switch to realize channel selection.
5. The structure for realizing the receiving synchronization of the multipath RapidIO test boards as claimed in claim 1, characterized in that: the synchronous clock generating device is a crystal oscillator.
6. The structure for realizing the receiving synchronization of the multipath RapidIO test boards as claimed in claim 1, characterized in that: the clock selector is a multi-channel selector, the path selection is realized by arranging a first dial switch, and the first dial switch is connected with a channel selection end of the clock selector.
7. The method for synchronizing the structure for realizing the receiving synchronization of the multipath RapidIO test boards as claimed in any one of claims 1 to 6, which is characterized by comprising the following steps:
setting one RapidIO test board card of the plurality of RapidIO test board cards as a master mode board card, and setting the other RapidIO test board cards as slave mode board cards;
the master mode board card adopts a clock signal generated by a crystal oscillator on the board card as a synchronous clock of the board card, and simultaneously transmits the clock signal to the slave mode board card step by step;
the slave mode board card adopts a clock signal transmitted by the master mode board card as a synchronous clock;
the master mode board card generates a synchronization start signal and starts to receive data, and transmits the synchronization start signal to the slave mode board card;
and the slave mode board card receives a synchronization starting signal of the master mode board card and starts to receive data.
8. The synchronization method of claim 7, wherein: the master mode board card adopts a synchronous clock signal and a synchronous start signal generated on the board card, and the slave mode board card adopts two signals received from other test board cards as the synchronous clock signal and the synchronous start signal of the slave mode board card.
9. The synchronization method of claim 7, wherein: and setting the RapidIO test board card as a master mode board card or a slave mode board card to be switched and set through the first dial switch and the second dial switch.
10. A test device is characterized in that: the multi-path RapidIO test board card receiving synchronization structure comprises a backboard and a plurality of cascaded RapidIO test board cards, wherein the backboard and the plurality of cascaded RapidIO test board cards adopt the structure for realizing the receiving synchronization of the multi-path RapidIO test board cards in any one of claims 1-6.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11697410B2 (en) * | 2019-03-07 | 2023-07-11 | Toyota Jidosha Kabushiki Kaisha | Vehicle-to-everything communication-based lane change collision avoidance warning |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100080210A1 (en) * | 2008-09-29 | 2010-04-01 | Samsung Electronics Co., Ltd. | System clock synchronization apparatus and method for mobile communication system |
| CN102004622A (en) * | 2010-11-17 | 2011-04-06 | 广东威创视讯科技股份有限公司 | Multiprocessor display system and method |
| CN103067148A (en) * | 2012-07-27 | 2013-04-24 | 杭州亿恒科技有限公司 | Hardware synchronization method of cascading instrument |
-
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- 2019-10-30 CN CN201911045730.2A patent/CN110808804A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100080210A1 (en) * | 2008-09-29 | 2010-04-01 | Samsung Electronics Co., Ltd. | System clock synchronization apparatus and method for mobile communication system |
| CN102004622A (en) * | 2010-11-17 | 2011-04-06 | 广东威创视讯科技股份有限公司 | Multiprocessor display system and method |
| CN103067148A (en) * | 2012-07-27 | 2013-04-24 | 杭州亿恒科技有限公司 | Hardware synchronization method of cascading instrument |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11697410B2 (en) * | 2019-03-07 | 2023-07-11 | Toyota Jidosha Kabushiki Kaisha | Vehicle-to-everything communication-based lane change collision avoidance warning |
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