CN110753580B - Flow channel structure device and its manufacturing method - Google Patents
Flow channel structure device and its manufacturing method Download PDFInfo
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Abstract
一种流道结构器件及其制造方法，涉及半导体技术领域。该方法包括：提供第一基片(21)；在该第一基片(21)中形成第一沟槽(31)；在该第一基片(21)上形成材料层(43)，其中该材料层(43)的一部分形成在该第一沟槽(31)中以形成第二沟槽(32)；在该材料层(43)上形成牺牲层(45)，该牺牲层(45)包括填充在该第二沟槽(32)中的第一部分(451)；将形成该牺牲层(45)后的第一基片(21)与第二基片(47)键合，使得该材料层(43)位于该第一基片(21)与该第二基片(47)之间；对该第一基片(21)的背面进行减薄处理，以露出该牺牲层(45)的第一部分(451)；以及利用选择性刻蚀工艺去除该第一部分(451)，从而形成流道(50)。该方法可以实现具有垂直流道的流道结构器件。
A flow channel structure device and a manufacturing method thereof relate to the technical field of semiconductors. The method comprises: providing a first substrate (21); forming a first trench (31) in the first substrate (21); forming a material layer (43) on the first substrate (21), wherein A portion of the material layer (43) is formed in the first trench (31) to form a second trench (32); a sacrificial layer (45) is formed on the material layer (43), the sacrificial layer (45) comprising a first portion (451) filled in the second trench (32); bonding the first substrate (21) with the second substrate (47) after the sacrificial layer (45) is formed, so that the material A layer (43) is located between the first substrate (21) and the second substrate (47); the backside of the first substrate (21) is thinned to expose the sacrificial layer (45) a first portion (451); and removing the first portion (451) using a selective etching process, thereby forming a flow channel (50). The method can realize a flow channel structure device with vertical flow channels.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a flow channel structure device and a manufacturing method thereof.
Background
The micro-nanofluidic analysis technology based on micro-nanofluidic channels is increasingly researched and applied in the fields of biochemical analysis, gene sequencing and the like. The combination of the micro-nano flow channel device and an Integrated Circuit (IC for short) is also helpful to promote the automation and miniaturization of a micro-analysis system and better expand the application space of the micro-analysis system. In some applications, it is necessary to embed electrode materials in the micro-nano flow channel, and in some designs, it is necessary to have a nano flow channel with a high aspect ratio.
In the traditional method, electron beam lithography or laser lithography can be adopted, and an anisotropic etching process is combined to realize the nano flow channel. However, the direct electron beam or laser lithography method has low efficiency and poor size adjustability, and it is difficult to achieve high aspect ratios, usually only about 1, on metal materials.
In the prior art, the micro-nano flow channel structure can also be realized by a side wall method. However, the sidewall method must rely on a semiconductor material sidewall support structure to realize structure interconnection and signal extraction, which may cause more parasitic effects and finally affect the quality of the detection signal, and the process thermal budget is high, which is not favorable for integration with the CMOS chip. For example, most of the electrode extraction in the prior art needs to rely on the alloy structure extraction of a spliced metal interconnection line (for example, aluminum and copper are typical materials) or a semiconductor interconnection line (for example, polysilicon is a typical material) and an electrode material. However, the alloy structure has the following disadvantages: (1) the alloying process requires an additional thermal treatment process, which increases the thermal budget of the process, and is not favorable for implementing process integration on an IC chip, and for example, a typical polysilicon interconnection process requires a high thermal budget process technology such as a polysilicon deposition process (typically, a temperature higher than 600 ℃), ion implantation and activation (typically, 550 ℃) and a metal semiconductor alloy (typically, 400 ℃); (2) the alloy body will introduce additional contact resistance which will degrade device performance. In addition, there is a lateral flow channel structure of metal leads in the prior art, but in such a lateral flow channel structure, the metal electrodes are respectively distributed on the upper and lower sides of the flow channel, which may affect the application range, for example, it cannot be used for applications including light emission, because the light signal will be blocked by the upper and lower electrodes. Moreover, such lateral flow channel structures also limit the manufacturing density on the chip.
In the prior art, the nanometer gap structure can be realized by adjusting the metal sputtering angle. In the sputtering process, a certain angle exists between the sputtering direction of particles and the surface of a substrate, and the bottom of a groove prepared in advance can generate a sputtering dead angle by adjusting the angle, so that a nanogap flow channel structure is obtained, but the process controllability and the size adjustability are poor.
Disclosure of Invention
The inventors of the present invention have found that there are problems in the above-mentioned prior art, and thus have proposed a new technical solution to at least one of the problems.
According to a first aspect of the present invention, there is provided a method of manufacturing a flow channel structure device, comprising: providing a first substrate; forming a first trench in the first substrate; forming a material layer on the first substrate, wherein a portion of the material layer is formed in the first trench to form a second trench; forming a sacrificial layer on the material layer, the sacrificial layer including a first portion filled in the second trench; bonding the first substrate and the second substrate after the sacrificial layer is formed, so that the material layer is located between the first substrate and the second substrate; thinning the back surface of the first substrate to expose a first part of the sacrificial layer; and removing the first portion by using a selective etching process, thereby forming a flow channel.
In one embodiment, in the step of thinning the back surface of the first substrate, the material layer is also exposed; before removing the first portion using a selective etch process, the method further comprises: and forming a cap layer on the back side of the thinned first substrate, wherein the cap layer covers the first part of the sacrificial layer.
In one embodiment, the material of the cap layer comprises: an insulating dielectric material or a semiconductor material; the cap layer has a thickness in a range from 1 nanometer to 10 micrometers.
In one embodiment, in the step of removing the first portion using a selective etching process, a selective etching liquid is injected from an edge side of the second trench to remove the first portion.
In one embodiment, prior to removing the first portion using a selective etch process, the method further comprises: etching the cap layer to form a through hole which penetrates through the cap layer and exposes the first part; wherein, in the step of removing the first portion by using a selective etching process, a selective etching liquid is injected from the through hole to remove the first portion.
In one embodiment, in the step of forming a sacrificial layer on the material layer, the sacrificial layer further includes: a second portion formed outside the second trench.
In one embodiment, the second portion of the sacrificial layer is bonded to the second substrate in the step of bonding the first substrate after the sacrificial layer is formed to the second substrate.
In one embodiment, in the step of forming a material layer on the first substrate, another portion of the material layer is formed outside the first trench; before bonding the first substrate and the second substrate after forming the sacrificial layer, the method further comprises: removing the second portion of the sacrificial layer to expose a portion of the material layer outside the first trench; and bonding the part of the material layer outside the first groove and the second substrate in the step of bonding the first substrate and the second substrate after the sacrificial layer is formed.
In one embodiment, in the step of removing the first portion using a selective etching process, the selective etching process further removes a portion of the second portion corresponding to the flow channel, thereby breaking the second portion.
In one embodiment, the step of forming a first trench in the first substrate comprises: forming a patterned mask layer on the first substrate; etching the first substrate by taking the mask layer as a mask to form a first groove; and removing the mask layer.
In one embodiment, the material of the material layer comprises: a metallic material or a semiconductor material; wherein a portion of the material layer in the first trench serves as an electrode of the flow channel structure device; the portion of the material layer between the first substrate and the second substrate serves as a lead of the electrode.
In one embodiment, the material of the material layer comprises: an insulating dielectric material.
In one embodiment, the width of the first trench ranges from 10 nanometers to 100 micrometers, and the depth of the first trench ranges from 10 nanometers to 1 millimeter; the thickness of the material layer ranges from 1 nanometer to 50 micrometers; the width range of the flow channel is 0.1 nanometer to 1 micrometer; the thickness of the sacrificial layer is larger than one half of the width of the flow channel.
In the above manufacturing method of the present invention, the first trench is formed in the first substrate, and then the material layer filling the first trench is formed on the first substrate, thereby forming the second trench; then forming a sacrificial layer on the material layer so as to fill the second trench; then bonding the first substrate and the second substrate; thinning the back surface of the first substrate to expose a first part of the sacrificial layer; and removing the first portion by using a selective etching process, thereby forming a flow channel. The manufacturing method can form the flow channel structure device with the vertical flow channel, and the manufacturing method can reduce the process thermal budget and is convenient for the integration of the flow channel structure device and the CMOS chip.
Further, the manufacturing method can realize the flow channel structure with high aspect ratio.
Further, in the above-described manufacturing method, since the material of the material layer may be a metal material or a semiconductor material, a portion of the material layer in the first trench may be used as an electrode embedded in the flow channel.
Further, in the above-described manufacturing method, a portion of the material layer in the first trench and a portion outside the first trench are formed together. In the case where the portion of the material layer in the first trench serves as an electrode, the portion of the material layer outside the first trench (i.e., the portion located between the first substrate and the second substrate) may serve as a lead of the electrode, which may reduce contact resistance.
According to a second aspect of the present invention, there is provided a flow channel structure device comprising: a first substrate formed with a trench penetrating the first substrate; a second substrate bonded to the first substrate; and a material layer, wherein a portion of the material layer is located on a sidewall of the trench and forms a flow channel, and another portion of the material layer is located between the first substrate and the second substrate.
In one embodiment, the flow channel structure device further comprises: and the cover cap layer is arranged on the first substrate, and covers the flow channel.
In one embodiment, the material of the cap layer comprises: an insulating dielectric material or a semiconductor material; the cap layer has a thickness in a range from 1 nanometer to 10 micrometers.
In one embodiment, the flow channel structure device further comprises: and the through hole penetrates through the cap layer and is communicated with the flow channel.
In one embodiment, the flow channel structure device further comprises: a sacrificial layer between the material layer and the second substrate.
In one embodiment, the sacrificial layer is broken at a position corresponding to the flow channel.
In one embodiment, the material of the material layer comprises: a metallic material or a semiconductor material; wherein a portion of the material layer on a sidewall of the trench serves as an electrode of the flow channel structure device; the portion of the material layer between the first substrate and the second substrate serves as a lead of the electrode.
In one embodiment, the material of the material layer comprises: an insulating dielectric material.
In one embodiment, the width of the trench ranges from 10 nanometers to 100 micrometers, and the depth of the trench ranges from 10 nanometers to 1 millimeter; the thickness of the material layer ranges from 1 nanometer to 50 micrometers; the width range of the flow channel is 0.1 nanometer to 1 micrometer; the thickness of the sacrificial layer is larger than one half of the width of the flow channel.
The flow channel structure device of the above embodiment of the present invention has the vertical flow channel, which can improve the manufacturing density of the flow channel on the chip, can improve the application throughput, and reduce the manufacturing and application costs, etc.
Further, the flow channel structure device can realize a flow channel structure with a high depth-to-width ratio.
Further, in the case where the material layer uses a metal material or a semiconductor material, it may be realized that the electrode is embedded in the flow channel, that is, a portion of the material layer in the first trench may serve as an electrode, and a portion of the material layer between the first substrate and the second substrate may serve as a lead of the electrode, which may reduce contact resistance.
According to a third aspect of the present invention, there is provided a flow channel sensor comprising: a flow channel structure device as hereinbefore described.
According to a fourth aspect of the present invention, there is provided a biochemical analysis apparatus comprising: a flow channel structure device as hereinbefore described.
According to a fifth aspect of the present invention, there is provided a chip for molecular detection, comprising: the flow channel structure device, the signal collecting unit and the signal processing unit are as described above; the method comprises the following steps that a sample to be detected is added into a flow channel of a flow channel structure device, and under the condition that an electrode of the flow channel structure device is applied with electric excitation, target molecules in the sample to be detected generate electric signals or optical signals under the action of the electric excitation; the signal collecting unit is used for collecting the electric signal or the optical signal and transmitting the electric signal or the optical signal to the signal processing unit; the signal processing unit is used for carrying out signal processing on the electric signal or the optical signal and identifying the information of the target molecule.
According to a sixth aspect of the present invention, there is provided a molecular detection method comprising: molecular detection was performed using the chip as described previously.
In one embodiment, the step of performing molecular detection using the chip comprises: processing a sample to be detected; adding the sample to be detected into the chip; applying electric excitation to electrodes in a flow channel structure device in the chip to enable target molecules in the sample to be detected to generate an electric signal or an optical signal under the action of the electric excitation; and the signal processing unit of the chip acquires the electric signal or the optical signal through the signal collecting unit, and performs signal processing on the electric signal or the optical signal to identify the information of the target molecule.
In the above embodiments, the application of molecular detection is realized by using a chip including the flow channel structure device of the embodiments of the present invention.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
The invention will be more clearly understood from the following detailed description, taken with reference to the accompanying drawings, in which:
fig. 1 is a flowchart illustrating a method of manufacturing a flow channel structure device according to an embodiment of the present invention.
Fig. 2 is a cross-sectional view schematically illustrating the structure at a stage in the fabrication of a flow channel structure device according to an embodiment of the present invention.
Fig. 3 is a cross-sectional view schematically illustrating the structure at a stage in the fabrication of a flow channel structure device according to an embodiment of the present invention.
Fig. 4 is a cross-sectional view schematically illustrating the structure at a stage in the fabrication of a flow channel structure device according to an embodiment of the present invention.
Fig. 5 is a cross-sectional view schematically illustrating the structure at a stage in the fabrication of a flow channel structure device according to an embodiment of the present invention.
Fig. 6 is a cross-sectional view schematically illustrating the structure at a stage in the fabrication of a flow channel structure device according to an embodiment of the present invention.
Fig. 7 is a cross-sectional view schematically illustrating the structure at a stage in the fabrication of a flow channel structure device according to an embodiment of the present invention.
Fig. 8 is a cross-sectional view schematically illustrating the structure at a stage in the fabrication of a flow channel structure device according to an embodiment of the present invention.
Fig. 9 is a cross-sectional view schematically illustrating the structure at a stage in the fabrication of a flow channel structure device according to an embodiment of the present invention.
Fig. 10 is a cross-sectional view schematically illustrating the structure at a stage in the fabrication of a flow channel structure device according to an embodiment of the present invention.
Fig. 11 is a cross-sectional view schematically illustrating a structure at a stage in the fabrication of a flow channel structure device according to another embodiment of the present invention.
Fig. 12 is a cross-sectional view schematically illustrating a structure at a stage in the fabrication of a flow channel structure device according to another embodiment of the present invention.
Fig. 13 is a cross-sectional view schematically illustrating a structure at a stage in the fabrication of a flow channel structure device according to another embodiment of the present invention.
Fig. 14 is a top view schematically illustrating a structure at a stage in the fabrication of a flow channel structure device according to another embodiment of the present invention.
Fig. 15 is a cross-sectional view schematically illustrating a structure at a stage in the fabrication of a flow channel structure device according to another embodiment of the present invention.
Fig. 16 is a cross-sectional view schematically illustrating a structure at a stage in the fabrication of a flow channel structure device according to another embodiment of the present invention.
Fig. 17 is a cross-sectional view schematically illustrating a structure at a stage in the fabrication of a flow channel structure device according to another embodiment of the present invention.
Fig. 18 is a cross-sectional view schematically illustrating a structure at a stage in the fabrication of a flow channel structure device according to another embodiment of the present invention.
Fig. 19 is a cross-sectional view schematically illustrating a structure at a stage in the fabrication of a flow channel structure device according to another embodiment of the present invention.
FIG. 20 is a structural view schematically showing a chip for molecular detection according to an embodiment of the present invention.
FIG. 21 is a flow chart illustrating a method of molecular detection according to one embodiment of the present invention.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
Fig. 1 is a flowchart illustrating a method of manufacturing a flow channel structure device according to an embodiment of the present invention. Fig. 2 to 10 are cross-sectional views schematically showing the structure at several stages in the manufacturing process of a flow channel structure device according to an embodiment of the present invention. A process of manufacturing a flow channel structure device according to an embodiment of the present invention is described in detail below with reference to fig. 1 and fig. 2 to 10.
As shown in fig. 1, in step S101, a first substrate is provided.
Fig. 2 is a cross-sectional view schematically showing the structure at step S101 in the manufacturing process of the flow channel structure device according to one embodiment of the present invention. As shown in fig. 2, a first substrate 21 is provided. For example, the first substrate 21 may include: a semiconductor substrate (e.g., silicon, germanium, etc.), an insulating substrate (e.g., quartz, silicon nitride, etc.), a wafer into which IC circuitry has been integrated, or any combination of these substrates.
Returning to fig. 1, in step S102, a first trench is formed in the first substrate. The process of implementing this step S102 according to one embodiment of the present invention is described in detail below with reference to fig. 3 to 5.
In one embodiment, the step S102 may include: as shown in fig. 3, a patterned mask layer 22 is formed on a first substrate 21. For example, a patterned mask layer 22 may be obtained on the first substrate 21 using a lithographic process. The material of the mask layer may include photoresist or the like. The photolithography process may include: optical lithography, electron beam lithography, nanoimprint lithography, focused ion beam lithography, or the like.
Next, the step S102 may further include: as shown in fig. 4, the first substrate 21 is etched using the mask layer 22 as a mask to form a first trench 31. For example, an anisotropic etch process may be used to etch the first substrate to form the first trench. The anisotropic etching process may include: dry etching process or wet etching process, etc. In one embodiment, the width of the first trench 31 may range from 10nm to 100 μm. For example, the width of the first trench 31 may be 100 nm, 500 nm, 1 micron, 10 microns, or 50 microns. In one embodiment, the depth of the first trench 31 may range from 10nm to 1 mm. For example, the depth of the first trench 31 may be 100 nm, 500 nm, 1 micron, 10 microns, 100 microns, or 500 microns, etc.
Next, the step S102 may further include: as shown in fig. 5, the mask layer 22 is removed. To this end, a first trench 31 is formed in the first substrate 21.
Returning to fig. 1, in step S103, a material layer is formed on the first substrate, wherein a portion of the material layer is formed in the first trench to form a second trench.
Fig. 6 is a cross-sectional view schematically showing the structure at step S103 in the manufacturing process of the flow channel structure device according to one embodiment of the present invention. As shown in fig. 6, a material layer 43 may be formed on the first substrate 21, for example, by a deposition process. A portion of the material layer 43 is formed in the first trench 31, and the width of the first trench 31 is reduced, thereby forming the second trench 32. In this step S103, as shown in fig. 6, another portion of the material layer 43 is formed outside the first trench 31, i.e., the other portion is formed on the upper surface of the first substrate 21.
In one embodiment, the material of the material layer 43 may include: a metallic material (e.g., gold, platinum, silver, titanium nitride, etc., or a combination of metals) or a semiconductor material (e.g., polysilicon, amorphous silicon, indium tin oxide, etc., or a combination of semiconductor materials). After the flow channel structure device is formed subsequently, in the case that the material layer 43 is made of a conductive material such as a metal material or a semiconductor material, a portion of the material layer 43 in the first trench 31 may serve as an electrode of the flow channel structure device; the portion of the material layer 43 outside the first trench, i.e., the portion between the first substrate and a second substrate (to be described later), serves as a lead of the electrode. In another embodiment, the material of the material layer 43 may include: an insulating dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc., or combinations of multiple insulating dielectric materials). This allows the formation of a flow channel structure device surrounded by an insulating medium in a subsequent step.
In one embodiment, the thickness of the material layer 43 may range from 1 nanometer to 50 micrometers. For example, the thickness of the material layer 43 may be 10 nanometers, 100 nanometers, 500 nanometers, 1 micron, 10 microns, or the like. In one embodiment, the width of the second trench 32 may range from 0.1 nm to 1 μm. For example, the width of the second trench 32 may be 1 nm, 10nm, 100 nm, or 500 nm. In the following steps, the second groove is used for forming a flow channel, and the width of the second groove is the width of the flow channel.
Returning to fig. 1, in step S104, a sacrificial layer is formed on the material layer, the sacrificial layer including the first portion filled in the second trench.
Fig. 7 is a cross-sectional view schematically showing the structure at step S104 in the manufacturing process of the flow channel structure device according to one embodiment of the present invention. As shown in fig. 7, a sacrificial layer 45 is formed on the material layer 43 to fill the second trench 32. The sacrificial layer 45 may include a first portion 451 filled in the second trench 32. The sacrificial layer 45 may further include: a second portion 452 is formed outside the second trench 32. As shown in fig. 7, the second portion 452 is formed on the material layer 43 above the upper surface of the first substrate 21.
In one embodiment, the material of the sacrificial layer 45 may include: a metal material (e.g., chromium, aluminum, titanium, etc., or a combination of multiple metal materials), a semiconductor material (e.g., polysilicon, amorphous silicon, indium tin oxide, etc., or a combination of multiple semiconductor materials), or an insulating dielectric material (e.g., silicon dioxide, silicon nitride, etc., or a combination of multiple insulating dielectric materials), and so forth. The material of the sacrificial layer 45 is not limited to metal or nonmetal, and is selected mainly according to and standard with the corrosion selectivity between the material of the sacrificial layer 45 and the material of the material layer 43 as the damascene electrode, and generally, the larger the corrosion selectivity ratio, the better. For example, when some metal materials are used as the electrodes, other materials with high corrosion selectivity can be selected to match the corresponding sacrificial layer materials.
In one embodiment, the thickness of the sacrificial layer 45 may be determined according to the width of the second trench (i.e., the width of the flow channel formed in the subsequent step) to ensure that the second trench 32 is filled. The width and thickness of the second trench 32 are determined by design requirements and are obtained by filling the first trench with a material layer 43, i.e. the second trench corresponds to the gap sandwiched between the two side material layers 43 filled in the first trench. While the thickness of the sacrificial layer 45 is greater than 1/2 (one-half) the width of the gap to ensure that the sacrificial layer 45 can completely fill the gap. I.e., the sacrificial layer 45 has a thickness greater than one-half the width of the flow channel (to be formed in a subsequent step).
In an embodiment of the present invention, the sacrificial layer 45 may be formed by a physical Deposition (e.g., sputtering), a Chemical Deposition (e.g., CVD (Chemical Vapor Deposition)), or an electroplating process.
Returning to fig. 1, in step S105, the first substrate after the sacrificial layer is formed is bonded to the second substrate such that the material layer is located between the first substrate and the second substrate.
Fig. 8 is a cross-sectional view schematically showing the structure at step S105 in the manufacturing process of the flow channel structure device according to one embodiment of the present invention. As shown in fig. 8, the first substrate 21 after the formation of the sacrificial layer is bonded to the second substrate 47 such that the material layer 43 is located between the first substrate 21 and the second substrate 47, for example, such that the portion of the material layer 43 outside the first trench 31 is located between the first substrate 21 and the second substrate 47. In one embodiment, in the step S105, as shown in fig. 8, the second portion 452 of the sacrificial layer 45 is bonded to the second substrate 47. In one embodiment, the second substrate 47 may comprise: a semiconductor substrate (e.g., silicon, germanium, etc.), an insulating substrate (e.g., quartz, silicon nitride, etc.), a wafer into which IC circuitry has been integrated, or any combination of these substrates.
Returning to fig. 1, in step S106, the back surface of the first substrate is thinned to expose the first portion of the sacrificial layer.
Fig. 9 is a cross-sectional view schematically showing the structure at step S106 in the manufacturing process of the flow channel structure device according to one embodiment of the present invention. As shown in fig. 9, after bonding the first substrate 21 to the second substrate 47, the back surface of the first substrate 21 is subjected to a thinning process, for example, by a Chemical Mechanical Polishing (CMP) process, to expose a first portion 451 of the sacrificial layer 45. In this step of the thinning process, as shown in fig. 9, the material layer 43 is also exposed, i.e., the portion of the material layer 43 in the first trench 31 is exposed.
Returning to fig. 1, in step S107, the first portion is removed by using a selective etching process, thereby forming a flow channel.
Fig. 10 is a cross-sectional view schematically showing the structure at step S107 in the manufacturing process of the flow channel structure device according to one embodiment of the present invention. As shown in fig. 10, the first portion 451 of the sacrificial layer 45 is removed using a selective etching process, thereby forming the flow channel 50. In one embodiment, the width of the flow channel 50 may range from 0.1 nm to 1 μm. For example, the width of the flow channel 50 may be 1 nm, 10nm, 100 nm, or 500 nm. In one embodiment, the thickness of the sacrificial layer 45 is greater than one-half the runner width.
Thus, a method of manufacturing a flow channel structure device according to an embodiment of the present invention is provided. In the method, a first trench is formed in a first substrate, and then a material layer filling the first trench is formed on the first substrate, thereby forming a second trench; then forming a sacrificial layer on the material layer so as to fill the second trench; then bonding the first substrate and the second substrate; thinning the back surface of the first substrate to expose a first part of the sacrificial layer; and removing the first portion by using a selective etching process, thereby forming a flow channel. The fabrication method of the present invention can form a flow channel structure device having vertical flow channels (i.e., flow channels perpendicular to the upper or lower surface of the second substrate). For example, the flow channel may be open or may be provided with a transparent material in a direction perpendicular to the substrate, so that the transmission of the optical signal is not affected. In addition, the vertical flow channel is adopted, so that the effective surface area of a single flow channel is the sectional area of the flow channel, the manufacturing density of the flow channel on the chip can be greatly improved, the manufacturing and application cost is reduced, and the like.
The manufacturing method of the embodiment of the invention can reduce the process thermal budget. For example, the method of the present invention involves a relatively low process temperature (ranging from room temperature to 350 ℃) and a short thermal processing time, thereby reducing the process thermal budget to facilitate the integration of the runner structure device with the CMOS chip.
Further, the manufacturing method can realize the flow channel structure with high aspect ratio. For example, a channel structure with a width of 10nm and an aspect ratio of 100:1 can be realized. The aspect ratio of the flow channel structure realized by the method of the embodiment of the invention may range from 1:1 to 100000: 1.
Further, since the material of the material layer may be a conductive material such as a metal material or a semiconductor material (e.g., a doped semiconductor material), the above-described manufacturing method may realize that 1 electrode, 1 pair of electrodes, or more pairs of electrodes are formed in the flow channel. As shown in fig. 6, an electrode (i.e., a material layer using a metal or semiconductor material) is initially formed, and if no subsequent process is performed, it is considered to have only one electrode; after the subsequent processes, two electrodes may be formed on both sides of the flow channel (for example, a portion of the material layer on the left side of the flow channel may be referred to as a first electrode, and a portion of the material layer on the right side of the flow channel may be referred to as a second electrode), and these two electrodes may serve as a pair of working electrodes. In addition, more pairs of electrodes may be formed on both sides of the flow channel, for example, a plurality of material layer portions distributed along the second trench may be formed by a patterning process in the process of forming the material layer, and then, through the subsequent above process, each material layer portion forms a pair of electrodes on both sides of the flow channel, respectively, so that the plurality of material layer portions form a plurality of pairs of electrodes on both sides of the flow channel.
Further, in the above-described manufacturing method, the portion of the material layer in the first trench and the portion outside the first trench are formed together, for example, by a deposition process. In the case where the portion of the material layer in the first trench serves as an electrode, the portion of the material layer outside the first trench (i.e., the portion located between the first substrate and the second substrate) may implement a lead of the electrode, and in particular, an all-metal connection structure may be employed, which may reduce contact resistance and lead resistance.
By the manufacturing method of the embodiment of the invention, the flow channel structure device according to the embodiment of the invention is also formed. For example, as shown in fig. 10, the flow channel structure device may include: a first substrate 21, wherein a groove 31 penetrating through the first substrate 21 is formed. For example, the width of the trench 31 may range from 10nm to 100 μm, and the depth of the trench 31 may range from 10nm to 1 mm. As shown in fig. 10, the flow channel structure device may further include: and a second substrate 47 bonded to the first substrate 21. The flow channel structure device may further include: a layer of material 43, wherein a portion of the layer of material 43 is located on the sidewalls of the trench 31 and forms the flow channel 50, and another portion of the layer of material 43 is located between the first substrate 21 and the second substrate 47.
In one embodiment, the material of the material layer 43 may include: a metallic material or a semiconductor material. In such a case, the portion of the material layer 43 on the sidewall of the trench 31 serves as an electrode of the flow channel structure device; the portion of the material layer 43 between the first substrate 21 and the second substrate 47 serves as a lead for the electrode.
In another embodiment, the material of the material layer 43 may include: an insulating dielectric material. The flow channel structure device can be applied to some cases where electrodes do not need to be applied in the flow channel by using the insulating dielectric material as the material layer, for example, in some cases, the surface of the flow channel needs to be modified by using a specific insulating dielectric material as the material layer to obtain certain specific effects, such as obtaining a hydrophobic surface or a hydrophilic surface, and in addition, the flow channel structure device can also be applied to fluid formation and control, and the like.
In one embodiment, the thickness of the material layer 43 may range from 1 nanometer to 50 micrometers. In one embodiment, the width of the flow channel 50 may range from 0.1 nm to 1 μm.
In one embodiment, as shown in fig. 10, the flow channel structure device may further include: a sacrificial layer 45 between the material layer 43 and a second substrate 47. The first substrate 21 is bonded to the second substrate 47 through the sacrificial layer 45. For example, the thickness of the sacrificial layer 45 is greater than one-half the width of the flow channel 50.
The flow channel structure device of the above-described embodiment of the present invention has a vertical flow channel, which may be, for example, an open space in a direction perpendicular to the surface of the second substrate or may be provided with a transparent material, and thus this does not affect the transmission of optical signals. In addition, with the vertical flow channel, the effective surface area of a single flow channel can be made to be the cross-sectional area of the flow channel (the cross-sectional area of the flow channel refers to the cross-sectional area of the flow channel taken perpendicular to the depth direction), and the cross-sectional area of the flow channel is much smaller than the area of the electrode (the area of the electrode refers to the extension area of the electrode in the depth direction and the length direction, that is, the area of the electrode is the depth of the electrode x the length of the electrode), so that the manufacturing density of the flow channel on the chip can be greatly increased, the application flux (that is, the number of flow channels per unit area) can be increased, and the manufacturing and application costs and the like can be reduced.
Further, the flow channel structure device can realize a flow channel structure with a high depth-to-width ratio.
Further, in the case where the material layer employs a conductive material such as a metal material or a semiconductor material (e.g., a doped semiconductor material), it is possible to realize embedding of an electrode in the flow channel, that is, a portion of the material layer in the first trench may serve as an electrode, and a portion of the material layer between the first substrate and the second substrate may serve as a lead of the electrode, and since the lead and the electrode are formed together by, for example, a deposition process, contact resistance can be reduced.
Fig. 11 is a cross-sectional view schematically illustrating a structure at a stage in the fabrication of a flow channel structure device according to another embodiment of the present invention.
In one embodiment of the present invention, as shown in fig. 11, in the step of removing the first portion using a selective etching process (i.e., step S107), the selective etching process also removes a portion of the second portion 452 of the sacrificial layer 45 corresponding to the flow channel 50, thereby causing the second portion 452 to be disconnected. In this embodiment, in the case where the material layer uses a metal or semiconductor material as the electrode, when the material of the sacrificial layer also uses a conductive material such as a metal or semiconductor, in order to prevent the sacrificial layer from short-circuiting the electrodes on both sides of the flow channel, in the process of performing the selective etching, a portion of the second portion of the sacrificial layer corresponding to the flow channel is also removed, so that the second portion of the sacrificial layer is disconnected.
By the above manufacturing method, a flow channel structure device as shown in fig. 11 is also formed. In an embodiment of the present invention, the flow channel structure device shown in fig. 11 differs from the flow channel structure device shown in fig. 10 except that it has the same or similar structure as the flow channel structure device shown in fig. 10 (which is not described again here): the sacrificial layer 45 of the flow channel structure device of fig. 11 is broken at a position corresponding to the flow channel 50.
Fig. 12 is a cross-sectional view schematically illustrating a structure at a stage in the fabrication of a flow channel structure device according to another embodiment of the present invention.
In an embodiment of the present invention, before removing the first portion by using the selective etching process (i.e., step S107), the manufacturing method may further include: as shown in fig. 12, a cap layer 60 is formed on the back side of the first substrate 21 after the thinning process, for example, by a deposition process, wherein the cap layer 60 covers the first portion 451 of the sacrificial layer 45. In addition, the cap layer 60 may also cover the material layer 43. After the flow channel is formed subsequently, in the step of forming the flow channel subsequently, the capping layer can seal the upper part of the flow channel, so that a closed flow channel is realized, and parasitic reaction possibly brought by the contact of the surface of the first substrate and the fluid can be avoided. And the cap layer covers the flow channels, so that for some applications requiring fluid (e.g., liquid) to flow in the flow channels, the flow channels covered with the cap layer of this embodiment more readily control the flow of such fluids. In addition, the cap layer can also serve to passivate the backside of the first substrate and the surface of the material layer.
In one embodiment, the material of the cap layer 60 may include: an insulating dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, borophosphosilicate glass, aluminum oxide, titanium oxide, tantalum oxide, or the like) or a semiconductor material (e.g., polysilicon, amorphous silicon, or the like). In one embodiment, the cap layer 60 may have a thickness ranging from 1 nanometer to 10 micrometers. For example, the cap 60 may have a thickness of 10 nanometers, 100 nanometers, 500 nanometers, 1 micron, or 5 microns, etc.
Fig. 13 is a cross-sectional view schematically illustrating a structure at a stage in the fabrication of a flow channel structure device according to another embodiment of the present invention.
In one embodiment of the present invention, in the step of removing the first portion using the selective etching process, as shown in fig. 13, a selective etching liquid may be injected from an edge side of the second trench 32 to remove the first portion 451 of the sacrificial layer 45, thereby forming the flow channel 50. In a practical planar structure the planarly extending material layer is bordered, so that there will be openings at the border of the material layer, i.e. at the edge sides of the second trenches (not shown in the figure), so that a selective etching liquid can be injected from the edge sides of the second trenches to remove the first portions of the sacrificial layer.
By the above manufacturing method, a flow channel structure device as shown in fig. 13 is also formed. In an embodiment of the present invention, the flow channel structure device shown in fig. 13 differs from the flow channel structure device shown in fig. 10 except that it has the same or similar structure as the flow channel structure device shown in fig. 10 (which is not described again here): the flow channel structure device shown in fig. 13 may further include: and a cap layer 60 on the first substrate 21, wherein the cap layer 60 covers the runner 50. In addition, the capping layer may also cover the material layer 43. For example, the material of the cap layer 60 may include: an insulating dielectric material or a semiconductor material. For example, the cap layer 60 may have a thickness ranging from 1 nanometer to 10 micrometers. The cover layer can seal the upper part of the flow channel, so as to realize a closed flow channel and avoid parasitic reaction possibly brought by the contact of the surface of the first substrate and fluid. Also, for some applications where fluid (e.g., liquid) flow is desired in the flow channels, the capped flow channels of this embodiment are easier to control. In addition, the cap layer can also serve to passivate the backside of the first substrate and the surface of the material layer.
In one embodiment, the sacrificial layer 45 of a flow channel structure device such as that shown in fig. 13 can also be broken at locations corresponding to the flow channels 50 using the process steps previously described (not shown in fig. 13).
Fig. 14 is a top view schematically illustrating a structure at a stage in the fabrication of a flow channel structure device according to another embodiment of the present invention.
In another embodiment of the present invention, before removing the first portion using the selective etching process, the manufacturing method may further include: as shown in fig. 14, the cap layer 60 is etched to form a via hole 61 penetrating the cap layer 60 and exposing the first portion 451 (of the sacrificial layer 45). Wherein, in the step of removing the first portion using the selective etching process, a selective etching liquid is injected from the via hole 61 to remove the first portion 451. It will be understood by those skilled in the art that the number, shape, size, etc. of the through holes can be determined according to the design requirements, and the scope of the present invention is not limited to the number, shape, size, etc. of the through holes shown in fig. 14. In this embodiment, a via hole is formed in the cap layer 60, so that in the selective etching process, a selective etching liquid is advantageously injected into the second trench, thereby more conveniently removing the first portion of the sacrificial layer to form the flow channel.
From the above manufacturing method, a flow channel structure device according to an embodiment of the present invention is also formed. Except that the flow channel structure device has the same or similar structure as the flow channel structure device shown in fig. 13 (which is not described here), the flow channel structure device is different from the flow channel structure device shown in fig. 13 in that: the flow channel structure device of this embodiment may further include: a via 61 extending through the cap 60 and communicating with the flow channel 50 (not shown in fig. 14).
Fig. 15 to 18 are cross-sectional views schematically showing the structure at several stages in the manufacturing process of a flow channel structure device according to another embodiment of the present invention.
In an embodiment of the present invention, before bonding the first substrate after the formation of the sacrificial layer with the second substrate (i.e., step S105), the manufacturing method may further include: as shown in fig. 15, the second portion 452 of the sacrificial layer 45 is removed to expose a portion of the material layer 43 outside the first trench 31. This second portion of the sacrificial layer may be removed, for example, using a dry etch, chemical mechanical polishing, or the like. Next, in the step of bonding the first substrate after the formation of the sacrificial layer to the second substrate, as shown in fig. 16, the portion of the material layer 43 outside the first trench 31 is bonded to the second substrate 47. Next, as shown in fig. 17, the back surface of the first substrate 21 is subjected to thinning treatment by, for example, a CMP process to expose the first portion 451 of the sacrificial layer 45. Next, as shown in fig. 18, the first portion 451 of the sacrificial layer 45 is removed using a selective etching process, thereby forming the flow channel 50.
In the above-described embodiments, the second portion of the sacrificial layer (i.e., the portion in the non-runner region) is removed before bonding the first substrate to the second substrate, which can reduce the risk of a short circuit that may occur due to incomplete etching of the second portion of the sacrificial layer. In addition, in the selective etching process, since the etching process may be isotropic, that is, during the etching process, the etching process may also be performed laterally towards both sides, which may cause the sacrificial layer to generate a parasitic flow channel in a region (e.g., between the first substrate and the second substrate) opposite to the non-electrode, which may cause additional errors in practical applications, and therefore, the second portion of the sacrificial layer is removed before the first substrate is bonded to the second substrate, which may also reduce the possibility of generating the parasitic flow channel.
By the above manufacturing method, a flow channel structure device as shown in fig. 18 is also formed. As shown in fig. 18, the flow channel structure device may include: a first substrate 21, wherein a groove 31 penetrating through the first substrate 21 is formed. The flow channel structure device may further include: and a second substrate 47 bonded to the first substrate 21. The flow channel structure device may further include: a layer of material 43, wherein a portion of the layer of material 43 is located on the sidewalls of the trench 31 and forms the flow channel 50, and another portion of the layer of material 43 is located between the first substrate 21 and the second substrate 47. In this embodiment, the first substrate 21 is bonded to the second substrate 47 through the layer of material 43, as shown in fig. 18. The flow channel structure device shown in fig. 18 is different from the flow channel structure device shown in fig. 10 in that: the flow channel structure device shown in fig. 18 does not include a sacrificial layer.
Fig. 19 is a cross-sectional view schematically illustrating a structure at a stage in the fabrication of a flow channel structure device according to another embodiment of the present invention.
In one embodiment of the present invention, the manufacturing method may include: after removing the second portion 452 of the sacrificial layer 45, bonding the portion of the material layer 43 outside the first trench 31 with the second substrate 47; next, the back surface of the first substrate 21 is subjected to thinning treatment, for example, by a CMP process, to expose the first portion 451 of the sacrificial layer 45; next, forming a cap layer 60 on the back side of the first substrate 21 after the thinning process, wherein the cap layer covers the runner 50; the first portion 451 of the sacrificial layer 45 is then removed using a selective etching process, thereby forming the flow channel 50, as shown in fig. 19.
By the above manufacturing method, a flow channel structure device as shown in fig. 19 is also formed. In an embodiment of the present invention, except that the flow channel structure device shown in fig. 19 has the same or similar structure as the flow channel structure device shown in fig. 18 (which is not described again), the flow channel structure device shown in fig. 19 differs from the flow channel structure device shown in fig. 18 in that: the flow channel structure device shown in fig. 19 may further include: and a cap layer 60 on the first substrate 21, wherein the cap layer 60 covers the runner 50. In addition, the capping layer may also cover the material layer 43.
Thus, fabrication methods and flow channel structure devices formed by these fabrication methods are provided according to some embodiments of the present invention. The flow channels of embodiments of the invention may be nanochannels. The invention has the following advantages: (1) the nano flow channel structure with high depth-width ratio can be realized, and the size controllability is good; (2) the mosaic structure of the all-metal conductive electrode can be realized; (3) the manufacturability of the nano flow channel structure can be effectively improved, and the manufacturing cost of the nano flow channel structure is reduced; (4) has low thermal budget and is compatible with integrated circuit technology.
In some embodiments of the present invention, the flow channel structure device may have a damascene electrode structure, and may have different biochemical analysis and fluid processing functions. For example, electrical or electrochemical reactions can occur in the flow channel by applying electrical excitation through the electrodes, electrical or optical signals can be generated, and specific molecular species can be identified through the acquired electrical or optical signals; still further, by identifying a variety of different molecular species, functions such as gene sequencing can be achieved.
In an embodiment of the invention, a flow channel sensor is also provided. The flow channel sensor may include: a flow channel structure device as hereinbefore described (e.g. as shown in figure 10, figure 11, figure 13, figure 18 or figure 19).
In an embodiment of the present invention, there is also provided a biochemical analysis apparatus. The biochemical analysis apparatus may include: a flow channel structure device as hereinbefore described (e.g. as shown in figure 10, figure 11, figure 13, figure 18 or figure 19).
FIG. 20 is a structural view schematically showing a chip for molecular detection according to an embodiment of the present invention. As shown in fig. 20, the chip 200 may include: a flow channel structure device 2001, a signal collection unit 2002, and a signal processing unit 2003. The flow channel structure device 2001 includes electrodes. The flow channel structure device may be, for example, a flow channel structure device as shown in fig. 10, 11, 13, 18 or 19. The sample to be detected is added into the flow channel of the flow channel structure device, and under the condition that the electrode of the flow channel structure device is applied with electric excitation, the target molecules in the sample to be detected generate electric signals or optical signals under the action of electric excitation.
The signal collection unit 2002 may be configured to collect the electrical signal or the optical signal and transmit the electrical signal or the optical signal to the signal processing unit 2003.
The signal processing unit 2003 may be used to perform signal processing on the electrical signal or the optical signal to identify information of the target molecule.
In the embodiment of the invention, a molecular detection method is also provided. The method can comprise the following steps: the molecular assay was performed using a chip as described previously (e.g., a chip as shown in FIG. 20).
FIG. 21 is a flow chart illustrating a method of molecular detection according to one embodiment of the present invention. The procedure of molecular detection using the chip is described below with reference to FIG. 21.
In step S2101, a sample to be detected is processed. For example, the sample to be tested may be subjected to chemical or other treatment.
In step S2102, a sample to be detected is added to the chip. For example, a sample to be tested is added to the flow channel of the flow channel structure device of the chip.
In step S2103, an electrical excitation is applied to the electrodes in the flow channel structure device in the chip, so that the target molecules in the sample to be detected generate an electrical signal or an optical signal under the electrical excitation.
In step S2104, the signal processing unit of the chip obtains the electrical signal or the optical signal through the signal collecting unit, and performs signal processing on the electrical signal or the optical signal to identify information of the target molecule.
In the above embodiments, the application of molecular detection is realized by using a chip including the flow channel structure device of the embodiments of the present invention.
Thus far, the present invention has been described in detail. Some details well known in the art have not been described in order to avoid obscuring the concepts of the present invention. It will be fully apparent to those skilled in the art from the foregoing description how to practice the presently disclosed embodiments.
Although some specific embodiments of the present invention have been described in detail by way of illustration, it should be understood by those skilled in the art that the above illustration is only for the purpose of illustration and is not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (23)
1. A method of fabricating a flow channel structure device, comprising:
providing a first substrate;
forming a first trench in the first substrate;
forming a material layer on the first substrate, wherein a portion of the material layer is formed in the first trench to form a second trench;
forming a sacrificial layer on the material layer, the sacrificial layer including a first portion filled in the second trench;
bonding the first substrate and the second substrate after the sacrificial layer is formed, so that the material layer is located between the first substrate and the second substrate;
thinning the back surface of the first substrate to expose a first part of the sacrificial layer; and
and removing the first part by using a selective etching process so as to form the flow channel.
2. The method of claim 1,
in the step of thinning the back surface of the first substrate, the material layer is also exposed;
before removing the first portion using a selective etch process, the method further comprises: and forming a cap layer on the back side of the thinned first substrate, wherein the cap layer covers the first part of the sacrificial layer.
3. The method of claim 2,
the material of the cap layer comprises: an insulating dielectric material or a semiconductor material;
the cap layer has a thickness in a range from 1 nanometer to 10 micrometers.
4. The method of claim 2,
and in the step of removing the first part by using a selective etching process, injecting selective etching liquid from the side surface of the edge of the second groove to remove the first part.
5. The method of claim 2,
before removing the first portion using a selective etch process, the method further comprises: etching the cap layer to form a through hole which penetrates through the cap layer and exposes the first part;
wherein, in the step of removing the first portion by using a selective etching process, a selective etching liquid is injected from the through hole to remove the first portion.
6. The method according to claim 1 or 2,
in the step of forming a sacrificial layer on the material layer, the sacrificial layer further includes: a second portion formed outside the second trench.
7. The method of claim 6,
and bonding the second portion of the sacrificial layer to the second substrate in the step of bonding the first substrate after the formation of the sacrificial layer to the second substrate.
8. The method of claim 6,
in the step of forming a material layer on the first substrate, another part of the material layer is formed outside the first trench;
before bonding the first substrate and the second substrate after forming the sacrificial layer, the method further comprises: removing the second portion of the sacrificial layer to expose a portion of the material layer outside the first trench;
and bonding the part of the material layer outside the first groove and the second substrate in the step of bonding the first substrate and the second substrate after the sacrificial layer is formed.
9. The method of claim 6,
in the step of removing the first portion using a selective etching process, the selective etching process also removes a portion of the second portion corresponding to the flow channel, thereby disconnecting the second portion.
10. The method of claim 1, wherein the step of forming a first trench in the first substrate comprises:
forming a patterned mask layer on the first substrate;
etching the first substrate by taking the mask layer as a mask to form a first groove; and
and removing the mask layer.
11. The method of claim 1,
the material of the material layer comprises: a metallic material or a semiconductor material;
wherein a portion of the material layer in the first trench serves as an electrode of the flow channel structure device; the portion of the material layer between the first substrate and the second substrate serves as a lead of the electrode.
12. The method of claim 1,
the material of the material layer comprises: an insulating dielectric material.
13. The method of claim 1,
the width range of the first groove is 10 nanometers to 100 micrometers, and the depth range of the first groove is 10 nanometers to 1 millimeter;
the thickness of the material layer ranges from 1 nanometer to 50 micrometers;
the width range of the flow channel is 0.1 nanometer to 1 micrometer;
the thickness of the sacrificial layer is larger than one half of the width of the flow channel.
14. A flow channel structure device, comprising:
a first substrate formed with a trench penetrating the first substrate;
a second substrate bonded to the first substrate;
a material layer, wherein one part of the material layer is positioned on the side wall of the groove and forms a flow channel, and the other part of the material layer is positioned between the first substrate and the second substrate, wherein the material of the material layer comprises an insulating medium material; and
a sacrificial layer between the material layer and the second substrate, wherein the sacrificial layer is broken at a position corresponding to the flow channel, and the material of the sacrificial layer includes: a metallic material or a semiconductor material.
15. The flow channel structure device according to claim 14, further comprising:
and the cover cap layer is arranged on the first substrate, and covers the flow channel.
16. The flow channel structure device according to claim 15,
the material of the cap layer comprises: an insulating dielectric material or a semiconductor material;
the cap layer has a thickness in a range from 1 nanometer to 10 micrometers.
17. The flow channel structure device according to claim 15, further comprising:
and the through hole penetrates through the cap layer and is communicated with the flow channel.
18. The flow channel structure device according to claim 14,
the width range of the groove is 10 nanometers to 100 micrometers, and the depth range of the groove is 10 nanometers to 1 millimeter;
the thickness of the material layer ranges from 1 nanometer to 50 micrometers;
the width range of the flow channel is 0.1 nanometer to 1 micrometer;
the thickness of the sacrificial layer is larger than one half of the width of the flow channel.
19. A flow channel sensor, comprising: a flow-channel structure device according to any of claims 14 to 18.
20. A biochemical analysis apparatus, characterized by comprising: a flow-channel structure device according to any of claims 14 to 18.
21. A chip for molecular detection, comprising: a flow channel structure device according to claim 14, a signal collection unit and a signal processing unit;
the method comprises the following steps that a sample to be detected is added into a flow channel of a flow channel structure device, and under the condition that an electrode of the flow channel structure device is applied with electric excitation, target molecules in the sample to be detected generate electric signals or optical signals under the action of the electric excitation;
the signal collecting unit is used for collecting the electric signal or the optical signal and transmitting the electric signal or the optical signal to the signal processing unit;
the signal processing unit is used for carrying out signal processing on the electric signal or the optical signal and identifying the information of the target molecule.
22. A method of molecular detection, comprising: molecular detection using the chip of claim 21.
23. The method of claim 22, wherein the step of performing molecular detection using the chip comprises:
processing a sample to be detected;
adding the sample to be detected into the chip;
applying electric excitation to electrodes in a flow channel structure device in the chip to enable target molecules in the sample to be detected to generate an electric signal or an optical signal under the action of the electric excitation; and
the signal processing unit of the chip obtains the electric signal or the optical signal through the signal collecting unit, and performs signal processing on the electric signal or the optical signal to identify the information of the target molecule.
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| CN113237932B (en) * | 2021-05-07 | 2023-09-19 | 中国工程物理研究院电子工程研究所 | Preparation method of counter electrode type nano electric sensor |
| WO2023123314A1 (en) * | 2021-12-31 | 2023-07-06 | 京东方科技集团股份有限公司 | Micro/nanofluidic substrate, chip, preparation method and system |
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| CN105158310A (en) * | 2015-09-21 | 2015-12-16 | 东南大学 | Microfluidic detection chip based on micropore electrode and application thereof |
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| CN110753580A (en) | 2020-02-04 |
| WO2019023945A1 (en) | 2019-02-07 |
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